Chip packaging structure and chip packaging product
By deflecting the cleavage plane angle of the bare chip in the chip package structure and optimizing the pin layout, as well as using dammed areas and protective layers, the stress resistance and signal stability issues of the chip package structure are solved, thereby improving its reliability and performance.
Patent Information
- Application Number
- CN202423261632.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2034-12-27
AI Technical Summary
As chip functional requirements increase, wiring becomes more complex and the area of bare chips increases, the basic performance of chip packaged products decreases and their resistance to triple stress weakens, affecting their reliability.
By deflecting the cleavage surface of the bare chip by a preset angle relative to the preset stress direction, optimizing the distance layout between the ground pin and the input/output pin, and employing a dammed area and protective layer structure, the stress resistance and signal transmission stability of the chip package are enhanced.
It improves the stress resistance and electrical performance of the chip packaging structure, ensures the stability and accuracy of signal transmission, and enhances the reliability of the chip packaging structure in actual use.
Smart Images
Figure CN223786403U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip packaging, for example to a chip packaging structure and a chip packaging product. BACKGROUND
[0002] The chip packaging product refers to fixing a die through a series of processes such as die mounting, wire bonding, encapsulation, etc., on a substrate which plays a role of bearing, and leading out pins or leads, and finally assembling into a chip product with specific functions.
[0003] With the increasing functional requirements of the chip product, the wiring in the chip product is more and more complex, and the area occupied by the die is larger and larger. With the increasing complexity of the wiring and the gradual increase of the area of the die, the basic performance of the chip packaging product is reduced, and the three-wheel stress resistance is weakened, so that the reliability of the chip packaging product in the actual use process is low.
[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information which does not constitute prior art known to those of ordinary skill in the art. CONTENT OF THE INVENTION
[0005] In order to have a basic understanding of some aspects of the disclosed embodiments, the following is a simple summary. The summary is not a general review, nor is it intended to determine the key / important components or delineate the scope of protection of these embodiments, but as a prelude to the detailed description below.
[0006] The chip packaging structure and the chip packaging product provided by the embodiments of the present application can improve the performance and the three-wheel stress resistance of the chip packaging structure, so that the reliability of the chip packaging structure in the actual use process is higher.
[0007] In some embodiments, a chip packaging structure is provided, comprising: a substrate comprising ground pins and input / output pins arranged at intervals; a die arranged on the substrate, and a cleavage surface of the die being deflected by a preset angle relative to a preset stress direction, the die comprising ground pads and input / output pads arranged at intervals, the ground pads being arranged in connection with the ground pins, and the input / output pads being arranged in connection with the input / output pins; and wherein a distance from the ground pins to the ground pads is less than a distance from the input / output pins to the input / output pads.
[0008] Optionally, the substrate further comprises serial interface input / output pins arranged at intervals with the ground pins and the input / output pins; and the die further comprises serial interface input / output pads arranged at intervals with the ground pads and the input / output pads, the serial interface input / output pads being arranged in connection with the serial interface input / output pins.
[0009] Optionally, the substrate further comprises a clock signal input pin spaced apart from the ground pin and the input / output pin; and the bare chip further comprises a clock signal input pad spaced apart from the ground pad and the input / output pad, the clock signal input pad being connected to the clock signal input pin.
[0010] Optionally, the substrate further comprises a reset signal input pin spaced apart from the ground pin and the input / output pin; and the bare chip further comprises a reset signal input pad spaced apart from the ground pad and the input / output pad, the reset signal input pad being connected to the reset signal input pin.
[0011] Optionally, the substrate further comprises a power voltage input pin spaced apart from the ground pin and the input / output pin; and the bare chip further comprises a power voltage input pad spaced apart from the ground pad and the input / output pad, the power voltage input pad being connected to the power voltage input pin.
[0012] Optionally, the substrate comprises a clock signal input pin and a power voltage input pin spaced apart from the ground pin and the input / output pin; and the bare chip comprises a clock signal input pad and a power voltage input pad spaced apart from the ground pad and the input / output pad; wherein a distance from the clock signal input pin to the clock signal input pad is less than a distance from the power voltage input pin to the power voltage input pad.
[0013] Optionally, the preset angle is 30° to 60°.
[0014] Optionally, the substrate comprises a mounting area, and the ground pin and the input / output pin are located in the mounting area; the bare chip comprises oppositely arranged first and second surfaces, and the bare chip is arranged in the mounting area with the first surface facing the substrate, and the ground pad and the input / output pad are located on the second surface; the chip packaging structure further comprises a dam area and a protective layer, the dam area covers the side surface of the bare chip and part of the mounting area along the circumference of the bare chip, and the protective layer covers the second surface of the bare chip and the surface of the dam area; wherein the hardness of the dam area is greater than the hardness of the protective layer.
[0015] Optionally, the dam area is formed by curing damming glue; and / or the protective layer is formed by curing ultraviolet curing glue.
[0016] Optionally, the chip packaging structure further comprises a buffer layer arranged in the mounting area; wherein the first surface of the bare chip is arranged on a side of the buffer layer away from the substrate.
[0017] Optionally, the cross-sectional area of the buffer layer parallel to the substrate is greater than the cross-sectional area of the bare chip parallel to the substrate.
[0018] Optionally, the buffer layer covers part of the side surface of the bare chip along the circumference of the bare chip; the height of the dam region is greater than the height of the buffer layer, and the dam region covers the side surface of the buffer layer, part of the side surface of the bare chip and part of the mounting region along the circumference of the bare chip.
[0019] In some embodiments, a chip packaging product is provided, comprising: a chip packaging structure as described in the above embodiments.
[0020] The chip packaging structure and the chip packaging product provided by the embodiments of the present disclosure can achieve the following technical effects:
[0021] In the embodiments of the present disclosure, by setting the cleavage surface of the bare chip to be deflected by a preset angle relative to the preset stress direction, when the chip packaging structure is subjected to stress, the stress will not directly propagate along the cleavage surface of the bare chip, thereby reducing the risk of the bare chip breaking due to the weakness of the cleavage surface, improving the stress resistance of the chip packaging structure, and effectively reducing the chip damage caused by stress concentration. In addition, after the cleavage surface of the bare chip is deflected by a preset angle relative to the preset stress direction, the distance from the ground pin to the ground pad is less than the distance from the input / output pin to the input / output pad, so that the voltage drop of the ground signal in the transmission process is relatively small, so as to maintain the stability and accuracy of the ground signal, reduce the attenuation and interference of the signal in the transmission process. The chip packaging structure of the present disclosure can make the signal more accurately transmitted from the bare chip to the external circuit, thereby improving the electrical performance of the entire chip packaging structure. In summary, the embodiments of the present disclosure can improve the performance and three-wheel stress resistance of the chip packaging structure, so that the reliability of the chip packaging structure in actual use is higher.
[0022] The foregoing general description and the following description are only exemplary and explanatory, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS
[0023] One or more embodiments are exemplarily illustrated by corresponding drawings, which do not constitute limitation on the embodiments, elements with the same reference numerals in the drawings are shown as similar elements, the drawings do not constitute proportional limitation, and wherein:
[0024] Figure 1 is a structural schematic diagram of a chip packaging structure provided by one embodiment of the present disclosure;
[0025] Figure 2 is a structural schematic diagram of a chip packaging structure without deflection of the cleavage surface relative to the preset stress direction;
[0026] Figure 3 is a structural schematic diagram of a chip packaging structure provided by another embodiment of the present disclosure;
[0027] Figure 4 is a structural diagram of a chip packaging structure provided by another embodiment of the present disclosure;
[0028] Figure 5 is a structural diagram of a chip packaging structure provided by another embodiment of the present disclosure;
[0029] Figure 6 is a sectional view of a conventional chip packaging product;
[0030] Figure 7 is a structural diagram of a chip packaging product provided by an embodiment of the present disclosure;
[0031] Figure 8 is a schematic diagram of a chip packaging method provided by an embodiment of the present disclosure;
[0032] Figure 9 is a schematic diagram of a chip packaging method provided by another embodiment of the present disclosure;
[0033] Figure 10 is a schematic diagram of a conventional dispensing method in which glue is dispensed on a substrate;
[0034] Figure 11 is a schematic diagram of a conventional dispensing method in which glue overflows the four edges of a bare chip;
[0035] Figure 12 is a schematic diagram of a method of dispensing glue on a substrate using a cross-shaped dispensing method according to an embodiment of the present disclosure;
[0036] Figure 13 is a schematic diagram of a method of dispensing glue on a substrate using a cross-shaped dispensing method according to an embodiment of the present disclosure;
[0037] Figure 14 is a schematic diagram of a method of dispensing glue on a substrate using a cross-shaped dispensing method according to an embodiment of the present disclosure;
[0038] Figure 15 is a schematic diagram of a chip packaging method provided by another embodiment of the present disclosure.
[0039] Reference Signs:
[0040] 1 chip packaging product;
[0041] 10 chip package structure; 100 substrate; 101 mounting area; 102 ground pin; 103 serial interface input / output pin; 104 input / output pin; 105 clock signal input pin; 106 reset signal input pin; 107 power voltage input pin; 200 bare chip; 201 first surface; 202 second surface; 203 first side; 204 second side; 205 ground solder joint; 206 serial interface input / output solder joint; 207 input / output solder joint; 208 clock signal input solder joint; 209 reset signal input solder joint; 210 power voltage input solder joint; 300 dam area; 400 protective layer; 500 buffer layer;
[0042] 200' bare chip; 400' plastic encapsulation layer. DETAILED DESCRIPTION
[0043] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be simplified to facilitate the drawings.
[0044] The terms "first", "second", and the like in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.
[0045] In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "back", and the like indicate the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the embodiments of the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components must have a specific orientation, or be constructed and operated in a specific orientation. In addition, in addition to indicating the orientation or positional relationship, the above-mentioned terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain attachment relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the embodiments of the present disclosure can be understood according to the specific circumstances.
[0046] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.
[0047] Unless otherwise stated, the term "multiple" means two or more.
[0048] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0049] The term "and / or" describes an association between objects, indicating that there can be three relationships. For example, A and / or B means that there are three relationships: A, B, and A and B.
[0050] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.
[0051] In some embodiments, combined with Figure 1 and Figure 3 As shown, a chip package structure 10 is provided, including a substrate 100 and a bare chip 200. The substrate 100 includes a ground pin 102 and an input / output pin 104 spaced apart. The bare chip 200 is disposed on the substrate 100, and the cleavage surface of the bare chip 200 is deflected by a preset angle relative to a preset stress direction. Ground solder joints 205 and input / output solder joints 207 are spaced apart on the bare chip 200. The ground solder joints 205 are connected to the ground pins 102, and the input / output solder joints 207 are connected to the input / output pins 104. The distance from the ground pins 102 to the ground solder joints 205 is less than the distance from the input / output pins 104 to the input / output solder joints 207.
[0052] Cleavage surfaces (e.g.) Figure 1 The dotted line with double-headed arrows (as shown in the image) represents a special plane in crystalline materials, signifying an ordered arrangement of atoms within the crystal. This plane is the surface of the chip that is prone to breakage due to stress. In the chip packaging structure 10 provided in this embodiment, the preset stress direction refers to the direction of stress experienced by the chip packaging structure 10 during three rounds of testing. By setting a preset angle θ to deflect the cleavage surface of the bare chip 200 relative to the preset stress direction, stress will not propagate directly along the cleavage surface of the bare chip 200 when the chip packaging structure 10 is subjected to stress. This reduces the risk of the bare chip 200 breaking due to the fragility of the cleavage surface, improves the stress resistance of the chip packaging structure 10, and effectively reduces chip damage caused by stress concentration.
[0053] In addition, the ground pin 102, i.e., the GND (Ground) pin, represents the ground or 0 line, and is used to connect the common end or reference ground of the circuit to provide a stable potential reference for the bare chip 200. The input / output pin 104, i.e., the IO (Input / Output) pin, is connected with the input / output pad 207, and is used for input and output of data, signals or power supply with the bare chip 200. In the embodiment of the present disclosure, after the cleavage surface of the bare chip 200 is deflected by a preset angle relative to the preset stress direction, the distance from the ground pin 102 to the ground pad 205 is less than the distance from the input / output pin 104 to the input / output pad 207, so that the voltage drop of the ground signal in the transmission process is relatively small, so as to maintain the stability and accuracy of the ground signal, and reduce the attenuation and interference of the signal in the transmission process. The chip packaging structure 10 of the embodiment of the present disclosure can make the signal more accurately transmitted from the bare chip 200 to the external circuit, thereby improving the electrical performance of the entire chip packaging structure 10.
[0054] In summary, the embodiment of the present disclosure can improve the performance and three-wheel stress resistance of the chip packaging structure 10, so that the reliability of the chip packaging structure 10 in actual use is higher.
[0055] In order to more clearly illustrate the embodiment of the present disclosure, a rectangular coordinate system is constructed on the substrate 100 to explain the chip packaging structure 10 provided by the embodiment of the present disclosure.
[0056] Specifically, the schematic diagram of the chip packaging structure 10 without the cleavage surface deflected by a preset angle relative to the preset stress direction is as shown in FIG. 2. Figure 2As shown. The substrate 100 includes ground pins 102 and input / output pins 104 arranged at intervals. The bare chip 200 includes a first side 203 and a second side 204 located at opposite sides of a cleavage plane, respectively. The bare chip 200 is provided with a plurality of solder joints for connecting the pins near the first side 203 and the second side 204. The bare chip 200 is arranged on the substrate 100, and the midpoint of the bare chip 200 coincides with the midpoint of the substrate 100. A rectangular coordinate system is constructed along a plane parallel to the substrate 100, including a vertical coordinate axis y and a horizontal coordinate axis x. The vertical coordinate axis y coincides with and is in the same direction as the axis of the predetermined stress direction, and the horizontal coordinate axis x extends in the direction from the first side 203 to the second side 204, and is perpendicular to the vertical coordinate axis y through the midpoint of the substrate 100 and / or the bare chip 200. The bare chip 200 is arranged at intervals with ground solder joints 205 and input / output solder joints 207. The ground solder joints 205 are arranged in connection with the ground pins 102, and the input / output solder joints 207 are arranged in connection with the input / output pins 104. The ground pins 102 and the ground solder joints 205 are located in the fourth quadrant of the rectangular coordinate system, the input / output pins 104 are located in the first quadrant of the rectangular coordinate system, and the ground pins 102 and the input / output pins 104 are symmetrical with respect to the horizontal coordinate axis x. Since the connecting lines between the pins and the solder joints cannot cross the chip, the input / output pins 104 are arranged in connection with the input / output solder joints 207 on the bare chip 200 which are also located in the first quadrant. At this time, the distance from the ground pins 102 to the ground solder joints 205 is equal to the distance from the input / output pins 104 to the input / output solder joints 207.
[0057] The chip packaging structure 10 of the embodiment of the present disclosure is as shown in Figure 1As shown, the substrate 100 includes a ground pin 102 and an input / output pin 104 arranged at intervals. The bare chip 200 includes a first side 203 and a second side 204 located on opposite sides of the cleavage plane, respectively. The bare chip 200 is arranged on the substrate 100, and the midpoint of the bare chip 200 coincides with the midpoint of the substrate 100. A rectangular coordinate system is constructed along a plane parallel to the substrate 100, including a vertical coordinate axis y and a horizontal coordinate axis x. The vertical coordinate axis y coincides with and is in the same direction as the axis of the predetermined stress direction, and the horizontal coordinate axis x extends in the direction from the first side 203 to the second side 204, and is perpendicular to the vertical coordinate axis y through the midpoint of the substrate 100 and / or the bare chip 200. Then, the cleavage plane of the bare chip 200 is deflected by a predetermined angle θ with respect to the vertical coordinate axis y. The ground pads 205 and the input / output pads 207 are arranged at intervals on the bare chip 200, the ground pads 205 are arranged in connection with the ground pin 102, and the input / output pads 207 are arranged in connection with the input / output pin 104. With the cleavage plane deflected by the predetermined angle θ with respect to the vertical coordinate axis y, the ground pad 205 in the fourth quadrant on the bare chip 200 is further deflected by the predetermined angle θ with respect to the horizontal coordinate axis x in the direction of the ground pin 102, so that the distance between the ground pin 102 and the ground pad 205 after deflection is smaller than the distance between the ground pin 102 and the ground pad 205 before deflection. At the same time, the input / output pin 104 is arranged in connection with the input / output pad 207 on the bare chip 200 in the second quadrant, and the distance between the input / output pin 104 and the input / output pad 207 after deflection is greater than the distance between the input / output pin 104 and the input / output pad 207 before deflection. In summary, after the cleavage plane is deflected by the predetermined angle with respect to the predetermined stress direction, the distance between the ground pin 102 and the ground pad 205 is smaller than the distance between the input / output pin 104 and the input / output pad 207.
[0058] The ground is the most likely place to generate noise and interference in the circuit. By reducing the distance of the connecting line between the ground pin 102 and the ground pad 205, the resistance and voltage drop between the ground pin 102 and the ground pad 205 are reduced, thereby reducing signal noise and interference, improving the signal-to-noise ratio of the circuit, stabilizing the ground potential, reducing potential fluctuations caused by poor grounding, and improving signal stability. By reducing the resistance and voltage drop of the connecting line between the ground pin 102 and the ground pad 205, the circuit performance of the chip packaging structure 10 is enhanced.
[0059] Alternatively, in combination with Figure 1 and Figure 3As shown, the substrate 100 further comprises a clock signal input pin 105 which is arranged apart from the ground pin 102 and the input / output pin 104. The die 200 is further provided with a clock signal input pad 208 which is arranged apart from the ground pad 205 and the input / output pad 207, and the clock signal input pad 208 is connected to the clock signal input pin 105.
[0060] The clock signal input pin 105, i.e. the CLK (Clock) pin, is used to receive a clock signal provided by an external crystal oscillator or oscillator, so as to synchronize the operation of various modules in the chip and ensure that they perform tasks in the correct time sequence. In this embodiment, the clock signal input pad 208 is connected to the clock signal input pin 105 on the substrate 100, so as to ensure that the clock signal can be accurately transmitted to the inside of the die 200, ensure the accuracy of the timing logic inside the die 200, and thus reduce data conflicts, improve data transmission efficiency, and improve the overall performance of the chip packaging structure 10.
[0061] Optionally, in combination with Figure 1 and Figure 3 As shown, the substrate 100 further comprises a reset signal input pin 106 which is arranged apart from the ground pin 102 and the input / output pin 104. The die 200 is further provided with a reset signal input pad 209 which is arranged apart from the ground pad 205 and the input / output pad 207, and the reset signal input pad 209 is connected to the reset signal input pin 106.
[0062] The reset signal input pin 106, i.e. the RST (Reset) pin, is used to restore the chip to the initial state. The reset signal is crucial to ensure the stable operation of the system. In the event of an exception or failure, an external reset signal can quickly reset the system to the initial state, thereby avoiding system crashes or entering an unknown state. In this embodiment, the reset signal input pad 209 is connected to the reset signal input pin 106 on the substrate 100, so as to ensure that the reset signal can be accurately and reliably transmitted to the inside of the die 200, thereby avoiding the chip packaging structure 10 from crashing or entering an unknown state.
[0063] Optionally, in combination with Figure 1 and Figure 3 As shown, the substrate 100 further comprises a power voltage input pin 107 which is arranged apart from the ground pin 102 and the input / output pin 104. The die 200 is further provided with a power voltage input pad 210 which is arranged apart from the ground pad 205 and the input / output pad 207, and the power voltage input pad 210 is connected to the power voltage input pin 107.
[0064] The power voltage input pin 107, i.e. the VCC (Voltage Common Collector) pin, is used to connect the positive pole of an external power supply to provide the required DC power supply for the chip. The VCC pin is the basis for the normal operation of the chip. In this embodiment, the power voltage input pad 210 is connected to the power voltage input pin 107 on the substrate 100, ensuring that the power voltage can be stably and reliably transmitted to the internal circuit of the bare chip 200, ensuring that the bare chip 200 obtains stable and reliable power voltage, thereby maintaining the normal working state of the chip packaging structure 10.
[0065] In some embodiments, in combination with Figure 1 and Figure 3 As shown, the substrate 100 includes a clock signal input pin 105 and a power voltage input pin 107 arranged apart from the ground pin 102 and the input / output pin 104. The bare chip 200 includes a clock signal input pad 208 and a power voltage input pad 210 arranged apart from the ground pad 205 and the input / output pad 207. Among them, the distance from the clock signal input pin 105 to the clock signal input pad 208 is less than the distance from the power voltage input pin 107 to the power voltage input pad 210.
[0066] In this embodiment, the distance from the clock signal input pin 105 to the clock signal input pad 208 is less than the distance from the power voltage input pin 107 to the power voltage input pad 210. By preferentially reducing the distance from the clock signal input pin 105 to the clock signal input pad 208, the attenuation and interference of the clock signal in the transmission process can be reduced, so as to maintain the stability and accuracy of the clock signal, ensure the accurate execution of the internal timing logic of the chip, and make the bare chip 200 can process data more efficiently, improve the performance of the entire chip packaging structure 10.
[0067] Specifically, the schematic diagram of the chip packaging structure 10 whose cleavage plane is deflected by a preset angle relative to the preset stress direction is as shown in Figure 2As shown. The substrate 100 includes a clock signal input pin 105 and a power voltage input pin 107 arranged at intervals. The bare chip 200 includes a first side 203 and a second side 204 located at opposite sides of the cleavage plane, respectively. The bare chip 200 is arranged on the substrate 100, and the midpoint of the bare chip 200 coincides with the midpoint of the substrate 100. A rectangular coordinate system is constructed along a plane parallel to the substrate 100, and the rectangular coordinate system includes a vertical coordinate axis y and a horizontal coordinate axis x. The vertical coordinate axis y coincides with and is in the same direction as the axis of the preset stress direction, and the horizontal coordinate axis x extends in the direction from the first side 203 to the second side 204, and is perpendicular to the vertical coordinate axis y through the midpoint of the substrate 100 and / or the bare chip 200. The clock signal input pad 208 and the power voltage input pad 210 are arranged at intervals on the bare chip 200, the clock signal input pad 208 is arranged in connection with the clock signal input pin 105, and the power voltage input pad 210 is arranged in connection with the power voltage input pin 107. The clock signal input pin 105 and the clock signal input pad 208 are located in the second quadrant of the rectangular coordinate system, the power voltage input pin 107 is located in the third quadrant of the rectangular coordinate system, and the clock signal input pin 105 and the power voltage input pin 107 are symmetrical with respect to the horizontal coordinate axis x. The power voltage input pin 107 is arranged in connection with the power voltage input pad 210 on the bare chip 200 which is also located in the third quadrant. At this time, the distance from the clock signal input pin 105 to the clock signal input pad 208 is equal to the distance from the power voltage input pin 107 to the power voltage input pad 210.
[0068] The chip packaging structure 10 of the embodiment of the present disclosure is as shown in Figure 1As shown, the substrate 100 includes a clock signal input pin 105 and a power voltage input pin 107 arranged at intervals. The bare chip 200 is arranged on the substrate 100, and the midpoint of the bare chip 200 coincides with the midpoint of the substrate 100. A rectangular coordinate system is constructed along a plane parallel to the substrate 100, and the rectangular coordinate system includes a vertical coordinate axis y and a horizontal coordinate axis x. The vertical coordinate axis y coincides with and is in the same direction as the axis of the preset stress direction, and the horizontal coordinate axis x extends in the direction from the first side 203 to the second side 204 and is perpendicular to the vertical coordinate axis y through the midpoint of the substrate 100 and / or the bare chip 200. Then, the cleavage surface of the bare chip 200 is deflected by a preset angle θ relative to the vertical coordinate axis y. The clock signal input pad 208 and the power voltage input pad 210 are arranged at intervals on the bare chip 200, and the clock signal input pad 208 is arranged in connection with the clock signal input pin 105, and the power voltage input pad 210 is arranged in connection with the power voltage input pin 107. With the cleavage surface deflected by the preset angle θ relative to the vertical coordinate axis y, the clock signal input pad 208 in the second quadrant on the bare chip 200 is further deflected by the preset angle θ relative to the horizontal coordinate axis x in the direction of the clock signal input pin 105, so that the distance between the clock signal input pin 105 and the clock signal input pad 208 after deflection is smaller than the distance between the clock signal input pin 105 and the clock signal input pad 208 before deflection. At the same time, the power voltage input pin 107 is arranged in connection with the power voltage input pad 210 in the second quadrant after deflection, and the distance between the power voltage input pin 107 and the power voltage input pad 210 after deflection is greater than the distance between the power voltage input pin 107 and the power voltage input pad 210 before deflection. In summary, after the cleavage surface is deflected by the preset angle relative to the preset stress direction, the distance between the clock signal input pin 105 and the clock signal input pad 208 is smaller than the distance between the power voltage input pin 107 and the power voltage input pad 210.
[0069] The clock signal input pin 105 is used to receive a clock signal provided by an external crystal oscillator or oscillator to synchronize the operation of various modules in the chip and ensure that they perform tasks in the correct time sequence. By reducing the distance between the clock signal input pin 105 and the clock signal input pad 208, the resistance and voltage drop between the clock signal input pad 208 and the clock signal input pin 105 are reduced, the delay and distortion of the clock signal in the transmission process are reduced, the timing synchronization accuracy of the chip packaging structure 10 is improved, the chip packaging structure 10 can process data more efficiently, and the reliability of the chip packaging structure 10 in actual use is further improved.
[0070] Optionally, the preset angle θ is 30° to 60°.
[0071] In this embodiment, by limiting the preset angle θ between the cleavage surface of the bare chip 200 and the preset stress direction to 30°-60°, the stress distribution of the bare chip 200 when subjected to external force is optimized, ensuring that the stress is no longer propagated along the cleavage surface, but dispersed to each part of the bare chip 200, reducing the risk of the bare chip 200 breaking due to stress concentration, and improving the stress resistance of the chip packaging structure 10. For example, the specific value of the preset angle θ is 30°, 45° or 60°.
[0072] In some embodiments, in combination with Figure 3 to Figure 5 As shown, the substrate 100 includes a mounting area 101, and the ground pin 102 and the input / output pin 104 are located in the mounting area 101. The bare chip 200 includes oppositely arranged first and second surfaces 201 and 202, and the bare chip 200 is arranged in the mounting area 101 with the first surface 201 facing the substrate 100. The ground pad 205 and the input / output pad 207 are located on the second surface 202. The chip packaging structure 10 further includes a dam area 300 and a protective layer 400. The dam area 300 covers the side surface of the bare chip 200 and part of the mounting area 101 along the circumference of the bare chip 200. The protective layer 400 covers the second surface 202 of the bare chip 200 and the surface of the dam area 300. The hardness of the dam area 300 is greater than that of the protective layer 400.
[0073] In this embodiment, the dam area 300 covers the side surface of the bare chip 200 and part of the mounting area 101 along the circumference of the bare chip 200, and the protective layer 400 covers the second surface 202 of the bare chip 200 and the surface of the dam area 300. The sealing of the bare chip 200 is realized by the combination of the dam area 300 and the protective layer 400, so as to protect the chip from the erosion of the external environment (such as humidity, temperature, dust, etc.), while providing electrical insulation and mechanical support. The hardness of the dam area 300 is greater than that of the protective layer 400, and the dam area 300 covers the side surface of the bare chip 200 along the circumference of the bare chip 200 to reinforce the periphery of the bare chip 200, especially to protect the corners of the bare chip 200, prevent damage caused by stress concentration on the corners, and support the protective layer 400. The protective layer 400 covers the second surface 202 of the bare chip 200 and the surface of the dam area 300, protects the surface of the bare chip 200 from scratching and contamination, and provides a buffering effect to reduce the impact of the external environment on the bare chip 200.
[0074] The chip packaging structure 10 provided by the embodiments of the present disclosure utilizes the high hardness and support of the dam area 300 and the buffering effect of the protective layer 400 to effectively resist the impact and damage of the external environment and protect the bare chip 200 from damage. It is not limited by the direction of stress. Therefore, in actual use, it has stronger stress resistance and higher reliability.
[0075] An exemplary cross-sectional view of a conventional chip packaging product is shown in Figure 6 The chip packaging structure 10 formed by the embodiments of the present disclosure is shown in Figure 4 and Figure 5 As can be seen by comparison, the distance a from the outer surface of the protective layer 400 to the bare chip 200 is greater than the distance b from the outer surface of the plastic encapsulation layer 400' to the bare chip 200' with the support of the dam area 300. In the embodiments of the present disclosure, the distance from the outer surface of the protective layer 400 to the bare chip 200 is increased by adding the dam area 300 and supporting the protective layer 400 with the support of the dam area 300, so that the protective layer 400 formed is more full, thereby enhancing the buffering effect of the chip packaging structure 10, and effectively resisting the impact and damage from the outside world without being limited by the direction of stress.
[0076] In this embodiment, the ground pins 102, the input / output pins 104, the serial interface input / output pins 103, the clock signal input pins 105, the reset signal input pins 106, and the power voltage input pins 107 are distributed at intervals in the mounting area 101. The ground pads 205, the input / output pads 207, the serial interface input / output pads 206, the clock signal input pads 208, the reset signal input pads 209, and the power voltage input pads 210 are distributed at intervals in the mounting area 101 and distributed at intervals on the second surface 202 of the bare chip 200.
[0077] Optionally, the height of the dam area 300 is greater than or equal to the height of the bare chip 200 in the height direction of the chip packaging structure 10.
[0078] In this embodiment, the height of the dam area 300 is limited to be greater than or equal to the height of the bare chip 200, so as to ensure that the dam area 300 can cover all the side surfaces of the bare chip 200, especially the corners of the bare chip 200, so as to better protect the bare chip 200 from the impact and damage from the outside world. At the same time, the extension of the dam area 300 in the height direction improves the support effect on the protective layer 400, further increases the distance from the outer surface of the protective layer 400 to the bare chip 200, and ensures that the protective layer 400 formed is more full, thereby improving the stress resistance of the chip packaging structure 10.
[0079] Optionally, the dam area 300 is formed by curing dam glue. Dam glue is a high-performance adhesive with good fluidity, bonding strength and curing performance. Dam glue can be cured by certain means (such as heat curing, ultraviolet curing, etc.). The cured dam glue has high strength and hardness, which can effectively protect the corners and edges of the bare chip 200. The dam area 300 formed by curing the dam glue not only provides additional mechanical support, but also disperses and absorbs external stress through the special adhesion and strength of the dam glue, further enhancing the stress resistance of the chip packaging structure 10.
[0080] Optionally, the protective layer 400 is formed by curing ultraviolet curing glue. Ultraviolet curing glue can be quickly cured under the irradiation of ultraviolet light, with the advantages of fast curing speed, low curing temperature, high strength after curing, high transparency, etc. The cured ultraviolet curing glue forms the protective layer 400, which can protect the chip from the erosion of the external environment (such as humidity, temperature, dust, etc.), while providing electrical insulation and mechanical support.
[0081] Optionally, the dam area 300 and the protective layer 400 are integrally formed. In this embodiment, the dam area 300 and the protective layer 400 are integrally formed to avoid adding additional packaging steps and ensure production efficiency. At the same time, there is no interface problem between the integrally formed dam area 300 and the protective layer 400, so the formed structure is more stable and reliable. It should be noted that in the embodiments of the present disclosure, the interface shown by the dashed line in Figure 4 and Figure 5 is to facilitate the distinction between the dam area 300 and the protective layer 400, and there is no interface shown by the dashed line in the actual product.
[0082] Optionally, in combination with Figure 3 , the protective layer 400 is polygonal in cross section parallel to the substrate 100.
[0083] In this embodiment, by limiting the protective layer 400 to be polygonal in cross section parallel to the substrate 100 instead of the traditional circular shape, the protective layer 400 can more evenly disperse stress when subjected to external force, enhancing the structural strength of the chip packaging structure 10. Compared with the traditional circular structure, the polygonal protective layer 400 has stronger structural strength at the corners, which helps to resist mechanical stress and thermal stress during packaging, thereby reducing damage and failure during packaging. The polygonal protective layer 400 forms a smooth transition at the corners, which can reduce the probability of stress concentration and reduce the failure and damage of the chip packaging structure 10 caused by stress concentration, prolonging the service life of the packaging structure. In summary, by designing the protective layer 400 to be polygonal in cross section parallel to the substrate 100, the stress resistance of the chip packaging structure 10 is further improved, and the reliability and stability of the chip packaging structure 10 are improved.
[0084] In some embodiments, the protection layer 400 has a pentagonal, hexagonal, heptagonal or octagonal cross section parallel to the substrate 100. In one practical application, as shown in FIG. 4A, the protection layer 400 has a hexagonal cross section parallel to the substrate 100. Figure 3
[0085] Optionally, as shown in FIG. 4B, the chip package structure 10 further comprises a buffer layer 500. The buffer layer 500 is disposed on the mounting area 101. The first surface 201 of the bare chip 200 is disposed on a side of the buffer layer 500 away from the substrate 100. Figure 4 Figure 5 Optionally, as shown in FIG. 4B, the chip package structure 10 further comprises a buffer layer 500. The buffer layer 500 is disposed on the mounting area 101. The first surface 201 of the bare chip 200 is disposed on a side of the buffer layer 500 away from the substrate 100.
[0086] In this embodiment, the buffer layer 500 is used to fix the mounting of the bare chip 200 and the substrate 100. At the same time, by disposing the buffer layer 500 between the bare chip 200 and the substrate 100, it plays the role of a "cushion". When the chip package structure 10 is subjected to external force impact or vibration, the buffer layer 500 can absorb and disperse these stresses, thereby protecting the bare chip 200 from damage, further improving the stress resistance of the chip package structure 10, and improving the stability and reliability of the chip package structure 10.
[0087] Optionally, as shown in FIG. 4B, the chip package structure 10 further comprises a buffer layer 500. The buffer layer 500 is disposed on the mounting area 101. The first surface 201 of the bare chip 200 is disposed on a side of the buffer layer 500 away from the substrate 100. Figure 3 In this embodiment, by limiting the cross-sectional area of the buffer layer 500 parallel to the substrate 100 to be greater than the cross-sectional area of the bare chip 200 parallel to the substrate 100, the buffer layer 500 can completely cover the first surface 201 of the bare chip 200, thereby providing a larger protection area for the bare chip 200, achieving more comprehensive and stable support for the bare chip 200, and reducing the risk of chip damage or failure due to stress concentration during the packaging process or use.
[0088] It should be noted that,
[0089] In the above embodiments, the circular shaded area represents the buffer layer 500 in the top view, and the polygonal shaded area represents the protection layer 400 in the top view. Figure 3 Optionally, as shown in FIG. 4B, the chip package structure 10 further comprises a buffer layer 500. The buffer layer 500 is disposed on the mounting area 101. The first surface 201 of the bare chip 200 is disposed on a side of the buffer layer 500 away from the substrate 100.
[0090] Figure 4 Optionally, as shown in FIG. 4B, the chip package structure 10 further comprises a buffer layer 500. The buffer layer 500 is disposed on the mounting area 101. The first surface 201 of the bare chip 200 is disposed on a side of the buffer layer 500 away from the substrate 100. Figure 5 In this embodiment, the buffer layer 500 covers part of the side surface of the bare chip 200 along the circumference of the bare chip 200. The height of the dam area 300 is greater than the height of the buffer layer 500, and the dam area 300 covers the side surface of the buffer layer 500, part of the side surface of the bare chip 200 and part of the mounting area 101 along the circumference of the bare chip 200.
[0091] In this embodiment, the buffer layer 500 covers part of the side surface of the bare chip 200 along the circumferential direction of the bare chip 200. The height of the dam region 300 is greater than the height of the buffer layer 500, so that the dam region 300 can cover part of the side surface of the bare chip 200 on the basis of covering the side surface of the buffer layer 500. By the buffer layer 500 and the dam region 300 jointly covering the side surface of the bare chip 200, the periphery of the bare chip 200 is protected, especially the corners of the bare chip 200, to prevent damage caused by stress concentration on the corners. By limiting the buffer layer 500 to cover part of the side surface of the bare chip 200, it is ensured that the buffer layer 500 is full, so that the buffer layer 500 can play a buffering role in the process of stress pressing, protecting the bare chip 200 from damage and improving the stress resistance of the chip packaging structure 10.
[0092] As shown in Figure 4 and Figure 5 , along the height direction of the chip packaging structure 10, the height of the dam region 300 is m, the height of the buffer layer 500 is q, and m>q.
[0093] In some embodiments, in combination with Figure 4 and Figure 5 , along the height direction of the chip packaging structure 10, the height of the dam region 300 is greater than or equal to the height of the buffer layer 500 and the bare chip 200.
[0094] In this embodiment, by limiting the height of the dam region 300 to be greater than or equal to the height of the buffer layer 500 and the bare chip 200, it is ensured that the entire side surface of the bare chip 200 can be covered, especially the corners of the bare chip 200, so as to better protect the bare chip 200 from external impact and damage. At the same time, the extension of the height of the dam region 300 improves the support effect of the protective layer 400, further increases the distance from the outer surface of the protective layer 400 to the bare chip 200, ensures that the formed protective layer 400 is more full, and improves the stress resistance of the chip packaging structure 10.
[0095] As shown in Figure 4 , along the height direction of the chip packaging structure 10, the height of the dam region 300 is h, and the height of the buffer layer 500 and the bare chip 200 is h. As shown in Figure 5 , along the height direction of the chip packaging structure 10, the height of the buffer layer 500 and the bare chip 200 is h, and the height of the dam region 300 is m, m>h.
[0096] In a specific application, as shown in Figure 4 and Figure 5As shown, the chip packaging structure 10 includes a substrate 100, a buffer layer 500, a bare chip 200, a dam region 300, and the dam region 300. The substrate 100 includes a mounting region 101. The buffer layer 500 is disposed on the mounting region 101. The bare chip 200 includes a first surface 201 and a second surface 202 disposed oppositely, and the bare chip 200 is disposed on the side of the buffer layer 500 away from the substrate 100 with the first surface 201 facing the substrate 100. The buffer layer 500 covers part of the side surface of the bare chip 200. The dam region 300 covers the side surface of the buffer layer 500, part of the side surface of the bare chip 200, and part of the mounting region 101 along the circumference of the bare chip 200. The protective layer 400 covers the second surface 202 of the bare chip 200 and the surface of the dam region 300. The hardness of the dam region 300 is greater than the hardness of the protective layer 400. In the height direction of the chip packaging structure 10, the height of the dam region 300 is greater than or equal to the height of the buffer layer 500 and the bare chip 200. In this embodiment, the chip packaging structure 10 has the technical effects as described in the above embodiments, which will not be described here.
[0097] In some embodiments, the chip packaging structure 10 is used in combination with Figure 7 As shown, a chip packaging product 1 is provided, which includes the chip packaging structure 10 as described in the above embodiments.
[0098] The chip packaging product 1 provided by the embodiments of the present disclosure includes the chip packaging structure 10 as described in the above embodiments, and thus has the technical effects of the chip packaging structure 10 as described in the above embodiments, which will not be described here.
[0099] It should be noted that the chip packaging product 1 in the embodiments of the present disclosure refers to a physical object including the chip packaging structure 10 as described in the above embodiments. The specific types of the chip packaging product 1 include but are not limited to financial cards, smart cards, processors, electronic devices, and the like, and the electronic devices include but are not limited to mobile phones, tablets, wearable wristbands, and the like.
[0100] In some embodiments, the chip packaging structure 10 is used in combination with Figure 1 As shown, a chip packaging method is provided for the chip packaging structure 10, which includes Figure 8 As shown, the chip packaging method includes:
[0101] S801, fixing and mounting a bare chip on a substrate, and making a cleavage surface of the bare chip form a preset angle with a preset stress direction.
[0102] S802, connecting a grounding pin on the substrate and a grounding pad on the bare chip, and connecting an input / output pin on the substrate and an input / output pad on the bare chip.
[0103] In this step, the pins and pads can be connected by welding or crimping using metal wires (such as gold wires).
[0104] The chip packaging method provided by the embodiments of the present disclosure can make the cleavage surface of the bare chip 200 form a preset angle with the preset stress direction in the process of fixing and installing the bare chip 200 on the substrate 100, and then connect the ground pin 102 and the ground pad 205 and the input and output pin 104 and the input and output pad 207 on the bare chip, so as to realize the chip packaging structure 10 as described in the above embodiments.
[0105] Due to the chip packaging method provided by the embodiments of the present disclosure, the chip packaging structure 10 as described in the above embodiments can be formed, and the technical effects of the chip packaging structure 10 as described in the above embodiments are also possessed by the embodiments of the present disclosure, which will not be described here.
[0106] In some embodiments, in combination with the chip packaging structure 10 as shown in Figure 4 and Figure 5 , a chip packaging method is provided, as shown in Figure 9 . The bare chip includes a first surface and a second surface arranged oppositely. The chip packaging method includes:
[0107] S901, applying glue on the mounting area of the substrate.
[0108] S902, installing the bare chip on the mounting area coated with glue in a manner that the first surface faces the substrate.
[0109] In this step, the second surface of the bare chip is the surface containing circuits, functional elements, and various pads, and the first surface is the surface arranged oppositely to the second surface.
[0110] S903, curing the substrate on which the bare chip is installed to form a buffer layer between the first surface of the bare chip and the substrate.
[0111] S904, applying glue along the circumference and the second surface of the bare chip, respectively.
[0112] S905, curing the bare chip and the substrate coated with glue to form a dam area along the circumference of the bare chip and a protective layer between the second surface of the bare chip and the surface of the dam area.
[0113] The chip packaging method provided by the embodiments of the present disclosure includes: fixing and mounting a bare chip 200 on a mounting area 101 of a substrate 100 in a manner that a first surface 201 of the bare chip 200 faces the substrate 100; then coating glue along a circumferential direction of the bare chip 200 and a second surface 202 of the bare chip 200 respectively; and curing the bare chip 200 and the substrate 100 coated with the glue, so that a dam area 300 is formed along the circumferential direction of the bare chip 200, and a protective layer 400 is formed on the second surface 202 of the bare chip 200 and a surface of the dam area 300. The dam area 300 formed along the circumferential direction of the bare chip 200 covers the side surface of the bare chip 200 and part of the mounting area 101, and the protective layer 400 covers the second surface 202 of the bare chip 200 and the surface of the dam area 300, so that the chip packaging structure 10 as described in the above embodiments is formed.
[0114] In some embodiments, a chip packaging method is provided, including: fixing and mounting a bare chip on a mounting area of a substrate in a manner that a first surface of the bare chip faces the substrate, and making a cleavage surface of the bare chip form a preset angle with a preset stress direction; connecting a ground pin on the substrate and a ground pad on the bare chip, and connecting an input / output pin on the substrate and an input / output pad on the bare chip; coating glue along a circumferential direction of the bare chip and a second surface of the bare chip respectively; and curing the bare chip and the substrate coated with the glue, so that a dam area is formed along the circumferential direction of the bare chip, and a protective layer is formed on the second surface of the bare chip and a surface of the dam area. The hardness of the dam area is greater than the hardness of the protective layer.
[0115] Optionally, the fixing and mounting of the bare chip on the mounting area of the substrate in the manner that the first surface of the bare chip faces the substrate includes: coating glue on the mounting area of the substrate; mounting the bare chip on the mounting area coated with the glue in the manner that the first surface of the bare chip faces the substrate, and making the glue overflow four corners and four edges of the bare chip; and curing the substrate on which the bare chip is mounted, so that a buffer layer is formed between the first surface of the bare chip and the substrate.
[0116] In this embodiment, the bare chip 200 is fixed and mounted on the mounting area 101 of the substrate 100 by coating glue on the mounting area 101 of the substrate 100 and mounting the bare chip 200 on the mounting area 101 coated with the glue in the manner that the first surface 201 of the bare chip 200 faces the substrate 100, and then curing the substrate 100 on which the bare chip 200 is mounted. The glue overflows four corners and four edges of the bare chip 200 to ensure that the connection between the bare chip 200 and the substrate 100 is more compact, and the reliability and stability of the packaging are improved. In this embodiment, the glue overflows four corners and four edges of the bare chip 200, so that the buffer layer 500 formed between the first surface 201 of the bare chip 200 and the substrate 100 after the glue is cured is more full, so as to play a buffering role in the process of stress pressing.
[0117] Optionally, adhesive may be applied to the mounting area of the substrate, including applying adhesive to the mounting area of the substrate using a cross-hatching or crisscrossing method.
[0118] Traditional dispensing methods involve precisely applying adhesive onto the substrate 100, such as... Figure 10 As shown. Only four-sided adhesive overflow of the bare chip 200 can be achieved, such as... Figure 11 As shown. In this embodiment, adhesive is applied to the mounting area 101 of the substrate 100 using a cross-hatching or crisscrossing method, such as... Figure 12 and Figure 13 As shown, the cross-hatching or crisscrossing adhesive application method ensures that after the bare chip 200 is installed in the mounting area 101, adhesive overflow is achieved at all four corners and all four sides of the bare chip 200. Figure 14 As shown, this ensures that the buffer layer 500 formed after the glue cures is fuller.
[0119] In this embodiment, the adhesive applied to the mounting area can be an underfill adhesive. Underfill adhesive is an adhesive used for filling the underside of the chip, and it can be cured by heat curing.
[0120] Optionally, applying adhesive along the circumference and second surface of the bare chip includes: applying damming adhesive along the circumference of the bare chip; and applying UV-curing adhesive along the second surface of the bare chip and the surface of the damming adhesive.
[0121] The damming adhesive is an adhesive with high viscosity, high hardness, and good barrier properties. In this embodiment, the damming adhesive is uniformly applied along the circumference of the bare chip 200 to form a continuous adhesive dam of a certain height, namely the damming area 300, along the circumference of the bare chip 200. The cured damming adhesive has high strength and hardness, which can effectively protect the corners and edges of the bare chip 200, while providing additional mechanical support for the protective layer 400 to enhance the stress resistance of the chip packaging structure 10.
[0122] UV-curable adhesive is an adhesive that cures rapidly upon exposure to ultraviolet light. In this embodiment, by uniformly applying UV-curable adhesive along the second surface 202 of the bare chip 200 and the surface of the damming adhesive, a dense protective layer 400 is formed on the second surface 202 of the bare chip 200 and the surface of the damming area 300, protecting the chip from mechanical and chemical damage. Furthermore, supported by the damming area 300, the formed protective layer 400 is more substantial, providing effective cushioning to enhance the stress resistance of the chip packaging structure 10.
[0123] In this embodiment, by coating the damming glue and the ultraviolet curing glue in sequence and then uniformly curing, the packaging step is avoided, and the production efficiency is ensured. Meanwhile, the damming area 300 and the protection layer 400 are integrally formed by coating the damming glue and the ultraviolet curing glue in sequence and then uniformly curing, so that there is no interface problem between the damming area 300 and the protection layer 400, and the structure is more stable and reliable.
[0124] Optionally, the curing of the die and the substrate coated with the glue includes ultraviolet curing of the die and the substrate coated with the glue.
[0125] In some embodiments, the die 200 includes a first surface 201 and a second surface 202 arranged oppositely. After the curing of the die and the substrate coated with the glue, the chip packaging method further includes scribing the protection layer to make the cross section of the protection layer parallel to the substrate into a polygon.
[0126] In combination Figure 15 As shown in FIG. 1, another chip packaging method is provided, which includes:
[0127] S151, fixing and mounting the die on the mounting area of the substrate with the first surface facing the substrate, and making the cleavage surface of the die form a preset angle with the preset stress direction.
[0128] S152, connecting the ground pin on the substrate and the ground pad on the die, and connecting the input and output pin on the substrate and the input and output pad on the die.
[0129] S153, coating the glue along the circumference of the die and the second surface, respectively.
[0130] S154, curing the die and the substrate coated with the glue, so that the circumference of the die forms a damming area, and the second surface of the die and the surface of the damming area form a protection layer.
[0131] In this embodiment, by coating the damming glue and the ultraviolet curing glue in sequence and then uniformly curing, the packaging step is avoided, and the production efficiency is ensured. Meanwhile, the damming area 300 and the protection layer 400 are integrally formed by coating the damming glue and the ultraviolet curing glue in sequence and then uniformly curing, so that there is no interface problem between the damming area 300 and the protection layer 400, and the structure is more stable and reliable.
[0132] S155, scribing the protection layer to make the cross section of the protection layer parallel to the substrate into a polygon.
[0133] In this step, a scribing knife or a laser scribing machine can be used to perform the scribing operation on the surface of the protection layer to make the cross section of the protection layer parallel to the substrate into a polygon. The polygon includes a pentagon, a hexagon, a heptagon, or an octagon.
[0134] The chip packaging method provided by the embodiments of the present disclosure can, after the protective layer 400 is solidified to form, perform a protective layer 400 scribing to make the cross section of the protective layer 400 parallel to the substrate 100 a polygon, so that the protective layer 400 can more evenly disperse stress when subjected to external force, further improving the stress resistance of the chip packaging structure 10.
[0135] In some embodiments, the bare chip 200 includes a first surface 201 and a second surface 202 arranged opposite to each other. Before the bare chip is fixedly installed on the mounting area of the substrate with the first surface facing the substrate, the chip packaging method further includes: cutting a wafer to obtain the bare chip.
[0136] Wafer cutting is an important link in the semiconductor manufacturing process, and the purpose is to divide the whole wafer that has been manufactured into single chips (also known as "die", that is, the bare chip in the embodiments of the present disclosure) according to the size of the chip. In this embodiment, a cutting machine can be used to cut the wafer. The cutting machine is usually equipped with a high-speed rotating diamond blade or a laser cutting device, so as to accurately cut the wafer along the predetermined cutting line, and separate the single chip, that is, the bare chip 200.
[0137] Optionally, when the wafer is a low dielectric constant wafer, the wafer is cut in the following manner: laser grooving is performed on the wafer to obtain a cutting channel; and the wafer is cut off along the cutting channel by using a blade to obtain the bare chip.
[0138] In this embodiment, the low dielectric constant (Low-k) wafer is a wafer made of a dielectric material with a relatively low dielectric constant. The dielectric constant (k value) is an index for measuring the electricity storage capacity of the dielectric material, and the Low-k material can effectively reduce the distributed capacitance between the interconnection lines due to its low k value, thereby improving the performance of the chip. For the low dielectric constant wafer, the combination process of laser grooving and blade cutting is adopted to ensure the stable division of the bare chip 200. In this embodiment, the laser grooving can use nanosecond laser.
[0139] In a specific application, in combination with Figure 4 and Figure 5The chip packaging structure 10 is shown. The chip packaging method comprises: laser grooving a wafer to obtain a cutting path; cutting the wafer along the cutting path by using a blade to obtain a bare chip 200; applying glue in a rice-shaped or cross-shaped manner on a mounting area 101 of a substrate 100; mounting the bare chip 200 on the mounting area 101 coated with the glue in a manner that a first surface 201 of the bare chip 200 faces the substrate 100, and the cleavage surface of the bare chip 200 is at a preset angle with a preset stress direction, and the glue overflows four corners and four edges of the bare chip 200; curing the substrate 100 on which the bare chip 200 is mounted to form a buffer layer 500 between the first surface 201 of the bare chip 200 and the substrate 100; wherein along the circumference of the bare chip 200, the buffer layer 500 covers part of the side surface of the bare chip 200; connecting the ground pin 102 and the ground solder point 205, and the input and output pin 104 and the input and output solder point 207 by welding or pressure bonding; coating dam glue along the circumference of the bare chip 200; coating ultraviolet curing glue along the second surface 202 of the bare chip 200 and the surface of the dam glue; wherein the dam glue and the ultraviolet curing glue cover the ground pin 102, the ground solder point 205, the input and output pin 104 and the input and output solder point 207; ultraviolet curing the bare chip 200 and the substrate 100 coated with the dam glue and the ultraviolet curing glue, so that the circumference of the bare chip 200 forms a dam area 300, the second surface 202 of the bare chip 200 and the surface of the dam area 300 form a protective layer 400, the formed dam area 300 covers the side surface of the bare chip 200 and part of the mounting area 101 along the circumference of the bare chip 200, and the protective layer 400 covers the second surface 202 of the bare chip 200 and the surface of the dam area 300; scribing the protective layer 400, so that the protective layer 400 is polygonal in cross section parallel to the substrate 100.
[0140] The above description and drawings suffice to fully illustrate the embodiments of the present disclosure to enable a person skilled in the art to practice them. Other embodiments can include structural and other changes. The embodiments only represent possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations can be changed. Parts and features of some embodiments can be included or replaced by parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A chip package structure, characterized by, The chip packaging structure comprises: a substrate comprising ground pins and input-output pins arranged at intervals; a bare chip arranged on the substrate, and a cleavage surface of the bare chip being deflected by a preset angle relative to a preset stress direction, ground pads and input-output pads being arranged at intervals on the bare chip, the ground pads being arranged in connection with the ground pins, and the input-output pads being arranged in connection with the input-output pins; wherein a distance from the ground pins to the ground pads is less than a distance from the input-output pins to the input-output pads.
2. The chip packaging structure according to claim 1, wherein: the substrate further comprises serial interface input-output pins arranged at intervals with the ground pins and the input-output pins; the bare chip further comprises serial interface input-output pads arranged at intervals with the ground pads and the input-output pads, the serial interface input-output pads being arranged in connection with the serial interface input-output pins; and / or the substrate further comprises clock signal input pins arranged at intervals with the ground pins and the input-output pins; the bare chip further comprises clock signal input pads arranged at intervals with the ground pads and the input-output pads, the clock signal input pads being arranged in connection with the clock signal input pins; and / or the substrate further comprises reset signal input pins arranged at intervals with the ground pins and the input-output pins; the bare chip further comprises reset signal input pads arranged at intervals with the ground pads and the input-output pads, the reset signal input pads being arranged in connection with the reset signal input pins; and / or the substrate further comprises power voltage input pins arranged at intervals with the ground pins and the input-output pins; the bare chip further comprises power voltage input pads arranged at intervals with the ground pads and the input-output pads, the power voltage input pads being arranged in connection with the power voltage input pins.
3. The chip packaging structure according to claim 2, wherein: the substrate comprises clock signal input pins and power voltage input pins arranged at intervals with the ground pins and the input-output pins; the bare chip comprises clock signal input pads and power voltage input pads arranged at intervals with the ground pads and the input-output pads; wherein a distance from the clock signal input pins to the clock signal input pads is less than a distance from the power voltage input pins to the power voltage input pads.
4. The chip package structure of any one of claims 1 to 3, wherein, The preset angle is 30° to 60°.
5. The chip package structure of any one of claims 1 to 3, wherein, The substrate comprises a mounting area, and the ground pins and the input-output pins are located in the mounting area; the bare chip comprises oppositely arranged first and second surfaces, and the bare chip is arranged in the mounting area with the first surface facing the substrate, and the ground pads and the input-output pads are located on the second surface; the chip packaging structure further comprises a dam area and a protective layer, the dam area covering the side surface of the bare chip and part of the mounting area along the circumference of the bare chip, and the protective layer covering the second surface of the bare chip and the surface of the dam area; wherein the hardness of the dam area is greater than the hardness of the protective layer.
6. The chip packaging structure according to claim 5, wherein: the dam area is formed by curing dam glue; and / or the protective layer is formed by curing ultraviolet curing glue.
7. The chip package structure of claim 5, wherein, The chip packaging structure further comprises: a buffer layer arranged in the mounting area; wherein the first surface of the bare chip is arranged on a side of the buffer layer away from the substrate.
8. The chip package structure of claim 7, wherein, The cross-sectional area of the buffer layer parallel to the substrate is greater than the cross-sectional area of the die parallel to the substrate.
9. The chip package structure of claim 7, wherein, Along the circumference of the die, the buffer layer covers part of the side surface of the die; the height of the dam region is greater than the height of the buffer layer, and the dam region covers the side surface of the buffer layer, part of the side surface of the die, and part of the mounting region along the circumference of the die.
10. A chip package product, characterized by comprising: The chip package structure as claimed in any one of claims 1 to 9. The chip package structure as claimed in any one of claims 1 to 9.