Heterojunction solar cell and photovoltaic module

Abstract

The utility model provides a heterojunction solar cell and a photovoltaic assembly. The heterojunction solar cell comprises: a silicon substrate; along the thickness direction of the silicon substrate, the surface of the main light receiving surface of the silicon substrate comprises a front intrinsic layer, a front doping layer, a first transparent oxide conductive layer and a first electrode which are stacked in sequence. A first back intrinsic layer, a second back intrinsic layer, a back doping layer, a second transparent oxide conductive layer and a second electrode which are stacked in sequence are arranged on the surface of the other side opposite to the main light receiving surface of the silicon substrate; in the horizontal direction perpendicular to the thickness direction of the silicon substrate, the surface of the side wall of the silicon substrate comprises a front doping layer, a second back intrinsic layer and a back doping layer which are stacked from inside to outside. The structure of the utility model improves the insulation effect of the heterojunction solar cell, so that the heterojunction solar cell has better tunneling contact and higher thermal attenuation reliability, thereby realizing the improvement of the photoelectric conversion effect of the cell.

Description

Technical Field

[0001] This utility model belongs to the field of photovoltaic technology and relates to a heterojunction solar cell and a photovoltaic module. Background Technology

[0002] With the widespread application of solar cell modules, photovoltaic power generation is playing an increasingly important role in new energy sources and has experienced rapid development. Currently, among commercially available solar cell products, crystalline silicon (monocrystalline and polycrystalline) solar cells hold the largest market share, consistently maintaining over 85%. Therefore, developing high-performance, cost-effective crystalline silicon solar cells remains a key research focus for researchers worldwide.

[0003] Currently, Sanyo Corporation of Japan is producing a type of crystalline silicon heterojunction solar cell. A heterojunction refers to a cell where the PN junction on the front side is composed of amorphous silicon and an N-type monocrystalline silicon substrate. The amorphous silicon layer includes a P-type amorphous silicon thin film layer and an intrinsic amorphous silicon thin film layer. On the back side, the intrinsic amorphous silicon thin film layer and the N-type amorphous silicon thin film layer form the back electric field. Amorphous silicon, as a direct bandgap semiconductor material, has a large absorption coefficient for incident light; even a very thin amorphous silicon thin film layer can absorb a significant portion of the incident light. Simultaneously, the bandgap of amorphous silicon is 1.7 eV, much larger than the 1.1 eV bandgap of crystalline silicon. Therefore, the open-circuit voltage of a heterojunction solar cell can be significantly higher than that of a conventional crystalline silicon solar cell, resulting in superior performance.

[0004] The advantage of heterojunction high-efficiency solar cells compared to other types of cells lies in the efficient passivation and tunneling capabilities of the intrinsic amorphous layer. Typically, the inner layer effectively passivates by suppressing epitaxial growth, while the outer layer forms effective contact with the corresponding doped layer. Current research indicates that tunneling contacts on the back side of the cell significantly affect its IV performance and are directly related to thermal degradation reliability. Therefore, achieving better tunneling contacts is crucial. Furthermore, due to the relatively thin silicon substrate and limitations in coating process precision used in heterojunction solar cells, edge short circuits or leakage are prone to occur.

[0005] Therefore, how to make heterojunction solar cells have better tunneling contacts and reduce the possibility of edge short circuits or the existence of leakage current is an urgent research topic. Utility Model Content

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a heterojunction solar cell and photovoltaic module. This invention improves the insulation performance of the heterojunction solar cell by combining multiple intrinsic back layers on the silicon substrate surface and through the synergistic effect of the film structure at the sidewalls. It also enables the heterojunction solar cell to have better tunneling contact and higher thermal decay reliability, thereby achieving a significant improvement in the cell's photoelectric conversion efficiency.

[0007] To achieve this objective, the present invention adopts the following technical solution:

[0008] In a first aspect, this utility model provides a heterojunction solar cell, the heterojunction solar cell comprising:

[0009] Silicon substrate.

[0010] Along the thickness direction of the silicon substrate, the surface of the main light-receiving surface of the silicon substrate includes a front intrinsic layer, a front doped layer, a first transparent oxide conductive layer, and a first electrode, which are stacked sequentially.

[0011] Along the thickness direction of the silicon substrate, the main light-receiving surface of the silicon substrate includes, on the opposite side, a first back intrinsic layer, a second back intrinsic layer, a back doped layer, a second transparent oxide conductive layer, and a second electrode, which are stacked sequentially.

[0012] Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the sidewall surface of the silicon substrate includes, from the inside out, a front doped layer, a second back intrinsic layer, and a back doped layer stacked together.

[0013] In the heterojunction solar cell provided by this invention, a second intrinsic back layer is provided between the back doped layer (p layer) and the first intrinsic back layer, ensuring that the outermost part in contact with the p doped layer is undamaged, resulting in a low-resistance and stable tunneling contact. Furthermore, a film structure is also provided on the sidewall of the silicon substrate, ensuring that at least one intrinsic back layer structure is included between the front doped layer (n layer) and the back doped layer (p layer), thus improving the cell's insulation performance. Through the synergistic cooperation of the film layer stacking order and the specific types of structural layers in the cell structure, the insulation performance of the heterojunction solar cell is enhanced, and the heterojunction solar cell exhibits better tunneling contact and higher thermal decay reliability, thereby achieving a significant improvement in the cell's photoelectric conversion efficiency.

[0014] The following are preferred technical solutions of this utility model, but are not intended to limit the technical solutions provided by this utility model. Through the following preferred technical solutions, the technical objectives and beneficial effects of this utility model can be better achieved.

[0015] As a preferred technical solution of this utility model, the silicon substrate includes an N-type silicon substrate, the resistivity of which is 0.5 to 3 Ω·cm, such as 0.5 Ω·cm, 1 Ω·cm, 1.5 Ω·cm, 2 Ω·cm, 2.5 Ω·cm or 3 Ω·cm, etc., and the thickness of which is 90 to 120 μm, such as 90 μm, 95 μm, 100 μm, 105 μm, 110 μm, 115 μm or 120 μm, etc.

[0016] The heterojunction solar cell provided by this invention uses an N-type silicon substrate, which has higher quality and a longer minority carrier lifetime, resulting in a back-junction heterojunction solar cell with higher conversion efficiency.

[0017] As a preferred technical solution of this utility model, the thickness of the front doped layer disposed on the sidewall surface of the silicon substrate along the horizontal direction perpendicular to the thickness direction of the silicon substrate is 0.5 to 2 nm, for example, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc.

[0018] As a preferred technical solution of this utility model, the thickness of the second back intrinsic layer disposed on the sidewall surface of the silicon substrate along the horizontal direction perpendicular to the thickness direction of the silicon substrate is 0.5 to 2 nm, for example, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc.

[0019] As a preferred technical solution of this utility model, the thickness of the back-side doped layer disposed on the sidewall surface of the silicon substrate along the horizontal direction perpendicular to the thickness direction of the silicon substrate is 0.5 to 2 nm, for example, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc.

[0020] In this invention, a film structure is provided on the sidewall of the silicon substrate along a horizontal direction perpendicular to the thickness direction of the silicon substrate. The thickness of the front doped layer is 0.5-2 nm, and / or the thickness of the second back intrinsic layer is 0.5-2 nm, and / or the thickness of the back doped layer is 0.5-2 nm. By further limiting the thickness of the above-mentioned film structure, a good insulation effect can be achieved, and the sidewall film thickness can be avoided from being too thick, which would affect the good performance of the heterojunction solar cell.

[0021] As a preferred technical solution of this utility model, the sidewall surface of the silicon substrate, from the inside to the outside, includes a first back intrinsic layer, a front intrinsic layer, a front doped layer, a second back intrinsic layer, and a back doped layer stacked together along the horizontal direction perpendicular to the thickness direction of the silicon substrate.

[0022] In this invention, in addition to the front doped layer, the second back intrinsic layer, and the back doped layer, the sidewall treatment of the silicon substrate can also include a first back intrinsic layer and a front intrinsic layer, which can better improve the insulation effect.

[0023] As a preferred technical solution of this utility model, the thickness of the first back intrinsic layer disposed on the sidewall surface of the silicon substrate along the horizontal direction perpendicular to the thickness direction of the silicon substrate is 0.5 to 2 nm, for example, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc.

[0024] As a preferred technical solution of this utility model, the thickness of the front intrinsic layer disposed on the sidewall surface of the silicon substrate along the horizontal direction perpendicular to the thickness direction of the silicon substrate is 0.5 to 2 nm, for example, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc.

[0025] As a preferred technical solution of this utility model, a first transparent oxide conductive layer is further provided on the surface of the back doped layer away from the silicon substrate along the horizontal direction perpendicular to the thickness direction of the silicon substrate.

[0026] As a preferred technical solution of this utility model, the thickness of the first transparent oxide conductive layer disposed on the sidewall surface of the silicon substrate along the horizontal direction perpendicular to the thickness direction of the silicon substrate is 0.5 to 2 nm, for example, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc.

[0027] As a preferred technical solution of this utility model, the thickness of the front intrinsic layer along the thickness direction of the silicon substrate is 4.5 to 7.5 nm, for example, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm or 7.5 nm.

[0028] As a preferred technical solution of this utility model, the thickness of the front doped layer along the thickness direction of the silicon substrate is 25-35nm, such as 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, 31nm, 32nm, 33nm, 34nm or 35nm, etc.

[0029] In this invention, both the intrinsic front layer and the doped front layer are conventional technical solutions. This invention applies to any specific film layer type that is reasonably known to those skilled in the art.

[0030] For example, the front intrinsic layer can be an intrinsic amorphous silicon film; the front doped layer can be at least one of an n-type doped microcrystalline silicon film, an n-type doped amorphous silicon film, or an n-type microcrystalline amorphous mixed doped film, wherein n-type is a positive junction.

[0031] Furthermore, those skilled in the art can make adaptive selections and adjustments for the specific deposition conditions in the intrinsic amorphous silicon film, the n-type doped microcrystalline silicon film, and / or the n-type doped amorphous silicon film, based on actual needs.

[0032] As a preferred technical solution of this utility model, the thickness of the first back intrinsic layer along the thickness direction of the silicon substrate is 1 to 2 nm, such as 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm.

[0033] This invention does not specifically limit the types of the first and second back intrinsic layers. Any type of intrinsic layer that can be reasonably known by those skilled in the art is applicable to this invention.

[0034] For example, the first back intrinsic layer may be selected from an intrinsic amorphous silicon film layer; the second back intrinsic layer may be selected from at least one of an intrinsic hydrogenated amorphous silicon film layer, an intrinsic amorphous silicon film layer, an intrinsic hydrogenated microcrystalline silicon film layer, or an intrinsic microcrystalline silicon film layer; preferably, the second back intrinsic layer is hydrogenated.

[0035] In this invention, the first back intrinsic layer, which is close to the surface of the silicon substrate, has a low R value and a better passivation effect; while the second back intrinsic layer, which is far from the surface of the silicon substrate, is diluted by high hydrogen and doped with high oxygen, which is conducive to microcrystal nucleation and more conducive to obtaining a back P layer with a higher crystallinity, thereby enabling the heterojunction solar cell to have a higher bandgap energy (Eg).

[0036] As a preferred technical solution of this utility model, the thickness of the second back intrinsic layer along the thickness direction of the silicon substrate is 3 to 6 nm, such as 3 nm, 3.3 nm, 3.5 nm, 3.8 nm, 4 nm, 4.3 nm, 4.5 nm, 4.8 nm, 5 nm, 5.3 nm, 5.5 nm, 5.8 nm or 6 nm.

[0037] In this invention, by adjusting the thickness of the first back intrinsic layer to 1-2 nm and / or the thickness of the second back intrinsic layer to 3-6 nm, the outermost intrinsic layer in contact with the front doped layer can be kept undamaged, which is beneficial for obtaining a low-resistance and stable tunneling contact.

[0038] As a preferred technical solution of this utility model, the thickness of the back doped layer along the thickness direction of the silicon substrate is 25-35nm, such as 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, 31nm, 32nm, 33nm, 34nm or 35nm, etc.

[0039] In this invention, both the intrinsic back layer and the doped back layer are conventional technical solutions. This invention applies to any specific film layer type that is reasonably known to those skilled in the art.

[0040] For example, the intrinsic back layer can be an intrinsic amorphous silicon film; the doped back layer can be at least one of a p-type doped microcrystalline silicon film, a p-type doped amorphous silicon film, or a mixed doped microcrystalline-amorphous film, wherein p-type is the back junction.

[0041] It should be noted that the p-type doped microcrystalline silicon film and / or p-type doped amorphous silicon film in this invention are conventional film structures that can be obtained according to existing technologies. Those skilled in the art can adjust the flow rates of silane, hydrogen and doping gas and the type of doping gas according to actual needs to obtain the desired p-type amorphous silicon film.

[0042] As a preferred technical solution of this utility model, along the thickness direction of the silicon substrate, the thickness of the first transparent oxide conductive layer and the second transparent oxide conductive layer are each independently 40-120nm, such as 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm or 120nm.

[0043] Secondly, this utility model provides a photovoltaic module, which includes an upper glass layer, an upper encapsulating film, a battery string, a lower encapsulating film, and a lower glass layer stacked together, wherein the batteries in the battery string include heterojunction solar cells as described in the first aspect.

[0044] The numerical range described in this utility model includes not only the point values ​​listed above, but also any point values ​​within the numerical range not listed above. Due to space limitations and for the sake of brevity, this utility model will not exhaustively list the specific point values ​​included in the range.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] In the heterojunction solar cell provided by this invention, a second intrinsic back layer is provided between the back doped layer (p layer) and the first intrinsic back layer, ensuring that the outermost part in contact with the p doped layer is undamaged, resulting in a low-resistance and stable tunneling contact. Furthermore, a film structure is also provided on the sidewall of the silicon substrate, ensuring that at least one intrinsic back layer structure is included between the front doped layer (n layer) and the back doped layer (p layer), thus improving the cell's insulation performance. Through the synergistic cooperation of the film layer stacking order and the specific types of structural layers in the cell structure, the insulation performance of the heterojunction solar cell is enhanced, and the heterojunction solar cell exhibits better tunneling contact and higher thermal decay reliability, thereby achieving a significant improvement in the cell's photoelectric conversion efficiency. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the structure of a heterojunction solar cell in a specific embodiment of the present invention.

[0048] Figure 2 This is a schematic diagram of the heterojunction solar cell in the comparative example of this utility model.

[0049] Wherein, 1-silicon substrate, 2-first back intrinsic layer, 3-front intrinsic layer, 4-front doped layer, 5-second back intrinsic layer, 6-back doped layer, 7-first transparent oxide conductive layer, 8-second transparent oxide conductive layer, 9-first electrode, 10-second electrode, L-thickness direction. Detailed Implementation

[0050] It should be understood that in the description of this utility model, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0051] It should be noted that, in the description of this utility model, unless otherwise explicitly specified and limited, the terms "set," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0052] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments.

[0053] In one specific embodiment, the present invention provides a heterojunction solar cell, such as... Figure 1 As shown, the heterojunction solar cell includes:

[0054] Silicon substrate 1.

[0055] Along the thickness direction L of the silicon substrate 1, the surface of the main light-receiving surface of the silicon substrate 1 includes a front intrinsic layer 3, a front doped layer 4, a first transparent oxide conductive layer 7, and a first electrode 9, which are stacked sequentially.

[0056] Along the thickness direction L of the silicon substrate 1, the main light-receiving surface of the silicon substrate 1 on the opposite side includes a first back intrinsic layer 2, a second back intrinsic layer 5, a back doped layer 6, a second transparent oxide conductive layer 8, and a second electrode 10, which are stacked sequentially.

[0057] Along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, the sidewall surface of the silicon substrate 1 includes, from the inside to the outside, a front doped layer 4, a second back intrinsic layer 5, and a back doped layer 6 stacked together.

[0058] In a preferred embodiment, the silicon substrate 1 includes an N-type silicon substrate with a resistivity of 0.5–3 Ω·cm and a thickness of 90–120 μm.

[0059] As a preferred embodiment, the thickness of the front doped layer 4 disposed on the sidewall surface of the silicon substrate 1 along the direction perpendicular to the thickness direction L is 0.5 to 2 nm.

[0060] As a preferred embodiment, the thickness of the second back intrinsic layer 5 disposed on the sidewall surface of the silicon substrate 1 is 0.5 to 2 nm along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1.

[0061] As a preferred embodiment, the thickness of the back-side doped layer 6 disposed on the sidewall surface of the silicon substrate 1 is 0.5 to 2 nm along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1.

[0062] As a preferred technical solution in a specific embodiment, the sidewall surface of the silicon substrate 1, from the inside to the outside, includes a first back intrinsic layer 2, a front intrinsic layer 3, a front doped layer 4, a second back intrinsic layer 5, and a back doped layer 6 stacked together along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1.

[0063] As a preferred embodiment, the thickness of the first back intrinsic layer 2 disposed on the sidewall surface of the silicon substrate 1 is 0.5 to 2 nm along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1.

[0064] As a preferred embodiment, the thickness of the front intrinsic layer 3 disposed on the sidewall surface of the silicon substrate 1 along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1 is 0.5 to 2 nm.

[0065] As a preferred embodiment, along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, a first transparent oxide conductive layer 7 is also provided on the surface of the back doped layer 6 away from the silicon substrate 1.

[0066] Furthermore, along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, the thickness of the first transparent oxide conductive layer 7 disposed on the sidewall surface of the silicon substrate 1 is 0.5 to 2 nm.

[0067] As a preferred technical solution in a specific embodiment, the front intrinsic layer is an intrinsic amorphous silicon film layer.

[0068] As a preferred embodiment, the thickness of the front intrinsic layer 3 along the thickness direction L of the silicon substrate 1 is 4.5 to 7.5 nm.

[0069] As a preferred embodiment, the thickness of the front doped layer 4 along the thickness direction L of the silicon substrate 1 is 25-35 nm.

[0070] As a preferred embodiment, the thickness of the first back intrinsic layer 2 along the thickness direction L of the silicon substrate 1 is 1-2 nm.

[0071] In a preferred embodiment, the thickness of the second back intrinsic layer 5 is 3-6 nm along the thickness direction L of the silicon substrate 1.

[0072] In a preferred embodiment, the thickness of the back doped layer 6 is 25-35 nm along the thickness direction L of the silicon substrate 1.

[0073] As a preferred embodiment, along the thickness direction L of the silicon substrate 1, the thickness of the first transparent oxide conductive layer 7 and the second transparent oxide conductive layer 8 are each independently 40-120 nm.

[0074] In one application embodiment, the photovoltaic module includes an upper glass layer, an upper encapsulating film, a battery string, a lower encapsulating film, and a lower glass layer stacked together, wherein the batteries in the battery string include heterojunction solar cells as described in the above specific embodiments.

[0075] It should be noted that the heterojunction solar cell of this invention is feasible to manufacture, and the raw materials, preparation conditions and specific preparation sequence of each film layer can be adapted and adjusted by those skilled in the art according to the thickness and type requirements of the film layers.

[0076] By way of example, the present invention provides a method for fabricating a heterojunction solar cell, the method being as follows:

[0077] (1) Selection of silicon substrate: N-type crystal silicon wafers with resistivity of 0.5~3Ω.cm, thickness of 100μm, and size of 210mm are selected;

[0078] (2) Cleaning and texturing: The surface oxide layer of the silicon substrate is removed by using a diluted HF solution with a concentration of 5%. The anisotropic etching of single crystal silicon is used to form a pyramid structure on the surface by using KOH and alcohol, thus completing the texturing process on both sides of the silicon substrate.

[0079] (3) Deposition of the first back intrinsic layer: SiH4 (silane) gas is introduced into the vacuum chamber and the first back intrinsic layer is formed on the entire area of ​​the first surface of the silicon substrate (the surface on any side and the sidewall along the thickness direction of the silicon substrate) by plasma CVD; wherein, the silane flow rate is 800-1000 sccm, the pressure is 0.4-0.6 Torr, and the deposition power is 500-1000 W; the thickness of the first back intrinsic layer on one side surface of the silicon substrate (the non-light-receiving side opposite the light-receiving side) is 1-2 nm, and the thickness of the first back intrinsic layer along the thickness direction of the silicon substrate is 0.5-1 nm.

[0080] (4) Deposition of front intrinsic layer and front doped layer: The silicon substrate is flipped over to expose the opposite side of the silicon substrate. The tray of the silicon substrate is replaced. SiH4 (silane) gas is introduced into the vacuum chamber and the front intrinsic layer is formed on the entire area of ​​the second surface of the silicon substrate (the opposite side of the silicon substrate and the sidewall along the thickness direction of the silicon substrate) by plasma CVD. The silane flow rate is 500-1000 sccm, the pressure is 0.4-0.6 Torr, and the deposition power is 200-600 W. The thickness of the front intrinsic layer on the other side surface (light-receiving surface) of the silicon substrate is 4.5-7.5 nm, and the thickness of the front intrinsic layer on the sidewall along the thickness direction of the silicon substrate is 0.5-1 nm.

[0081] Then, SiH4 gas, H2 gas, and PH3 (phosphine, the first doping gas) gas were introduced into the vacuum chamber, and a front-side doped layer was formed on the surface of the intrinsic front layer by plasma CVD. The flow rate of silane was 40-70 sccm, the flow rate of hydrogen was 12000-16000 sccm, the flow rate of PH3 was 200-500 sccm, the pressure was 4-6 Torr, and the deposition power was 2000-5000 W. The thickness of the front-side doped layer on the light-receiving surface was 25-35 nm, and the thickness of the front-side doped layer along the thickness direction of the silicon substrate was 0.5-2 nm.

[0082] (5) Deposition of the second back intrinsic layer and the back doped layer: The silicon substrate is flipped over again, the tray is replaced, and then SiH4 (silane) and hydrogen gas are introduced into the vacuum chamber. The second back intrinsic layer is formed on the entire area of ​​the first back intrinsic layer by plasma CVD. The ratio of hydrogen to silane flow rate is (1-5):1, the flow rate of silane is 500-1000 sccm, the flow rate of hydrogen is 500-5000 sccm, the pressure is 0.4-0.6 Torr, and the deposition power is 100-300 W. The thickness of the second back intrinsic layer 2 on the non-light-receiving surface is 3-6 nm, and the thickness of the second back intrinsic layer on the sidewall along the thickness direction of the silicon substrate is 0.5-2 nm.

[0083] Then, SiH4 gas, H2 gas, and B2H6 (diborane, the second doping gas) gas were introduced into the vacuum chamber, and a back-side doped layer was formed on the second intrinsic layer by plasma CVD. The flow rate of silane was 50-80 sccm, the flow rate of hydrogen was 18000-25000 sccm, the flow rate of B2H6 was 30-200 sccm, the pressure was 3-6 Torr, and the deposition power was 5000-8000 W. The thickness of the deposited back-side doped layer was 25-35 nm, and the thickness of the back-side doped layer along the sidewalls of the silicon substrate thickness direction was 0.5-2 nm.

[0084] (6) Deposition of transparent conductive oxide thin film (TCO): A reactive plasma deposition (RPD) method is used to deposit a film on the amorphous silicon thin film layers on the front and back sides; the back side is edge-masked by a carrier disk (masked by a mask), with a specific masking area of ​​0.8 mm around the perimeter. The TCO used is ITO (99.5:0.5), the film thickness is 40-120 nm, and the carrier concentration is 3×E. 20 / cm 3 Mobility ~80cm 2 / Vs;

[0085] (7) Electrode preparation: A layer of low-temperature conductive paste (e.g., silver paste) is printed on the front and back transparent conductive oxide films by screen printing, and then sintered and cured at a low temperature of 200°C to form good ohmic contact.

[0086] (8) Photoinjection treatment: After the battery obtained in step (7) is alkaline washed, the battery cell is subjected to photoinjection treatment. The temperature of the photoinjection treatment is 210℃ and the time of the photoinjection treatment is 90s.

[0087] The heterojunction solar cells provided in the following examples and comparative examples can be obtained by adaptive selection and adjustment using the above-described preparation method.

[0088] Example 1

[0089] This embodiment provides a heterojunction solar cell, based on the specific implementation described above. The heterojunction solar cell is:

[0090] Silicon substrate 1.

[0091] Along the thickness direction L of the silicon substrate 1, the surface of the main light-receiving surface of the silicon substrate 1 includes a front intrinsic layer 3, a front doped layer 4, a first transparent oxide conductive layer 7, and a first electrode 9, which are stacked sequentially.

[0092] Along the thickness direction L of the silicon substrate 1, the main light-receiving surface of the silicon substrate 1 on the opposite side includes a first back intrinsic layer 2, a second back intrinsic layer 5, a back doped layer 6, a second transparent oxide conductive layer 8, and a second electrode 10, which are stacked sequentially.

[0093] Along a horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, a first back intrinsic layer 2, a front intrinsic layer 3, a front doped layer 4, a second back intrinsic layer 5, a back doped layer 6, and a first transparent oxide conductive layer 7 are stacked on the sidewall surface of the silicon substrate 1.

[0094] Furthermore, along the thickness direction L of the silicon substrate 1, the thickness of the silicon substrate 1 is 100 μm, the thickness of the front intrinsic layer 3 is 5 nm, the thickness of the front doped layer 4 is 25 nm; the thickness of the first back intrinsic layer 2 is 2 nm, the thickness of the second back intrinsic layer 5 is 5 nm, the thickness of the back doped layer 6 is 25 nm, and the thickness of the first transparent conductive layer 7 and the second transparent conductive layer 8 is 40 nm.

[0095] Along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, the thickness of the film layer structure stacked on the sidewall surface of the silicon substrate 1 is 0.5 nm.

[0096] Example 2

[0097] This embodiment provides a heterojunction solar cell, based on the specific implementation described above. The heterojunction solar cell is:

[0098] Silicon substrate 1.

[0099] Along the thickness direction L of the silicon substrate 1, the surface of the main light-receiving surface of the silicon substrate 1 includes a front intrinsic layer 3, a front doped layer 4, a first transparent oxide conductive layer 7, and a first electrode 9, which are stacked sequentially.

[0100] Along the thickness direction L of the silicon substrate 1, the main light-receiving surface of the silicon substrate 1 on the opposite side includes a first back intrinsic layer 2, a second back intrinsic layer 5, a back doped layer 6, a second transparent oxide conductive layer 8, and a second electrode 10, which are stacked sequentially.

[0101] Along a horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, a first back intrinsic layer 2, a front intrinsic layer 3, a front doped layer 4, a second back intrinsic layer 5, a back doped layer 6, and a first transparent oxide conductive layer 7 are stacked on the sidewall surface of the silicon substrate 1.

[0102] Furthermore, along the thickness direction L of the silicon substrate 1, the thickness of the silicon substrate 1 is 100 μm, the thickness of the front intrinsic layer 3 is 7.5 nm, the thickness of the front doped layer 4 is 32 nm; the thickness of the first back intrinsic layer 2 is 2 nm, the thickness of the second back intrinsic layer 5 is 5 nm, the thickness of the back doped layer 6 is 32 nm, and the thickness of the first transparent conductive layer 7 and the second transparent conductive layer 8 is 40 nm.

[0103] Along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, the thickness of the film layer structure stacked on the sidewall surface of the silicon substrate 1 is 2 nm.

[0104] Example 3

[0105] This embodiment provides a heterojunction solar cell, based on the specific implementation described above. The heterojunction solar cell is:

[0106] Silicon substrate 1.

[0107] Along the thickness direction L of the silicon substrate 1, the surface of the main light-receiving surface of the silicon substrate 1 includes a front intrinsic layer 3, a front doped layer 4, a first transparent oxide conductive layer 7, and a first electrode 9, which are stacked sequentially.

[0108] Along the thickness direction L of the silicon substrate 1, the main light-receiving surface of the silicon substrate 1 on the opposite side includes a first back intrinsic layer 2, a second back intrinsic layer 5, a back doped layer 6, a second transparent oxide conductive layer 8, and a second electrode 10, which are stacked sequentially.

[0109] Along a horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, a first back intrinsic layer 2, a front intrinsic layer 3, a front doped layer 4, a second back intrinsic layer 5, a back doped layer 6, and a first transparent oxide conductive layer 7 are stacked on the sidewall surface of the silicon substrate 1.

[0110] Furthermore, along the thickness direction L of the silicon substrate 1, the thickness of the silicon substrate 1 is 100 μm, the thickness of the front intrinsic layer 3 is 6.5 nm, the thickness of the front doped layer 4 is 29 nm; the thickness of the first back intrinsic layer 2 is 2 nm, the thickness of the second back intrinsic layer 5 is 5 nm, the thickness of the back doped layer 6 is 29 nm, and the thickness of the first transparent conductive layer 7 and the second transparent conductive layer 8 is 40 nm.

[0111] Along the horizontal direction perpendicular to the thickness direction L of the silicon substrate 1, the thickness of the film layer structure stacked on the sidewall surface of the silicon substrate 1 is 0.8 nm.

[0112] Example 4

[0113] The difference between this embodiment and Embodiment 1 is that, along the thickness direction L of the silicon substrate 1, the thickness of the first back intrinsic layer 2 in this embodiment is 3 nm.

[0114] The structure and parameters of the remaining heterojunction solar cells are consistent with those of Example 1.

[0115] Example 5

[0116] The difference between this embodiment and Embodiment 1 is that, along the thickness direction L of the silicon substrate 1, the thickness of the first back intrinsic layer 2 in this embodiment is 0.5 nm.

[0117] The structure and parameters of the remaining heterojunction solar cells are consistent with those of Example 1.

[0118] Example 6

[0119] The difference between this embodiment and Embodiment 1 is that, along the thickness direction L of the silicon substrate 1, the thickness of the second back intrinsic layer 5 in this embodiment is 7 nm.

[0120] The structure and parameters of the remaining heterojunction solar cells are consistent with those of Example 1.

[0121] Example 7

[0122] The difference between this embodiment and Embodiment 1 is that, along the thickness direction L of the silicon substrate 1, the thickness of the second back intrinsic layer 5 in this embodiment is 2nm.

[0123] The structure and parameters of the remaining heterojunction solar cells are consistent with those of Example 1.

[0124] Example 8

[0125] The difference between this embodiment and Embodiment 1 is that, in this embodiment, the thickness of the film layer structure stacked on the sidewall surface of the silicon substrate 1 along the direction perpendicular to the thickness direction L of the silicon substrate 1 is 2.5 nm.

[0126] The structure and parameters of the remaining heterojunction solar cells are consistent with those of Example 1.

[0127] Comparative Example 1

[0128] The difference between this comparative example and Example 1 is that, as Figure 2 As shown, in this comparative example, along the direction perpendicular to the thickness direction L of the silicon substrate 1, there are no film layer structures stacked on the sidewall surface of the silicon substrate 1.

[0129] The structure and parameters of the remaining heterojunction solar cells are consistent with those of Example 1.

[0130] The solar cells prepared in Examples 1-8 and Comparative Example 1 were subjected to AFM1.5 performance tests, including open-circuit voltage (Voc), fill factor (FF), short-circuit current density (Jsc), conversion efficiency (eta), and thermal degradation (ΔEff); the specific test results are shown in Table 1.

[0131] Table 1

[0132]

[0133]

[0134] The above description is only a specific embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model fall within the protection and disclosure scope of the present utility model.

Claims

1. A heterojunction solar cell, characterized in that, The heterojunction solar cell includes: silicon substrate; Along the thickness direction of the silicon substrate, the surface of the main light-receiving surface of the silicon substrate includes a front intrinsic layer, a front doped layer, a first transparent oxide conductive layer and a first electrode stacked sequentially. Along the thickness direction of the silicon substrate, the main light-receiving surface of the silicon substrate includes, on the opposite side, a first back intrinsic layer, a second back intrinsic layer, a back doped layer, a second transparent oxide conductive layer, and a second electrode, which are stacked sequentially. Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the sidewall surface of the silicon substrate includes, from the inside out, a front doped layer, a second back intrinsic layer, and a back doped layer stacked together.

2. The heterojunction solar cell according to claim 1, characterized in that, The silicon substrate includes an N-type silicon substrate with a thickness of 90–120 μm.

3. The heterojunction solar cell according to claim 1, characterized in that, Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the thickness of the front doped layer disposed on the sidewall surface of the silicon substrate is 0.5 to 2 nm.

4. The heterojunction solar cell according to claim 1, characterized in that, Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the thickness of the second back intrinsic layer disposed on the sidewall surface of the silicon substrate is 0.5 to 2 nm.

5. The heterojunction solar cell according to claim 1, characterized in that, Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the thickness of the back-side doped layer disposed on the sidewall surface of the silicon substrate is 0.5 to 2 nm.

6. The heterojunction solar cell according to claim 1, characterized in that, Along the horizontal direction perpendicular to the thickness direction of the silicon substrate, the sidewall surface of the silicon substrate includes, from the inside to the outside, a first back intrinsic layer, a front intrinsic layer, a front doped layer, a second back intrinsic layer, and a back doped layer stacked together. Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the thickness of the first back intrinsic layer disposed on the sidewall surface of the silicon substrate is 0.5 to 2 nm. Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the thickness of the front intrinsic layer disposed on the sidewall surface of the silicon substrate is 0.5–2 nm. Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, a first transparent oxide conductive layer is also disposed on the surface of the back doped layer away from the silicon substrate; Along a horizontal direction perpendicular to the thickness direction of the silicon substrate, the thickness of the first transparent oxide conductive layer disposed on the sidewall surface of the silicon substrate is 0.5 to 2 nm.

7. The heterojunction solar cell according to claim 1, characterized in that, Along the thickness direction of the silicon substrate, the thickness of the front intrinsic layer is 4.5–7.5 nm; Along the thickness direction of the silicon substrate, the thickness of the front doped layer is 25–35 nm.

8. The heterojunction solar cell according to claim 1, characterized in that, Along the thickness direction of the silicon substrate, the thickness of the first back intrinsic layer is 1–2 nm; Along the thickness direction of the silicon substrate, the thickness of the second back intrinsic layer is 3–6 nm; Along the thickness direction of the silicon substrate, the thickness of the back doped layer is 25–35 nm.

9. The heterojunction solar cell according to claim 1, characterized in that, Along the thickness direction of the silicon substrate, the thicknesses of the first transparent oxide conductive layer and the second transparent oxide conductive layer are each independently 40–120 nm.

10. A photovoltaic module, characterized in that, The photovoltaic module includes an upper glass layer, an upper encapsulating film, a battery string, a lower encapsulating film, and a lower glass layer stacked together, wherein the battery in the battery string includes a heterojunction solar cell as described in any one of claims 1-9.

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