Segmented compensation low temperature coefficient band-gap reference circuit

Abstract

The utility model relates to a sectional type compensation low temperature coefficient band-gap reference circuit which comprises a current bias circuit, a compensation current circuit, a starting circuit, a folding type cascode operational amplifier circuit and a band-gap reference core circuit. The current bias circuit, the compensating current circuit, the starting circuit, the folded cascode operational amplifier circuit and the band-gap reference core circuit are all connected to VDD and GND, and the compensating current circuit and the band-gap reference core circuit are both connected to voltage VCOMP. The starting circuit, the folded cascode operational amplifier circuit and the band-gap reference core circuit are connected to an operational amplifier output voltage VOUT, the starting circuit and the band-gap reference core circuit are connected to a band-gap reference output voltage VREF, and the folded cascode operational amplifier circuit is connected to a bias voltage Vb1 and a bias voltage Vb2. The folded cascode operational amplifier circuit and the band-gap reference core circuit are connected to a node X and a node Y.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a segmented compensation low temperature coefficient bandgap reference circuit. Background Technology

[0002] In DC-DC converters, the stability and accuracy of the output voltage are highly correlated with the stability and accuracy of the bandgap reference circuit's output voltage. Generally, the bandgap reference is integrated internally on the chip, providing a reference voltage and a certain degree of drive capability as a separate module. Compared to an external bandgap reference source, an internal bandgap reference offers higher stability. Summary of the Invention

[0003] The purpose of this invention is to address the aforementioned technical problems by providing a segmented compensation low temperature coefficient bandgap reference circuit, which can achieve a lower temperature coefficient using segmented temperature compensation technology.

[0004] To achieve the above objectives, this utility model provides the following solution:

[0005] A segmented compensated low-temperature coefficient bandgap reference circuit includes: a current bias circuit, a compensation current circuit, a startup circuit, a folded cascode operational amplifier circuit, and a bandgap reference core circuit. The current bias circuit, compensation current circuit, startup circuit, folded cascode operational amplifier circuit, and bandgap reference core circuit are all connected to VDD and GND. The compensation current circuit and bandgap reference core circuit are both connected to a voltage VDD. COMP The startup circuit, the folded cascode operational amplifier circuit, and the bandgap reference core circuit are all connected to the operational amplifier output voltage V. OUT The startup circuit and the core circuit of the bandgap reference are both connected to the output voltage V of the bandgap reference. REF The folded cascode operational amplifier circuit is connected to bias voltages Vb1 and Vb2, and both the folded cascode operational amplifier circuit and the bandgap reference core circuit are connected to nodes X and Y.

[0006] Preferably, the current bias circuit includes: PMOS transistors M1-MM7, M9-MM13, NMOS transistor M8, NPN BJT transistors Q1-Q9, and resistors R1 and R2; wherein the sources of M1, M9, M10, M11, M12, and M13 are interconnected with VDD; the gates of M1-M8 are interconnected with the enable port EN; the drain of M1 is interconnected with the source of M2; the drain of M2 is interconnected with the source of M3; the drain of M3 is interconnected with the source of M4; the drain of M4 is interconnected with the source of M5; the drain of M5 is interconnected with the source of M6; the drain of M6 is interconnected with the source of M7; the drains of M7, M8, and M9, the base and collector of Q3, and the base of Q4 are interconnected. The gates of M9, M10, and M12, and the collector of Q4 are interconnected; the emitters of Q3, Q2, and Q1 are interconnected; the emitters of Q4, Q1, and Q2 are interconnected; the emitter of Q2 is connected to the first terminal of R1; the drain of M12, the collector of Q6, and the base of Q7 are interconnected; the gate of M11, the collector of Q7, and the gate and drain of M13 are interconnected; the drain of M11, the base and collector of Q5, and the base of Q6 are interconnected; the emitter of Q5 is connected to the first terminal of R2; the emitter of Q6 is connected to the base and collector of Q8; the emitter of Q7 is connected to the base and collector of Q9; the source of M8, the emitter of Q1, the second terminal of R1, the second terminal of R2, the emitter of Q8, and the emitter of Q9 are interconnected to GND.

[0007] Preferably, the current compensation circuit includes: PMOS transistors M14, M15, M17, M18, and M19; NMOS transistors M20 to M27; and resistors R3 and R4. The sources of M14, M15, M17, M18, and M19 are interconnected with VDD; the gates of M14 and M15 are connected to the gate of M10; the gates of M17, M19, and M13 are interconnected; and the gates of M18 and M23, and the drains of M24 are interconnected with voltage VDD. COMP M14 drain, M20 drain and gate, M21 gate are interconnected; M17 drain, M21 drain, M22 drain and gate, M23 gate are interconnected; M15 drain, M24 gate, M25 gate and drain, M26 drain are interconnected; M19 drain, M26 gate, M27 gate and drain are interconnected; M23 source is connected to the first terminal of R3; M24 source is connected to the first terminal of R4; M20 source, M21 source, M22 source, the second terminal of R3, the second terminal of R4, M25 source, M26 source, M27 source are interconnected and connected to GND.

[0008] Preferably, the startup circuit includes: resistor R6, capacitor C1, NMOS transistors M33, M34, and M35; wherein, the first terminal of R6 is connected to VDD; the second terminal of R6, the drain and gate of M33, the gate of M34, and the first terminal of C1 are interconnected; the drain of M35 is connected to the operational amplifier output voltage VDD. OUT M33 gate connection to bandgap reference output voltage V REF The source terminals of M33, M34, and M35, and the second terminal of C1 are connected to GND.

[0009] Preferably, the folded common-source common-gate operational amplifier circuit includes: PMOS transistors M16, M28, M29, M36-M42, NMOS transistors M30, M31, M32, M43, M44, M45, and M46, resistors R5 and R7, and capacitor C2; wherein, the sources of M16, M28, M36, M39, and M40, and the first terminal of C2 are connected to VDD; the gates of M16 and M36 are connected to the gate of M10; the drains of M16, M31, M32, M45, and M46 are interconnected with the bias voltage Vb1; the gate of M28, the drain of M29, and the first terminal of R5 are interconnected; the drain of M28 is connected to the source of M29; and the gate of M29 and the second terminal of R5 are interconnected. The gates and drains of M30, M43, and M44 are connected to the bias voltage Vb2; the source of M30 is connected to the drain of M32; the drains of M36, M37, and M38 are connected; the gate of M37 is connected to node Y; the gate of M38 is connected to node X; the drains of M37, M43, and M45 are connected; the drains of M38, M44, and M46 are connected; the gates of M39, M41, the first terminal of R7, and the gate of M40 are connected; the gates of M41 and M42, the second terminal of R7, and the drain of M43 are connected; the drain of M39 is connected to the source of M41; the drain of M40 is connected to the source of M42; the drains of M42 and M44, and the second terminal of C2 are connected to the operational amplifier output voltage Vb2. OUT The M31, M32, M45, and M46 sources are interconnected with CND.

[0010] Preferably, the bandgap reference core circuit includes: PMOS transistors M47, M48, M49, and M50; NPN BJT transistors Q10 and Q11; and resistors R8, R9, R10, and R11. The sources of M47, M48, M49, and M50 are interconnected with VDD, and the gates of M47, M48, and M49 are connected to the operational amplifier output voltage VDD. OUT The gates of M50 and M18 are interconnected with voltage V. COMPThe drain of M47, the first terminal of R8, and the first terminal of M9 are connected to node X; the drain of M48, the first terminal of R10, the base and collector of Q11 are connected to node Y; the second terminal of R9 is connected to the base and collector of Q10; the drain of M49, the drain of M50, and the first terminal of R11 are connected to the bandgap reference output voltage V. REF The second terminal of R8, the emitter of Q10, the emitter of Q11, the second terminal of R10, and the second terminal of R11 are connected to GND.

[0011] The beneficial effects of this utility model are as follows:

[0012] This invention employs a segmented temperature compensation technique to achieve a low temperature coefficient. It uses a folded common-source cascode operational amplifier circuit to clamp the X and Y node voltages of the bandgap reference core circuit, ensuring its performance. Furthermore, the design minimizes the mismatch between the input transistors and the current mirror to guarantee the output voltage V. REF The accuracy; the current bias circuit generates positive and negative thermostatic currents, which are then processed to produce a compensation current I. COMP to I REF Compensation is performed to reduce the output voltage V. REF Temperature coefficient; startup circuit ensures that the bandgap reference core circuit can start normally. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the segmented compensation low temperature coefficient bandgap reference circuit structure according to an embodiment of the present invention.

[0015] Figure 2 This is a core circuit diagram of the bandgap reference according to an embodiment of the present invention;

[0016] Figure 3 The uncompensated output voltage V in this embodiment of the invention REF Simulation result diagram;

[0017] Figure 4 The compensation current I in this embodiment of the utility model COMP Simulation result diagram;

[0018] Figure 5 The output voltage V of this utility model embodiment REF Simulation result diagram;

[0019] Figure 6 The output voltage V of this utility model embodiment REF The Monte Carlo simulation results are shown in the figure. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] This embodiment provides a segmented compensation low temperature coefficient bandgap reference circuit, such as... Figure 1 , Figure 2 As shown, it includes: a current bias circuit, a current compensation circuit, a startup circuit, a folded cascode operational amplifier circuit, and a bandgap reference core circuit. The current bias circuit, current compensation circuit, startup circuit, folded cascode operational amplifier circuit, and bandgap reference core circuit are all connected to VDD and GND. The current compensation circuit and bandgap reference core circuit are both connected to voltage VDD. COMP The startup circuit, the folded cascode operational amplifier circuit, and the bandgap reference core circuit are all connected to the operational amplifier output voltage V. OUT The startup circuit and the core circuit of the bandgap reference are both connected to the output voltage V of the bandgap reference. REF The folded cascode operational amplifier circuit is connected to bias voltages Vb1 and Vb2, and both the folded cascode operational amplifier circuit and the bandgap reference core circuit are connected to nodes X and Y.

[0023] Specifically, this embodiment employs a segmented temperature compensation technique to achieve a low temperature coefficient. A folded cascode operational amplifier circuit is used to clamp the X and Y node voltages of the bandgap reference core circuit, ensuring its performance. Furthermore, the design minimizes the mismatch between the input transistors and the current mirror to guarantee the output voltage V. REF The accuracy; the current bias circuit generates positive and negative thermostatic currents, which are then processed to produce a compensation current I. COMP to I REF Compensation is performed to reduce the output voltage V. REF Temperature coefficient; startup circuit ensures that the bandgap reference core circuit can start normally.

[0024] Further, the current bias circuit includes: PMOS transistors M1-M7, M9-M13, NMOS transistor M8, NPN BJT transistors Q1-Q9, and resistors R1 and R2; wherein, the sources of M1, M9, M10, M11, M12, and M13 are interconnected with VDD; the gates of M1-M8 are interconnected with the enable port EN; the drain of M1 is interconnected with the source of M2; the drain of M2 is interconnected with the source of M3; the drain of M3 is interconnected with the source of M4; the drain of M4 is interconnected with the source of M5; the drain of M5 is interconnected with the source of M6; the drain of M6 is interconnected with the source of M7; the drains of M7, M8, and M9, the base and collector of Q3, and the base of Q4 are interconnected; The gates of M9, M10, and M12, and the collector of Q4 are interconnected; the emitters of Q3, Q2, and Q1 are interconnected; the emitters of Q4, Q1, and Q2 are interconnected; the emitter of Q2 is connected to the first terminal of R1; the drain of M12, the collector of Q6, and the base of Q7 are interconnected; the gate of M11, the collector of Q7, and the gate and drain of M13 are interconnected; the drain of M11, the base and collector of Q5, and the base of Q6 are interconnected; the emitter of Q5 is connected to the first terminal of R2; the emitter of Q6 is connected to the base and collector of Q8; the emitter of Q7 is connected to the base and collector of Q9; the source of M8, the emitter of Q1, the second terminal of R1, the second terminal of R2, the emitter of Q8, and the emitter of Q9 are interconnected and connected to GND.

[0025] Further, the current compensation circuit includes: PMOS transistors M14, M15, M17, M18, and M19; NMOS transistors M20 to M27; and resistors R3 and R4. The sources of M14, M15, M17, M18, and M19 are interconnected with VDD; the gates of M14 and M15 are connected to the gate of M10; the gates of M17, M19, and M13 are interconnected; and the gates of M18 and M23, and the drains of M24 are interconnected with voltage VDD. COMP M14 drain, M20 drain and gate, M21 gate are interconnected; M17 drain, M21 drain, M22 drain and gate, M23 gate are interconnected; M15 drain, M24 gate, M25 gate and drain, M26 drain are interconnected; M19 drain, M26 gate, M27 gate and drain are interconnected; M23 source is connected to the first terminal of R3; M24 source is connected to the first terminal of R4; M20 source, M21 source, M22 source, the second terminal of R3, the second terminal of R4, M25 source, M26 source, M27 source are interconnected and connected to GND.

[0026] Furthermore, the startup circuit includes: resistor R6, capacitor C1, NMOS transistors M33, M34, and M35; wherein, the first terminal of R6 is connected to VDD; the second terminal of R6, the drain and gate of M33 and M34, the gate of M35, and the first terminal of C1 are interconnected; the drain of M35 is connected to the operational amplifier output voltage VDD. OUT M33 gate connection to bandgap reference output voltage V REF The source terminals of M33, M34, and M35, and the second terminal of C1 are connected to GND.

[0027] Further, the folded common-source common-gate operational amplifier circuit includes: PMOS transistors M16, M28, M29, M36 to MM42, NMOS transistors M30, M31, M32, M43, M44, M45 and M46, resistors R5 and R7, and capacitor C2; wherein, the sources of M16, M28, M36, M39, and M40, and the first terminal of C2 are connected to VDD; the gates of M16 and M36 are connected to the gate of M10; the drains of M16, the gates of M31 and M32, the gates of M45 and M46 are interconnected with the bias voltage Vb1; the gate of M28, the drain of M29, and the first terminal of R5 are interconnected; the drain of M28 is connected to the source of M29; the gate of M29 and the second terminal of R5 are interconnected. The gates and drains of M30, M43, and M44 are connected to the bias voltage Vb2; the source of M30 is connected to the drain of M32; the drains of M36, M37, and M38 are connected; the gate of M37 is connected to node Y; the gate of M38 is connected to node X; the drains of M37, M43, and M45 are connected; the drains of M38, M44, and M46 are connected; the gates of M39, M41, the first terminal of R7, and the gate of M40 are connected; the gates of M41, M42, the second terminal of R7, and the drain of M43 are connected; the drain of M39 is connected to the source of M41; the drain of M40 is connected to the source of M42; the drains of M42 and M44, and the second terminal of C2 are connected to the operational amplifier output voltage Vb2. OUT The sources M31, M32, M45, and M46 are interconnected with GND.

[0028] Furthermore, the bandgap reference core circuit includes: PMOS transistors M47, M48, M49, and M50; NPN BJT transistors Q10 and Q11; and resistors R8, R9, R10, and R11. The sources of M47, M48, M49, and M50 are interconnected with VDD, and the gates of M47, M48, and M49 are connected to the operational amplifier output voltage VDD. OUT The gates of M50 and M18 are interconnected with voltage V. COMPThe drain of M47, the first terminal of R8, and the first terminal of M9 are connected to node X; the drain of M48, the first terminal of R10, the base and collector of Q11 are connected to node Y; the second terminal of R9 is connected to the base and collector of Q10; the drain of M49, the drain of M50, and the first terminal of R11 are connected to the bandgap reference output voltage V. REF The second terminal of R8, the emitter of Q10, the emitter of Q11, the second terminal of R10, and the second terminal of R11 are connected to GND.

[0029] Specifically, in this embodiment, the bandgap reference core circuit and the folded cascode operational amplifier circuit form a negative feedback loop. The folded cascode operational amplifier circuit clamps the X-node voltage and Y-node voltage of the bandgap reference core circuit, making them equal. Therefore, the voltage difference across resistor R9 can be expressed as:

[0030]

[0031] To ensure matching accuracy and reduce error, Q10 and Q11 should be transistors of the same type and with identical parameters, then I... s =I s11 =I s10 If the quantity ratio is set to MQ10:Q11 = 8:1, then ΔV BE =V T ln 8 is a voltage with a positive temperature coefficient. Therefore, the current flowing through R9 is a positive temperature coefficient current, expressed as I. PTAT express:

[0032]

[0033] Since the voltages at nodes X and Y are equal, and the resistances of R8 and R10 are equal with voltages of V each, this also applies to other nodes. BE11 This is a voltage with a negative temperature coefficient, therefore equal negative temperature coefficient currents flow through R8 and MR10, represented by I. CTAT express:

[0034]

[0035] At this point, the currents on MOSFETs M47 and M48 are the superposition of positive and negative temperature currents. By selecting appropriate resistors R9, R8, and R10, the zero-temperature current V can be obtained. REF and zero-temperature voltage MV REF I REF and V REF It can be represented as:

[0036]

[0037] However, in reality, the negative temperature coefficient voltage V BEThe relationship between the absolute temperature and absolute temperature is not perfectly linear; its expression is:

[0038]

[0039] Where (γ-α)V T ln(T / T0) is not linearly related to temperature, therefore, adjusting the resistance values ​​of R9, R8, and R10 to compensate for the temperature coefficient can only eliminate V. CTAT The linear term in the equation will affect V if the temperature range is too large. REF The temperature coefficient of voltage, the result is as follows Figure 3 As shown, the temperature coefficient is small in the range of 0℃-70℃, but it is large in the high-temperature and low-temperature ranges. REF Voltage varies considerably with temperature.

[0040] To improve this situation, this embodiment introduces a temperature compensation current to improve V. REF The temperature coefficient, in the low-temperature range V REF Voltage exhibits a positive temperature trend; within this temperature range, I... REF Compensation with a negative temperature current improves its temperature characteristics; in the high temperature range V REF The voltage exhibits a negative temperature characteristic; when I is applied within this temperature range... REF Compensation with a positive temperature current improves its temperature characteristics.

[0041] The specific implementation is shown in the compensation current circuit, which generates two compensation currents, which are then superimposed and copied to MM50 via M18, and finally superimposed onto I. REF Then change V REF Temperature characteristics. Wherein:

[0042] I1(T)=K1(I c1 -I p1 ),I2(T)=K2(I p2 -I c2 );

[0043] Current I c1 and I c2 For negative temperature current, I p1 and I p2 Since IT is a positive temperature current, I1(T) is a negative temperature current, and I2(T) is a positive temperature current. By adjusting IT... c1 I c2 I p1 and I p2 The magnitude of the compensation current can be changed to alter the temperature points T1 and T2 when I1(T) and I2(T) are zero. In this invention, T1 is set to 0℃ and T2 is set to 70℃. The magnitude of the compensation current is adjusted by setting the resistance values ​​of R3 and R4. The actual result of the compensation current is as follows: Figure 4 As shown. The output voltage V after compensation.REF like Figure 5 , Figure 6 As shown, it can be represented as:

[0044] V REF =(I REF +I COMP )×R 11 ;

[0045] The output voltage V can be adjusted by adjusting the resistance value of R11. REF And it is independent of temperature. V REF Besides temperature, the output voltage V is also affected by other factors. These factors should be mitigated as much as possible during the design process. These include mismatches in the current mirror circuit manufacturing process, input offset voltage of the operational amplifier, mismatches in the transistor emitter-base junction area and base parasitic resistance, transistor manufacturing errors, resistor temperature coefficients, and process deviations. All of these factors can affect the output voltage V. REF Temperature coefficient and accuracy.

[0046] To ensure the output voltage V REF To ensure accuracy, several aspects need to be considered during the design. The current mirror needs to have a larger L value to reduce its mismatch. All resistors should be of the same type and have a larger W value to reduce mismatch. The NPN transistor uses a 4μm*4μm specification to reduce the error caused by its base parasitic resistance. A compensation capacitor C2 is added to the loop to compress the loop bandwidth and give the loop sufficient phase margin.

[0047] The operational amplifiers employ a folded cascode structure. To reduce input pair transistor offset, M37 and M38 use a larger aspect ratio to increase their gm and thus increase the gain. M39, M40, M45, and M46 use a larger L value to reduce their offset. Their bias voltage is given by the self-bias voltage generated by the same current flowing through the same transistor.

[0048] The current bias circuit passes through ΔV BE / R and V BE The positive and negative temperature currents are generated in the / R manner. M1-M8 are the start-up circuits for the positive temperature current generation circuit. The circuit is started when the EN signal is low. The start-up circuit is not turned off. The width-to-length ratio of M9:M10 is designed to be 1:2 to ensure the matching degree of the currents on both sides.

[0049] The startup circuit starts upon power-on, converting the operational amplifier output voltage V... OUT Pull low, at output voltage V REF When the voltage exceeds the threshold voltage of M33, M33 turns on and the startup circuit turns off.

[0050] The embodiments described above are merely preferred embodiments of the present utility model and are not intended to limit the scope of the present utility model. Any modifications and improvements made to the technical solutions of the present utility model by those skilled in the art without departing from the spirit of the present utility model should fall within the protection scope defined by the claims of the present utility model.

Claims

1. A segmented compensation low temperature coefficient bandgap reference circuit, characterized in that, include: The system includes a current bias circuit, a current compensation circuit, a startup circuit, a folded cascode operational amplifier circuit, and a bandgap reference core circuit. The current bias circuit, current compensation circuit, startup circuit, folded cascode operational amplifier circuit, and bandgap reference core circuit are all connected to VDD and GND. The current compensation circuit and bandgap reference core circuit are both connected to voltage VDD. COMP The startup circuit, the folded cascode operational amplifier circuit, and the bandgap reference core circuit are all connected to the operational amplifier output voltage V. OUT The startup circuit and the core circuit of the bandgap reference are both connected to the output voltage V of the bandgap reference. REF The folded cascode operational amplifier circuit is connected to bias voltages Vb1 and Vb2, and both the folded cascode operational amplifier circuit and the bandgap reference core circuit are connected to nodes X and Y.

2. The segmented compensation low temperature coefficient bandgap reference circuit according to claim 1, characterized in that, The current bias circuit includes: PMOS transistors M1-M7, M9-M13, NMOS transistor M8, NPN BJT transistors Q1-Q9, and resistors R1 and R2; wherein, the sources of M1, M9, M10, M11, M12, and M13 are interconnected with VDD; the gates of M1-M8 are interconnected with the enable port EN; the drain of M1 is interconnected with the source of M2; the drain of M2 is interconnected with the source of M3; the drain of M3 is interconnected with the source of M4; the drain of M4 is interconnected with the source of M5; the drain of M5 is interconnected with the source of M6; the drain of M6 is interconnected with the source of M7; the drains of M7, M8, and M9, the base and collector of Q3, and the base of Q4 are interconnected; M9... The gate, gate and drain of M10, gate of M12, and collector of Q4 are interconnected; the emitter of Q3, base of Q2, and collector of Q1 are interconnected; the emitter of Q4, base of Q1, and collector of Q2 are interconnected; the emitter of Q2 is connected to the first terminal of R1; the drain of M12, collector of Q6, and base of Q7 are interconnected; the gate of M11, collector of Q7, gate and drain of M13 are interconnected; the drain of M11, base and collector of Q5, and base of Q6 are interconnected; the emitter of Q5 is connected to the first terminal of R2; the emitter of Q6 is connected to the base and collector of Q8; the emitter of Q7 is connected to the base and collector of Q9; the source of M8, emitter of Q1, second terminal of R1, second terminal of R2, emitter of Q8, and emitter of Q9 are interconnected and connected to GND.

3. The segmented compensation low temperature coefficient bandgap reference circuit according to claim 1, characterized in that, The current compensation circuit includes: PMOS transistors M14, M15, M17, M18, and M19; NMOS transistors M20 to M27; and resistors R3 and R4. The sources of M14, M15, M17, M18, and M19 are interconnected with VDD; the gates of M14 and M15 are connected to the gate of M10; the gates of M17, M19, and M13 are interconnected; and the gates of M18 and M24, as well as the drains of M23 and M24, are interconnected with voltage VDD. COMP M14 drain, M20 drain and gate, M21 gate are interconnected; M17 drain, M21 drain, M22 drain and gate, M23 gate are interconnected; M15 drain, M24 gate, M25 gate and drain, M26 drain are interconnected; M19 drain, M26 gate, M27 gate and drain are interconnected; M23 source is connected to the first terminal of R3; M24 source is connected to the first terminal of R4; M20 source, M21 source, M22 source, the second terminal of R3, the second terminal of R4, M25 source, M26 source, M27 source are interconnected and connected to GND.

4. The segmented compensation low temperature coefficient bandgap reference circuit according to claim 1, characterized in that, The startup circuit includes: resistor R6, capacitor C1, NMOS transistors M33, M34, and M35; wherein, the first terminal of R6 is connected to VDD; the second terminal of R6, the drain and gate of M33, the gate of M34, and the first terminal of C1 are interconnected; the drain of M35 is connected to the operational amplifier output voltage VDD. OUT M33 gate connection to bandgap reference output voltage V REF The source terminals of M33, M34, and M35, and the second terminal of C1 are connected to GND.

5. The segmented compensation low temperature coefficient bandgap reference circuit according to claim 1, characterized in that, The folded common-source common-gate operational amplifier circuit includes: PMOS transistors M16, M28, M29, M36~M42, NMOS transistors M30, M31, M32, M43, M44, M45 and M46, resistors R5 and R7, and capacitor C2; wherein, the sources of M16, M28, M36, M39, and M40, and the first terminal of C2 are connected to VDD; the gates of M16 and M36 are connected to the gate of M10; the drains of M16, M31, M32, M45, and M46 are interconnected with the bias voltage Vb1; the gate of M28, the drain of M29, and the first terminal of R5 are interconnected; the drain of M28 is connected to the source of M29; the gate of M29, the second terminal of R5, and M... The gates and drains of M30, M43, and M44 are connected to the bias voltage Vb2; the source of M30 is connected to the drain of M32; the drains of M36, M37, and M38 are connected; the gate of M37 is connected to node Y; the gate of M38 is connected to node X; the drains of M37, M43, and M45 are connected; the drains of M38, M44, and M46 are connected; the gates of M39, M41, the first terminal of R7, and the gate of M40 are connected; the gates of M41 and M42, the second terminal of R7, and the drain of M43 are connected; the drain of M39 is connected to the source of M41; the drain of M40 is connected to the source of M42; the drains of M42 and M44, and the second terminal of C2 are connected to the operational amplifier output voltage Vb2. OUT The sources M31, M32, M45, and M46 are interconnected with GND.

6. The segmented compensation low temperature coefficient bandgap reference circuit according to claim 1, characterized in that, The core circuit of the bandgap reference includes: PMOS transistors M47, M48, M49, and M50; NPN BJT transistors Q10 and Q11; and resistors R8, R9, R10, and R11. The sources of M47, M48, M49, and M50 are interconnected with VDD, and the gates of M47, M48, and M49 are connected to the operational amplifier output voltage VDD. OUT The gates of M50 and M18 are interconnected with voltage V. COMP The drain of M47, the first terminal of R8, and the first terminal of M9 are connected to node X; the drain of M48, the first terminal of R10, the base and collector of Q11 are connected to node Y; the second terminal of R9 is connected to the base and collector of Q10; the drain of M49, the drain of M50, and the first terminal of R11 are connected to the bandgap reference output voltage V. REF The second terminal of R8, the emitter of Q10, the emitter of Q11, the second terminal of R10, and the second terminal of R11 are connected to GND.

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