Active absorption circuit
By introducing an active snubber circuit into the DC-DC converter circuit, the voltage stress of the switching transistor is monitored and controlled, thus solving the problem of high switching stress caused by stray inductance and parasitic capacitance, achieving reduced circuit cost and improved reliability.
Patent Information
- Application Number
- CN202423309175.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2034-12-31
AI Technical Summary
In DC-DC converter circuits, the resonance of stray inductance and parasitic capacitance leads to excessive switching stress, which increases design difficulty and cost, and affects circuit reliability.
An active absorption circuit is adopted, including a reference voltage setting circuit, a first absorption circuit, a comparator circuit, a second absorption circuit, and an inverting logic circuit. By monitoring and controlling the voltage stress of the switching transistor, precise absorption and discharge are achieved.
Precise control of the voltage stress of the switching transistor reduces circuit costs and improves reliability, reduces passive circuit losses, and improves overall system efficiency.
Smart Images
Figure CN223798123U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic circuit technology, specifically to an active absorption circuit. Background Technology
[0002] In DC-DC converter circuit design, due to the presence of stray inductance in the actual circuit or components, when the switching transistor turns off, the current energy in the stray inductance needs to continue to dissipate. However, since the switching transistor is already in the off state, the current in the stray inductance cannot flow through the switching transistor's channel and can only flow through the parasitic capacitance across the switching transistor. Thus, LC resonance occurs between the stray inductance and parasitic capacitance in the circuit. The larger the leakage inductance or the larger the turn-off current, the higher the voltage amplitude generated by this resonance. This voltage amplitude, superimposed on the turn-off voltage platform of the switching transistor, forms the switching stress in the DC-DC converter circuit during operation.
[0003] Switching stress increases the difficulty of DC-DC converter circuit design. During product design, the voltage withstand capability of the switching transistors must exceed the maximum stress that the DC-DC converter circuit may experience under various operating conditions. Simultaneously, to ensure reliability after mass production, the dispersion of leakage inductance in the transformer after mass production must also be considered. Therefore, the selection of switching transistors must allow for a sufficiently large margin. However, using excessively large margins in switching devices can lead to increased costs, or cause risks to the switching devices due to high-stress conditions after prolonged operation.
[0004] In other words, how to provide a new type of active absorption circuit to achieve the technical effect of accurately controlling the voltage stress of the switching transistor and reducing circuit cost is a technical problem that urgently needs to be solved in this field. Utility Model Content
[0005] In view of the above-mentioned problems, the present invention aims to provide an active absorption circuit that solves at least one of the above-mentioned technical problems.
[0006] To at least solve the above-mentioned technical problems, this utility model provides an active absorption circuit. The active absorption circuit is used to absorb the voltage stress generated when the first field-effect transistor Q1 is turned off in a DC-DC converter circuit. The DC-DC converter circuit includes a power supply section, a load section, a first rectifier diode D1, a transformer TX1, and the first field-effect transistor Q1. The positive terminal of the power supply section is connected to the input side of the transformer TX1 (with the same polarity), and the input side of the transformer TX1 (with the opposite polarity) is connected to the drain of the first field-effect transistor Q1. The positive terminal of the first rectifier diode D1 is connected to the output side of the transformer TX1 (with the opposite polarity), and the negative terminal of the first rectifier diode D1 is connected to one end of the load section. The negative terminal of the power supply section, the source of the first field-effect transistor Q1, the other end of the load section, and the output side of the transformer TX1 (with the same polarity) are all grounded. The active absorption circuit includes:
[0007] A reference voltage setting circuit is connected in parallel across the two ends of the load section;
[0008] A first absorption circuit, wherein the first end and the second end of the first absorption circuit are respectively connected to the two ends of the first field-effect transistor Q1.
[0009] A comparator circuit, wherein the first terminal of the comparator circuit is connected to the third terminal of the first absorption circuit, the second terminal of the comparator circuit is connected to the voltage setting terminal of the reference voltage setting circuit, and the third terminal of the comparator circuit is connected to the fourth terminal of the first absorption circuit.
[0010] The second absorption circuit has its first terminal connected to the drain of the first field-effect transistor Q1.
[0011] An inverted logic circuit, wherein the first terminal of the inverted logic circuit is connected to the fourth terminal of the comparator circuit, and the second terminal of the inverted logic circuit is connected to the second terminal of the second absorption circuit.
[0012] Preferably, the power supply section includes:
[0013] DC power supply V1, the positive terminal of which is connected to the input side terminal of transformer TX1, and the negative terminal of DC power supply V1 is grounded;
[0014] The first capacitor C1 is connected in parallel across the two ends of the DC power supply V1.
[0015] Preferably, the load portion includes:
[0016] The first resistor R1 has one end connected to the negative terminal of the first rectifier diode D1, and the other end of the first resistor R1 is grounded.
[0017] The second capacitor C2 is connected in parallel across the two ends of the first resistor R1;
[0018] The reference voltage setting circuit is connected in parallel across the two ends of the first resistor R1.
[0019] Preferably, the first absorption circuit includes:
[0020] The positive terminal of the second rectifier diode D2 is connected to the drain of the first field-effect transistor Q1, and the first terminal of the first absorption circuit is connected to the drain of the first absorption circuit.
[0021] The third capacitor C3 has one end connected to the negative terminal of the second rectifier diode D2, and the other end of the third capacitor C3 is the second terminal of the first absorption circuit and connected to the source of the first field-effect transistor Q1.
[0022] The second resistor R2, one end of which is connected to one end of the third capacitor C3;
[0023] The third resistor R3 has one end connected to the other end of the second resistor R2, and the other end of the third resistor R3 is grounded.
[0024] The fourth capacitor C4 is connected in parallel across the two ends of the third resistor R3;
[0025] Wherein, one end of the third resistor R3 is connected to the third terminal of the first absorption circuit and the first terminal of the comparator circuit, and the cathode of the second rectifier diode D2 is connected to the fourth terminal of the first absorption circuit and the third terminal of the comparator circuit.
[0026] Preferably, the reference voltage setting circuit includes:
[0027] The fourth resistor R4, one end of which is connected to one end of the first resistor R1;
[0028] Zener diode D3, the negative terminal of which is connected to the other end of the fourth resistor R4, and the positive terminal of which is grounded;
[0029] The cathode of the Zener diode D3 is connected to the voltage setting terminal of the reference voltage setting circuit and the second terminal of the comparator circuit.
[0030] Preferably, the comparison circuit includes:
[0031] Comparator X1, wherein the non-inverting input terminal of comparator X1 is connected to the first terminal of the comparator circuit and one end of the third resistor R3, the inverting input terminal of comparator X1 is connected to the second terminal of the comparator circuit and the negative terminal of the Zener diode D3, the positive power supply terminal of comparator X1 is connected to the negative terminal of the first rectifier diode D1, and the negative power supply terminal of comparator X1 is grounded.
[0032] The second field-effect transistor Q2 has its gate connected to the output of the comparator X1. The output of the comparator X1 is the fourth terminal of the comparator circuit and is connected to the first terminal of the inverting logic circuit. The drain of the second field-effect transistor Q2 is the third terminal of the comparator circuit and is connected to the negative terminal of the second rectifier diode D2.
[0033] Transistor Q3, the base of transistor Q3 is connected to the source of second field-effect transistor Q2, the emitter of transistor Q3 is grounded, and the collector of transistor Q3 is connected to the output of comparator X1.
[0034] The fifth resistor R5 has one end connected to the collector of the transistor Q3 and the output terminal of the comparator X1, and the other end connected to the positive power supply terminal of the comparator X1.
[0035] The sixth resistor R6 has one end connected to the source of the second field-effect transistor Q2 and the base of the transistor Q3, and the other end connected to the emitter of the transistor Q3.
[0036] Preferably, the second absorption circuit includes:
[0037] The seventh resistor R7, one end of which is connected to the drain of the first field-effect transistor Q1, is the first end of the second absorption circuit.
[0038] The fifth capacitor C5, one end of which is connected to the other end of the seventh resistor R7;
[0039] The fourth field-effect transistor Q4 has its drain connected to the other end of the fifth capacitor C5, its source grounded, and its gate connected to the second terminal of the second absorption circuit and the second terminal of the inverted logic circuit.
[0040] Preferably, the inverse logic circuit includes:
[0041] The fifth field-effect transistor Q5 has its gate connected to the first terminal of the inverted logic circuit and the output terminal of the comparator X1, its source grounded, and its drain connected to the second terminal of the inverted logic circuit and the gate of the fourth field-effect transistor Q4.
[0042] The eighth resistor R8 has one end connected to the drain of the fifth field-effect transistor Q5, and the other end connected to the cathode of the first rectifier diode D1.
[0043] Preferably, the comparison circuit further includes:
[0044] The ninth resistor R9 is connected between the non-inverting input and the output of the comparator X1.
[0045] Preferably, the first field-effect transistor Q1, the second field-effect transistor Q2, the fourth field-effect transistor Q4, and the fifth field-effect transistor Q5 are all NMOS transistors, and the transistor Q3 is an NPN transistor.
[0046] Beneficial effects:
[0047] This invention provides an active absorption circuit for absorbing voltage stress generated when a switching transistor in a DC-DC converter circuit is turned off. The DC-DC converter circuit includes a power supply section, a load section, a first rectifier diode D1, a transformer TX1, and a first field-effect transistor Q1. The power supply section and the first field-effect transistor Q1 are connected to the input side of the transformer TX1. The output side of the transformer TX1 is connected to the load through the first rectifier diode D1 to form a DC-DC voltage conversion circuit. The active absorption circuit includes a reference voltage setting circuit, a first absorption circuit, a comparator circuit, a second absorption circuit, and an inverting logic circuit. The reference voltage setting circuit is connected in parallel across the two ends of the load section. The first and second ends of the first absorption circuit are respectively connected to the two ends of the first field-effect transistor Q1. The first end of the comparator circuit is connected to the third end of the first absorption circuit, the second end of the comparator circuit is connected to the voltage setting end of the reference voltage setting circuit, and the third end of the comparator circuit is connected to the fourth end of the first absorption circuit. The first end of the second absorption circuit is connected to the first field-effect transistor Q1. The drain of transistor Q1 is connected; the first terminal of the inverted logic circuit is connected to the fourth terminal of the comparator circuit, and the second terminal of the inverted logic circuit is connected to the second terminal of the second absorption circuit. A reference voltage value is generated by the reference voltage setting circuit and connected to the comparator circuit. By connecting the comparator circuit to the first absorption circuit, the voltage stress of the first field-effect transistor Q1 is compared with the reference voltage value, thereby realizing the monitoring of voltage stress. When the voltage stress is greater than the reference voltage value, the comparator circuit is activated to release stress. By setting an inverted logic circuit between the comparator circuit and the second absorption circuit, the inverted logic control between the comparator circuit and the second absorption circuit is realized. When the second absorption circuit is turned on, the comparator circuit is not activated. When the voltage stress is less than the reference voltage value, the voltage stress is absorbed by the second absorption circuit. This allows for precise control of the stress voltage of the first field-effect transistor Q1. Furthermore, when selecting Q1, a large withstand voltage margin is not required, further reducing circuit cost while ensuring circuit reliability.
[0048] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description
[0049] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0050] Figure 1 A schematic diagram of the circuit structure of the active absorption circuit provided in Example 1 applied to a DC-DC converter circuit;
[0051] Figure 2 This is a partial structural schematic diagram of the active absorption circuit provided in Embodiment 1.
[0052] Figure label:
[0053] 1. Reference voltage setting circuit;
[0054] 2. First absorption circuit;
[0055] 3. Comparison circuit;
[0056] 4. Second absorption circuit;
[0057] 5. Inverted logic circuit. Detailed Implementation
[0058] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art are within the scope of protection of this utility model; wherein the keyword "and / or" involved in this embodiment indicates two situations, and or. In other words, A and / or B mentioned in the embodiments of this specification indicates two situations, A and B, and A or B, describing three states of A and B. For example, A and / or B means: only A is included but not B; only B is included but not A; and A and B are included.
[0059] Furthermore, in the embodiments of this specification, when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intervening component present. When a component is considered to be "set on" another component, it can be directly set on the other component or there may be an intervening component present.
[0060] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0061] Example 1
[0062] Please see Figure 1-2This embodiment provides an active absorption circuit for absorbing the voltage stress generated when the first field-effect transistor Q1 is turned off in a DC-DC converter circuit. The DC-DC converter circuit includes a power supply section, a load section, a first rectifier diode D1, a transformer TX1, and the first field-effect transistor Q1. The positive terminal of the power supply section is connected to the input terminal of the transformer TX1, and the input terminal of the transformer TX1 is connected to the drain of the first field-effect transistor Q1. The positive terminal of the first rectifier diode D1 is connected to the output terminal of the transformer TX1, and the negative terminal of the first rectifier diode D1 is connected to one end of the load section. The negative terminal of the power supply section, the source of the first field-effect transistor Q1, the other end of the load section, and the output terminal of the transformer TX1 are all grounded. The active absorption circuit includes a reference voltage setting circuit 1, a first absorption circuit 2, a comparator circuit 3, a second absorption circuit 4, and an inverting logic circuit 5. The reference voltage setting circuit 1 is connected in parallel across the two ends of the load section. The first and second ends of the first absorption circuit 2 are respectively connected to the two ends of the first field-effect transistor Q1. The first end of the comparator circuit 3 is connected to the third end of the first absorption circuit 2, the second end of the comparator circuit 3 is connected to the voltage setting terminal of the reference voltage setting circuit 1, and the third end of the comparator circuit 3 is connected to the fourth end of the first absorption circuit 2. The first end of the second absorption circuit 4 is connected to the drain of the first field-effect transistor Q1. The first end of the inverting logic circuit 5 is connected to the fourth end of the comparator circuit 3, and the second end of the inverting logic circuit 5 is connected to the second end of the second absorption circuit 4.
[0063] This invention provides an active absorption circuit for absorbing voltage stress generated when a switching transistor in a DC-DC converter is turned off. The DC-DC converter includes a power supply section, a load section, a first rectifier diode D1, a transformer TX1, and a first field-effect transistor Q1. The power supply section and the first field-effect transistor Q1 are connected to the input side of the transformer TX1. The output side of the transformer TX1 is connected to the load through the first rectifier diode D1 to form a DC-DC voltage conversion circuit. The active absorption circuit includes a reference voltage setting circuit 1, a first absorption circuit 2, a comparator circuit 3, a second absorption circuit 4, and an inverting logic circuit 5. The reference voltage setting circuit 1 is connected in parallel across the two ends of the load section. The first and second ends of the first absorption circuit 2 are respectively connected to the two ends of the first field-effect transistor Q1. The first end of the comparator circuit 3 is connected to the third end of the first absorption circuit 2, the second end of the comparator circuit 3 is connected to the voltage setting terminal of the reference voltage setting circuit 1, and the third end of the comparator circuit 3 is connected to the fourth end of the first absorption circuit 2. The first end of the second absorption circuit 4 is connected to the first field-effect transistor Q1. The drain of transistor Q1 is connected; the first terminal of the inverting logic circuit 5 is connected to the fourth terminal of the comparator circuit 3, and the second terminal of the inverting logic circuit 5 is connected to the second terminal of the second absorption circuit 4, so that a reference voltage value is generated by the reference voltage setting circuit 1 and connected to the comparator circuit 3. By connecting the comparator circuit 3 to the first absorption circuit 2, the voltage stress of the first field-effect transistor Q1 is compared with the reference voltage value through the comparator circuit 3, thereby realizing the monitoring of voltage stress. When the voltage stress is greater than the reference voltage value, the comparator circuit 3 is activated to release stress. By setting an inverting logic circuit 5 between the comparator circuit 3 and the second absorption circuit 4, the inverting logic control between the comparator circuit 3 and the second absorption circuit 4 is realized. When the second absorption circuit 4 is turned on, the comparator circuit 3 is not activated, so when the voltage stress is less than the reference voltage value, the voltage stress is absorbed through the second absorption circuit 4. This can achieve precise control of the stress voltage of the first field-effect transistor Q1, and when Q1 is selected, a large withstand voltage margin is not required, further reducing circuit cost while ensuring circuit reliability.
[0064] The negative terminal of the first rectifier diode D1 is also connected to the power supply terminals of the comparator circuit 3 and the inverted logic circuit 5, respectively, to provide voltage to the comparator circuit 3 and the inverted logic circuit 5.
[0065] In one possible implementation, the power supply section includes a DC power supply V1 and a first capacitor C1. The positive terminal of the DC power supply V1 is connected to the input side of the transformer TX1, and the negative terminal of the DC power supply V1 is grounded. The first capacitor C1 is connected in parallel across the two ends of the DC power supply V1.
[0066] Furthermore, the load section includes a first resistor R1 and a second capacitor C2. One end of the first resistor R1 is connected to the negative terminal of the first rectifier diode D1, and the other end of the first resistor R1 is grounded. The second capacitor C2 is connected in parallel across the two ends of the first resistor R1. The reference voltage setting circuit 1 is connected in parallel across the two ends of the first resistor R1.
[0067] Specifically, the active absorption circuit provided in this application is used to absorb the voltage stress generated when the first field-effect transistor Q1 in the DC-DC converter circuit is turned off. The DC-DC converter circuit is a flyback topology, wherein the DC power supply V1 is the input voltage, the first capacitor C1 is the DC-DC input filter capacitor, the first field-effect transistor Q1 is the flyback switching transistor, the first rectifier diode D1 is the flyback output rectifier diode, the second capacitor C2 is the flyback output filter capacitor, and the first resistor R1 is the flyback output load resistor. The basic working principle of this DC-DC converter circuit is to utilize the energy stored and released by the transformer when the switching transistor is turned on and off to achieve electrical energy conversion. Specifically, when the first field-effect transistor Q1 is turned on, the input voltage V1 flows through the primary winding P1 of the transformer. At this time, due to the same polarity, the voltage in the secondary winding S1 is reversed, the first rectifier diode D1 is cut off, and the transformer does not supply power to the load. Simultaneously, the primary winding P1 begins to store energy. When the first field-effect transistor Q1 is turned off, the current in the primary winding P1 is suddenly interrupted. According to Lenz's law, a forward voltage is induced in the secondary winding S1, the first rectifier diode D1 is turned on, and the energy stored in the transformer is released to the load and the output filter capacitor C2 through the secondary winding S1. The gate of the first field-effect transistor Q1 is connected to the control chip of the external power circuit, and the PWM wave emitted by the control chip periodically controls the on / off state of the first field-effect transistor Q1.
[0068] In one possible implementation, the first absorption circuit 2 includes a second rectifier diode D2, a third capacitor C3, a second resistor R2, a third resistor R3, and a fourth capacitor C4. The anode of the second rectifier diode D2 is the first terminal of the first absorption circuit 2 and connected to the drain of the first field-effect transistor Q1. One end of the third capacitor C3 is connected to the cathode of the second rectifier diode D2, and the other end of the third capacitor C3 is the second terminal of the first absorption circuit 2 and connected to the source of the first field-effect transistor Q1. One end of the second resistor R2 is connected to one end of the third capacitor C3. One end of the third resistor R3 is connected to the other end of the second resistor R2, and the other end of the third resistor R3 is grounded. The fourth capacitor C4 is connected in parallel across the two ends of the third resistor R3. One end of the third resistor R3 is the third terminal of the first absorption circuit 2 and connected to the first terminal of the comparator circuit 3, and the cathode of the second rectifier diode D2 is the fourth terminal of the first absorption circuit 2 and connected to the third terminal of the comparator circuit 3.
[0069] Specifically, the second rectifier diode D2 and the third capacitor C3 are connected across the first field-effect transistor Q1, forming the absorption circuit for Q1. When Q1 is turned off and stress is generated, this voltage stress is stored in the third capacitor C3 through the unidirectional conduction of D2. The upper ends of resistors R2 and R3 are connected to the third capacitor C3. The voltage of C3 is monitored by voltage division sampling. When the voltage on R3 exceeds the set threshold Vref, comparator X1 outputs a high level, turning on the second field-effect transistor Q2. Thus, it can be seen that by setting the voltage divider between R2 and R3, the voltage on the third capacitor C3 can be precisely controlled, and the voltage on the third capacitor C3 is the stress voltage of the first field-effect transistor Q1.
[0070] In one possible implementation, the reference voltage setting circuit 1 includes a fourth resistor R4 and a Zener diode D3. One end of the fourth resistor R4 is connected to one end of the first resistor R1. The cathode of the Zener diode D3 is connected to the other end of the fourth resistor R4, and the anode of the Zener diode D3 is grounded. The cathode of the Zener diode D3 is the voltage setting terminal of the reference voltage setting circuit 1 and the second terminal of the comparator circuit 3.
[0071] Specifically, Zener diode D3 is a voltage reference source, and the fourth resistor R4 is a current-limiting resistor. A reference voltage value Vref is generated through R4 and D3. Vref is connected to the inverting input of comparator X1 to monitor the voltage stress of Q1 based on this reference voltage value Vref.
[0072] In one possible implementation, the comparator circuit 3 includes a comparator X1, a second field-effect transistor Q2, a transistor Q3, a fifth resistor R5, and a sixth resistor R6. The non-inverting input of comparator X1 is connected to the first terminal of comparator circuit 3 and one end of the third resistor R3. The inverting input of comparator X1 is connected to the second terminal of comparator circuit 3 and the cathode of Zener diode D3. The positive power supply terminal of comparator X1 is connected to the power supply terminal of comparator circuit 3 and the cathode of the first rectifier diode D1. The negative power supply terminal of comparator X1 is grounded. The gate of the second field-effect transistor Q2 is connected to the output terminal of comparator X1. The output terminal of comparator X1 is connected to the fourth terminal of comparator circuit 3 and the first terminal of inverting logic circuit 5. The drain of the second field-effect transistor Q2 is connected to the third terminal of the comparator circuit 3 and the negative terminal of the second rectifier diode D2; the base of transistor Q3 is connected to the source of the second field-effect transistor Q2, the emitter of transistor Q3 is grounded, and the collector of transistor Q3 is connected to the output terminal of comparator X1; one end of the fifth resistor R5 is connected to the collector of transistor Q3 and the output terminal of comparator X1 respectively, and the other end of the fifth resistor R5 is connected to the positive power supply terminal of comparator X1, which is equivalent to connecting to the negative terminal of the second rectifier diode D2; one end of the sixth resistor R6 is connected to the source of the second field-effect transistor Q2 and the base of transistor Q3 respectively, and the other end of the sixth resistor R6 is connected to the emitter of transistor Q3.
[0073] Specifically, the upper end of the second MOSFET Q2 is connected to the third capacitor C3, and the lower end is grounded through R6. When the second MOSFET Q2 is turned on, the energy stored in capacitor C3 is discharged through Q2 and R6. Then, when the first MOSFET Q1 is turned off again and stress is generated, the leakage inductance energy is stored in C3 again through D2. This circuit can discharge the leakage inductance energy step by step, ensuring that the voltage stress of the first MOSFET Q1 is within a reasonable and safe range. Transistor Q3 and the sixth resistor R6 together form an overcurrent protection circuit. If an abnormal current occurs in the path of Q2 and D2, and the abnormal current exceeds the set value, Q2 will be turned off.
[0074] The PVDD terminal provides an initial level to Q2 through the fifth resistor R5. That is, when the voltage spike is less than the reference voltage, the comparator outputs a low level; when the voltage spike exceeds the set value, the comparator flips, and PVDD provides a high level to Q2 through R5 to turn on Q2 for protection.
[0075] In one possible implementation, the second absorption circuit 4 includes a seventh resistor R7, a fifth capacitor C5, and a fourth field-effect transistor Q4. One end of the seventh resistor R7 is the first end of the second absorption circuit 4 and is connected to the drain of the first field-effect transistor Q1. One end of the fifth capacitor C5 is connected to the other end of the seventh resistor R7. The drain of the fourth field-effect transistor Q4 is connected to the other end of the fifth capacitor C5. The source of the fourth field-effect transistor Q4 is grounded. The gate of the fourth field-effect transistor Q4 is the second end of the second absorption circuit 4 and is connected to the second end of the inverted logic circuit 5.
[0076] Specifically, the switching on and off of the path between the seventh resistor R7 and the fifth capacitor C5 is controlled by the switching on and off of the fourth field-effect transistor Q4. The switching logic of the fourth field-effect transistor Q4 is opposite to that of the second field-effect transistor Q2. That is, when the comparator circuit 3 is started and the comparator X1 outputs a high level, the second field-effect transistor Q2 and the fifth field-effect transistor Q5 are turned on, and the fourth field-effect transistor Q4 is turned off, thus disconnecting the path between R7 and C5. When the comparator X1 outputs a low level, the second field-effect transistor Q2 and the fifth field-effect transistor Q5 are turned off, and the fourth field-effect transistor Q4 is turned on, thus connecting the path between R7 and C5.
[0077] In one possible implementation, the inverting logic circuit 5 includes a fifth field-effect transistor Q5 and an eighth resistor R8. The gate of the fifth field-effect transistor Q5 is the first terminal of the inverting logic circuit 5 and is connected to the output terminal of the comparator X1. The source of the fifth field-effect transistor Q5 is grounded, and the drain of the fifth field-effect transistor Q5 is the second terminal of the inverting logic circuit 5 and is connected to the gate of the fourth field-effect transistor Q4. One end of the eighth resistor R8 is connected to the drain of the fifth field-effect transistor Q5, and the other end of the eighth resistor R8 is the power supply terminal of the inverting logic circuit 5 and is connected to the negative terminal of the first rectifier diode D1.
[0078] Specifically, the inverse logic circuit 5 formed by the fifth field-effect transistor Q5 and the eighth resistor R8 makes the switching logic of Q4 opposite to that of Q2. That is, when Q2 is on, Q4 is off; when Q2 is off, Q4 is on.
[0079] In one possible implementation, the comparator circuit 3 further includes a ninth resistor R9. The seventh resistor R9 is connected between the non-inverting input and output of the comparator X1 to form a hysteresis network in the comparator circuit 3, thereby realizing the hysteresis function of the comparator threshold and ensuring that the auxiliary switch does not frequently turn on and off.
[0080] In one possible implementation, the first field-effect transistor Q1, the second field-effect transistor Q2, the fourth field-effect transistor Q4, and the fifth field-effect transistor Q5 are all NMOS transistors, and the transistor Q3 is an NPN transistor.
[0081] This application provides two stress absorption paths: the R7 and C5 absorption branch and the D2 and Q2 absorption branch, with only one branch conducting at a time. R7 and C5 can only absorb the stress of Q1 under normal operating conditions. Under normal operating conditions, the voltage stress generated by Q1 is less than the set reference voltage value Vref. However, when overcurrent, hardware overvoltage, or large load jumps occur, because the transformer leakage inductance stores a large amount of energy, R7 and C5 are insufficient to release the large leakage inductance energy. Therefore, it is necessary to switch to the Q2 and D2 absorption branch to forcibly release the leakage inductance energy.
[0082] In other words, the circuit principle of this application is:
[0083] Under normal operating conditions, when the stress voltage of Q1 is less than the set reference voltage value Vref, Q2 and Q5 are disconnected and Q4 is turned on. At this time, the absorption branches of D2 and Q2 do not function, and the absorption branches of R7 and C5 are turned on to absorb voltage stress.
[0084] When the outgoing line experiences an abnormally large transient load, the R7 and C5 absorption branches can no longer protect Q1. At this time, the stress voltage of Q1 is greater than the set reference voltage value Vref, Q2 and Q5 are turned on, and Q4 is turned off. At this time, the R7 and C5 absorption branches are turned off, while the D2 and Q2 absorption branches are turned on to discharge leakage inductance energy.
[0085] The active absorption circuit provided in this application is suitable for medium and low voltage circuits, such as circuits with voltages below 800V-900V. The active absorption circuit provided in this application has the following advantages:
[0086] 1. By monitoring and comparing the voltage stress of the first field-effect transistor Q1 through hardware circuitry, the stress optimization of Q1 under various operating conditions can be precisely controlled. The discreteness of other transformer components can be disregarded, which greatly improves the lifespan and reliability of the power supply in the DC-DC converter circuit.
[0087] 2. This active absorption circuit can reduce the losses of passive circuits in the circuit and improve the efficiency of the whole circuit.
[0088] 3. Since the stress voltage of the first field-effect transistor Q1 can be precisely controlled, a large withstand voltage margin is not required when selecting the main switching transistor Q1, which further reduces the cost of the circuit while ensuring its reliability.
[0089] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this invention, should still fall within the scope of the disclosed technical content. Furthermore, the terms "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of this invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this invention.
[0090] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model's technical solution. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the content of the present utility model's technical solution shall still fall within the scope of the present utility model's technical solution.
Claims
1. An active absorption circuit, characterized by, The active absorption circuit is used to absorb voltage stress generated in the DC-DC converter circuit. The DC-DC converter circuit includes a power supply section, a load section, a first rectifier diode D1, a transformer TX1, and a first field-effect transistor Q1. The positive terminal of the power supply section is connected to the input terminal of the transformer TX1, the input terminal of the transformer TX1 is connected to the drain of the first field-effect transistor Q1, the positive terminal of the first rectifier diode D1 is connected to the output terminal of the transformer TX1, and the negative terminal of the first rectifier diode D1 is connected to one end of the load section. The negative terminal of the power supply section, the source of the first field-effect transistor Q1, the other end of the load section, and the output terminal of the transformer TX1 are all grounded. The active absorption circuit includes: A reference voltage setting circuit is connected in parallel across the two ends of the load section; A first absorption circuit, wherein a first terminal of the first absorption circuit is connected to the drain of the first field-effect transistor Q1, and a second terminal of the first absorption circuit is connected to the source of the first field-effect transistor Q1. A comparator circuit, wherein the first terminal of the comparator circuit is connected to the third terminal of the first absorption circuit, the second terminal of the comparator circuit is connected to the voltage setting terminal of the reference voltage setting circuit, and the third terminal of the comparator circuit is connected to the fourth terminal of the first absorption circuit. The second absorption circuit has its first terminal connected to the drain of the first field-effect transistor Q1. An inverted logic circuit, wherein the first terminal of the inverted logic circuit is connected to the fourth terminal of the comparator circuit, and the second terminal of the inverted logic circuit is connected to the second terminal of the second absorption circuit.
2. The active absorption circuit of claim 1, wherein, The power supply section includes: DC power supply V1, the positive terminal of which is connected to the input side terminal of transformer TX1, and the negative terminal of DC power supply V1 is grounded; The first capacitor C1 is connected in parallel across the two ends of the DC power supply V1.
3. The active absorption circuit of claim 2, wherein, The load portion includes: The first resistor R1 has one end connected to the negative terminal of the first rectifier diode D1, and the other end of the first resistor R1 is grounded. The second capacitor C2 is connected in parallel across the two ends of the first resistor R1; The reference voltage setting circuit is connected in parallel across the two ends of the first resistor R1.
4. The active absorption circuit of claim 3, wherein, The first absorption circuit includes: The positive terminal of the second rectifier diode D2 is the first terminal of the first absorption circuit; The third capacitor C3 has one end connected to the negative terminal of the second rectifier diode D2, and the other end of the third capacitor C3 is the second terminal of the first absorption circuit. The second resistor R2, one end of which is connected to one end of the third capacitor C3; The third resistor R3 has one end connected to the other end of the second resistor R2, and the other end of the third resistor R3 is grounded. The fourth capacitor C4 is connected in parallel across the two ends of the third resistor R3; Wherein, one end of the third resistor R3 is the third terminal of the first absorption circuit, and the cathode of the second rectifier diode D2 is the fourth terminal of the first absorption circuit.
5. The active absorption circuit of claim 4, wherein, The reference voltage setting circuit includes: The fourth resistor R4, one end of which is connected to one end of the first resistor R1; Zener diode D3, the negative terminal of which is connected to the other end of the fourth resistor R4, and the positive terminal of which is grounded; The cathode of the Zener diode D3 is the voltage setting terminal of the reference voltage setting circuit.
6. The active absorption circuit of claim 5, wherein, The comparison circuit includes: Comparator X1, wherein the non-inverting input terminal of comparator X1 is the first terminal of the comparator circuit, the inverting input terminal of comparator X1 is the second terminal of the comparator circuit, the positive power supply terminal of comparator X1 is connected to the negative terminal of the first rectifier diode D1, and the negative power supply terminal of comparator X1 is grounded. The second field-effect transistor Q2 has its gate connected to the output terminal of the comparator X1, the output terminal of the comparator X1 being the fourth terminal of the comparator circuit, and the drain of the second field-effect transistor Q2 being the third terminal of the comparator circuit. Transistor Q3, the base of transistor Q3 is connected to the source of second field-effect transistor Q2, the emitter of transistor Q3 is grounded, and the collector of transistor Q3 is connected to the output of comparator X1. The fifth resistor R5 has one end connected to the collector of the transistor Q3 and the output terminal of the comparator X1, and the other end connected to the positive power supply terminal of the comparator X1. The sixth resistor R6 has one end connected to the source of the second field-effect transistor Q2 and the base of the transistor Q3, and the other end connected to the emitter of the transistor Q3.
7. The active absorption circuit of claim 6, wherein, The second absorption circuit includes: The seventh resistor R7, one end of which is the first end of the second absorption circuit; The fifth capacitor C5, one end of which is connected to the other end of the seventh resistor R7; The fourth field-effect transistor Q4 has its drain connected to the other end of the fifth capacitor C5, its source grounded, and its gate the second terminal of the second absorption circuit.
8. The active absorption circuit of claim 7, wherein, The inverse logic circuit includes: The fifth field-effect transistor Q5 has its gate as the first terminal of the inverted logic circuit, its source grounded, and its drain as the second terminal of the inverted logic circuit. The eighth resistor R8 has one end connected to the drain of the fifth field-effect transistor Q5, and the other end connected to the cathode of the first rectifier diode D1.
9. The active absorption circuit as described in claim 8, characterized in that, The comparison circuit further includes: The ninth resistor R9 is connected between the non-inverting input and the output of the comparator X1.
10. The active absorption circuit as described in claim 9, characterized in that: The first field-effect transistor Q1, the second field-effect transistor Q2, the fourth field-effect transistor Q4, and the fifth field-effect transistor Q5 are all NMOS transistors, and the transistor Q3 is an NPN transistor.