Adjustable hysteresis comparator circuit

Abstract

The utility model provides an adjustable hysteresis comparator circuit. The adjustable hysteresis comparator circuit comprises a resistor R1, a resistor R26, a three-terminal adjustable shunt regulator QT1, a voltage stabilizing diode D1, a resistor R28, a PMOS tube Q1, a resistor R27, a resistor R29, a three-terminal adjustable shunt regulator QT2, a resistor R99 and a resistor R100. Threshold adjustment of output comparison can be completed by designing the resistance value of the divider resistor in advance, the oscillation range of the external input voltage is controlled, and the problem of output level jump caused by jitter of the external input voltage is effectively solved.

Description

Technical Field

[0001] This utility model relates to the field of charging pile technology, specifically to an adjustable hysteresis comparator circuit. Background Technology

[0002] Comparators are frequently used devices in circuit design. Common single-threshold comparator circuits have high sensitivity but poor noise immunity; even slight fluctuations in the input voltage around the threshold can cause frequent output level jumps. Most comparators incorporate hysteresis circuits, typically with a hysteresis voltage of 5-10mV. This internal hysteresis prevents output oscillations caused by input voltage jitter. However, if the input voltage jitter is significant, the internal hysteresis will be ineffective, requiring an external hysteresis circuit to mitigate output jumps caused by jitter.

[0003] Therefore, it is necessary to provide a new type of adjustable hysteresis comparator circuit to overcome the above-mentioned defects. Utility Model Content

[0004] The purpose of this invention is to provide an adjustable hysteresis comparator circuit that effectively solves the problem of output level jumps caused by input voltage jitter.

[0005] To achieve the above objectives, the technical solution provided by this utility model is as follows: an adjustable hysteresis comparator circuit, comprising: resistor R1, resistor R26, three-terminal adjustable shunt regulator QT1, Zener diode D1, resistor R28, PMOS transistor Q1, resistor R27, resistor R29, three-terminal adjustable shunt regulator QT2, resistor R99, and resistor R100.

[0006] The first terminal of resistor R1 is connected to the input power supply VIN. The second terminal of resistor R1 is electrically connected to the first terminal of resistor R26 and the R terminal of the three-terminal adjustable shunt regulator QT1. The second terminal of resistor R26 is electrically connected to the A terminal of the three-terminal adjustable shunt regulator QT1 and grounded. The K terminal of the three-terminal adjustable shunt regulator QT1 is electrically connected to the first terminal of resistor R27.

[0007] The cathode of the Zener diode D1, the first terminal of resistor R28, and the source of the PMOS transistor are all electrically connected to the first terminal of resistor R1. The anode of the Zener diode D1 is electrically connected to the second terminal of resistor R28, the gate of the PMOS transistor, and the second terminal of resistor R27. The first terminal of resistor R29 is electrically connected to the second terminal of resistor R27. The second terminal of resistor R29 is electrically connected to the base (K) of the three-terminal adjustable shunt regulator QT2.

[0008] The drain of the NOMS tube is electrically connected to the first terminal of resistor R99. The second terminal of resistor R99 is electrically connected to the first terminal of resistor R100 and the R terminal of the three-terminal adjustable shunt regulator QT2. The second terminal of resistor R100 is electrically connected to the A terminal of the three-terminal adjustable shunt regulator QT2 and grounded.

[0009] Preferably, the adjustable hysteresis comparator circuit further includes capacitors C80 and C81. The first terminal of capacitor C80 is electrically connected to the second terminal of resistor R1, the second terminal of capacitor C80 is electrically connected to the second terminal of resistor R26, the first terminal of capacitor C81 is electrically connected to the second terminal of resistor R99, and the second terminal of capacitor C81 is electrically connected to the second terminal of resistor R100.

[0010] Preferably, the three-terminal adjustable shunt regulator QT1 and the three-terminal adjustable shunt regulator QT2 are of model CJ431.

[0011] Compared with existing technologies, the advantages are: the threshold adjustment of the output comparison can be completed by pre-designing the resistance value of the voltage divider resistor, controlling the oscillation range of the external input voltage, and effectively solving the problem of output level jump caused by external input voltage jitter. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 The circuit diagram of the adjustable hysteresis comparator circuit provided by this utility model. Detailed Implementation

[0014] To make the objectives, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described in this specification are merely for explaining the present utility model and are not intended to limit the present utility model.

[0015] Please see Figure 1 This utility model provides an adjustable hysteresis comparator circuit, including: resistor R1, resistor R26, three-terminal adjustable shunt regulator QT1, Zener diode D1, resistor R28, PMOS transistor Q1, resistor R27, resistor R29, three-terminal adjustable shunt regulator QT2, resistor R99, and resistor R100.

[0016] The first terminal of resistor R1 is connected to the input power supply VIN. The second terminal of resistor R1 is electrically connected to the first terminal of resistor R26 and the R terminal (pin 1) of the three-terminal adjustable shunt regulator QT1. The second terminal of resistor R26 is electrically connected to the A terminal (pin 3) of the three-terminal adjustable shunt regulator QT1 and grounded. The K terminal (pin 2) of the three-terminal adjustable shunt regulator QT1 is electrically connected to the first terminal of resistor R27.

[0017] The cathode of the Zener diode D1, the first terminal of resistor R28, and the source of the PMOS transistor are all electrically connected to the first terminal of resistor R1. The anode of the Zener diode D1 is electrically connected to the second terminal of resistor R28, the gate of the PMOS transistor, and the second terminal of resistor R27. The first terminal of resistor R29 is electrically connected to the second terminal of resistor R27. The second terminal of resistor R29 is electrically connected to the base (K) of the three-terminal adjustable shunt regulator QT2.

[0018] The drain of the NOMS transistor is electrically connected to the first terminal of resistor R99. The second terminal of resistor R99 is electrically connected to the first terminal of resistor R100 and the R terminal of the three-terminal adjustable shunt regulator QT2. The second terminal of resistor R100 is electrically connected to the A terminal of the three-terminal adjustable shunt regulator QT2 and grounded. It should be noted that in this embodiment, the three-terminal adjustable shunt regulators QT1 and QT2 are model CJ431.

[0019] In a preferred embodiment, the adjustable hysteresis comparator circuit further includes capacitors C80 and C81. The first terminal of capacitor C80 is electrically connected to the second terminal of resistor R1, the second terminal of capacitor C80 is electrically connected to the second terminal of resistor R26, the first terminal of capacitor C81 is electrically connected to the second terminal of resistor R99, and the second terminal of capacitor C81 is electrically connected to the second terminal of resistor R100.

[0020] Working principle:

[0021] Resistors R1 and R26 are used as voltage divider resistors. The threshold for enabling the output comparator function is adjusted by changing the resistance values ​​of resistors R1 and R26. The voltage divider point of resistors R1 and R26 is connected to the R terminal of the three-terminal adjustable shunt regulator QT1. If the voltage at the R terminal is ≥2.5V, the A and K terminals of the three-terminal adjustable shunt regulator QT1 are turned on. Then the driving circuit of PMOS transistor Q1, composed of resistors R28 and R27 and the three-terminal adjustable shunt regulator QT1, is turned on, driving PMOS transistor Q1 to turn on and enabling the output comparator function.

[0022] Resistors R99 and R100 are used as voltage divider resistors. The off threshold of the output comparator function is adjusted by changing the resistance values ​​of resistors R99 and R100. The voltage divider point of resistors R99 and R100 is connected to the R terminal of the three-terminal adjustable shunt regulator QT2. If the voltage at the R terminal is ≤2.5V, the A and K terminals of the three-terminal adjustable shunt regulator QT1 are turned off. Then, the Q1 drive circuit composed of resistors R28 and R29 and the three-terminal adjustable shunt regulator QT2 is turned off, driving the PMOS transistor Q1 to turn off, and the output comparator function is turned off.

[0023] The threshold values ​​for enabling and disabling the output comparator function can be arbitrarily designed. The threshold adjustment can be achieved by arbitrarily setting the resistance value of the voltage divider resistor. For example, if the comparator's hysteresis voltage needs to be designed to be 3V, then the output comparator enable threshold is 24V, and the output comparator disable threshold can be designed to be 21V. When the input voltage is ≥24V, the output comparator function is enabled. If the external input voltage oscillates within a range ≤3V, the output comparator function remains enabled. If the input voltage is <21V, the output comparator function is disabled.

[0024] This invention is not limited to the description in the specification and embodiments. Therefore, other advantages and modifications can be readily realized by those skilled in the art. Thus, without departing from the spirit and scope of the general concept as defined by the claims and their equivalents, this invention is not limited to the specific details, representative devices and illustrated examples shown and described herein.

Claims

1. An adjustable hysteresis comparator circuit, characterized in that, include: Resistors R1, R26, QT1 (three-terminal adjustable shunt regulator), D1 (zener diode), R28, Q1 (PMOS transistor), R27, R29, QT2 (three-terminal adjustable shunt regulator), R99, and R100. The first terminal of resistor R1 is connected to the input power supply VIN. The second terminal of resistor R1 is electrically connected to the first terminal of resistor R26 and the R terminal of the three-terminal adjustable shunt regulator QT1. The second terminal of resistor R26 is electrically connected to the A terminal of the three-terminal adjustable shunt regulator QT1 and grounded. The K terminal of the three-terminal adjustable shunt regulator QT1 is electrically connected to the first terminal of resistor R27. The cathode of the Zener diode D1, the first terminal of resistor R28, and the source of PMOS transistor Q1 are all electrically connected to the first terminal of resistor R1. The anode of the Zener diode D1 is electrically connected to the second terminal of resistor R28, the gate of PMOS transistor Q1, and the second terminal of resistor R27. The first terminal of resistor R29 is electrically connected to the second terminal of resistor R27. The second terminal of resistor R29 is electrically connected to the base (K) of the three-terminal adjustable shunt regulator QT2. The drain of the PMOS transistor Q1 is electrically connected to the first terminal of the resistor R99. The second terminal of the resistor R99 is electrically connected to the first terminal of the resistor R100 and the R terminal of the three-terminal adjustable shunt regulator QT2. The second terminal of the resistor R100 is electrically connected to the A terminal of the three-terminal adjustable shunt regulator QT2 and grounded.

2. The adjustable hysteresis comparator circuit as described in claim 1, characterized in that, The adjustable hysteresis comparator circuit further includes capacitors C80 and C81. The first terminal of capacitor C80 is electrically connected to the second terminal of resistor R1, the second terminal of capacitor C80 is electrically connected to the second terminal of resistor R26, the first terminal of capacitor C81 is electrically connected to the second terminal of resistor R99, and the second terminal of capacitor C81 is electrically connected to the second terminal of resistor R100.

3. The adjustable hysteresis comparator circuit as described in claim 1, characterized in that, The three-terminal adjustable shunt regulators QT1 and QT2 are model CJ431.

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