Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure includes a first circuit region having an active region extending longitudinally in a first direction, the active region includes a channel region between a plurality of source / drain (S / D) features, a gate over the channel region, a dielectric structure over the active region and surrounding the active region, a metal contact over one of the source / drain (S / D) features at a fixed point through an upper surface of the dielectric structure, and a first via landing on the metal contact at a fixed point. The semiconductor structure includes a second circuit region having a dielectric structure, a feed-through via passing through an upper surface of the dielectric structure and a lower surface of the dielectric structure, and a second via landing on the feed-through via at a fixed point. The first via and the second via have substantially coplanar lower surfaces.

Description

Technical Field

[0001] This utility model relates to a semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0002] The electronics industry's demand for smaller and faster electronic devices, capable of supporting a greater number of increasingly complex and sophisticated functions, is constantly growing. To meet these demands, the integrated circuit (IC) industry continues to evolve towards low-cost, high-efficiency, and low-power ICs. To date, these goals have been largely achieved by shrinking IC dimensions (e.g., miniaturizing IC feature sizes), thereby increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC manufacturing processes and technologies are needed to achieve further progress in IC devices and their performance.

[0003] One advancement is the use of feedthrough vias to connect signals from the front to the back of a wafer. This allows for flexibility in forming semiconductor features on both the front and back sides of the semiconductor structure. In one example, front-side source / drain features can be connected to back-side power rails via feedthrough vias. However, feedthrough vias are typically expensive due to the space they occupy. For instance, feedthrough vias can be formed within large, dedicated feedthrough cell regions (isolated from transistor circuit regions). These dedicated feedthrough cell regions occupy additional space in the circuit layout. To avoid area loss, better integration between the feedthrough vias and transistor regions is required. For example, feedthrough cell regions can be formed directly between and surrounded by transistor regions.

[0004] However, forming feedthrough vias around transistor circuit regions presents challenges, such as avoiding coupling with nearby transistor contact features, overlay issues when forming feedthrough vias from the back side, and achieving low resistance in a confined area. Therefore, while existing methods for forming feedthrough vias are generally sufficient to meet their intended purpose, they are not entirely satisfactory in every aspect. Utility Model Content

[0005] The purpose of this invention is to propose a semiconductor structure to solve at least one of the above-mentioned problems.

[0006] In some embodiments, a semiconductor structure is provided, comprising: a first circuit region having: an active region extending longitudinally along a first direction, the active region including a channel region located between a plurality of source / drain (S / D) features and a gate located above the channel region; a dielectric structure located above and surrounding the active region; a metal contact passing through an upper surface of the dielectric structure and positioned over one of the source / drain (S / D) features; and a first via positioned on the metal contact. The semiconductor structure includes a second circuit region having: the aforementioned dielectric structure; a feedthrough via penetrating the upper surface and a lower surface of the dielectric structure; and a second via located on the feedthrough via. The first via and the second via have substantially coplanar lower surfaces.

[0007] According to one embodiment of the present invention, the feedthrough via includes an adhesive layer and a via filling layer, wherein the adhesive layer is disposed on the side surface and the upper surface of the via filling layer, and the via filling layer is separated from the second via through the adhesive layer.

[0008] According to one embodiment of the present invention, the feedthrough via includes an adhesive layer and a via filling layer, wherein the adhesive layer is disposed on the side surface of the via filling layer but not on the upper surface of the via filling layer, and the via filling layer directly contacts the second via.

[0009] According to one embodiment of the present invention, the lower surface and side surface of the metal contact are embedded in the dielectric structure, and the lower surface of the metal contact is located below an upper surface of the feedthrough hole.

[0010] According to one embodiment of the present invention, along the first direction, the top width of the feedthrough hole is greater than the bottom width of the metal contact.

[0011] In some embodiments, a semiconductor structure is provided, comprising: a first circuit region having: an active region extending longitudinally along a first direction, the active region including a channel region located between a plurality of source / drain (S / D) features and a gate located above the channel region; a dielectric structure located above and surrounding the active region; a first metal contact having a first portion extending into the dielectric structure by a first distance to be precisely landed on one of the source / drain (S / D) features; and a first via landing precisely on the first metal contact. The semiconductor structure further comprises: a second circuit region having: a second portion of the first metal contact having a lower surface and a side surface directly contacting the dielectric structure; a feedthrough via adjacent to the second portion of the first metal contact and extending into the dielectric structure by a second distance; and a second via landing precisely on the feedthrough via. The second distance is greater than the first distance.

[0012] According to one embodiment of the present invention, it further includes: a back metal located below a lower surface of the dielectric structure, and the feedthrough via landing precisely on an upper surface of the back metal.

[0013] According to one embodiment of the present invention, the first circuit region further includes:

[0014] The active region includes a second channel region located between a plurality of second source / drain features and a second gate located above the second channel region; and a second metal contact having a first portion extending into the dielectric structure by a first distance to land precisely on one of the plurality of second source / drain features; wherein the second circuit region also includes a second portion of the second metal contact, which lands precisely on another horizontal surface of the dielectric structure, and the feedthrough via is laterally disposed between the first metal contact and the second metal contact along the first direction.

[0015] According to one embodiment of the present invention, the dielectric structure has a lower etch stop layer embedded therein, wherein the lower etch stop layer is positioned on an upper surface of the gate, and wherein the first metal contact and the feedthrough via both penetrate the lower etch stop layer.

[0016] According to one embodiment of the present invention, the dielectric structure includes an interlayer dielectric layer surrounding a cut-off metal gate feature, wherein the cut-off metal gate feature separates the feedthrough via from the interlayer dielectric layer, and the feedthrough via penetrates the cut-off metal gate feature, and wherein the interlayer dielectric layer and the cut-off metal gate feature comprise different dielectric materials. Attached Figure Description

[0017] Figure 1AThis is a top view schematic diagram of a semiconductor structure having a feedthrough circuit region surrounded by a transistor circuit region according to an embodiment of the present invention.

[0018] Figures 1B-1D The following is illustrated according to an embodiment of the present invention: Figure 1A A schematic cross-sectional view of a semiconductor structure cut by the B-B' line, C-C' line, and D-D' line.

[0019] Figure 2A This is a top view schematic diagram of a semiconductor structure having a feedthrough circuit region surrounded by a transistor circuit region, according to another embodiment of the present invention.

[0020] Figures 2B-2C The following is illustrated according to an embodiment of the present invention: Figure 2A A schematic cross-sectional view of a semiconductor structure cut along lines B-B' and C-C'.

[0021] Figure 3 A flowchart illustrating a method for forming a semiconductor structure having a feedthrough via adjacent to a device-level metal contact according to an embodiment of the present invention is shown.

[0022] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B The following is an illustration of an embodiment of the present utility model. Figure 3 The intermediate manufacturing stage of the semiconductor structure formed by the method shown.

[0023] Figure 10 A flowchart illustrating a method for forming a semiconductor structure having a feedthrough via adjacent to a device-level metal contact, according to another embodiment of the present invention.

[0024] Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B The following is an illustration of an embodiment of the present utility model. Figure 10 The intermediate manufacturing stage of the semiconductor structure formed by the method shown.

[0025] The attached figures are labeled as follows:

[0026] 100: Semiconductor Structure

[0027] 106: Active Zone

[0028] 106a: Passage Area

[0029] 106b: Source / Drain (S / D) Region

[0030] 108: Metal gate structure

[0031] 111,113: Etching stop layer

[0032] 112: Source / Drain (S / D) junction

[0033] 114: Feedthrough via

[0034] 116: Front through hole

[0035] 116a: Source / Drain (S / D) via rail

[0036] 116b: Feedthrough via (FTV) type via rail

[0037] 117: Hard mask layer

[0038] 118: Backside Metal

[0039] 130: First interlayer dielectric (ILD) layer

[0040] 135: Feedthrough through-hole groove

[0041] 140: Second Interlayer Dielectric (ILD) Layer

[0042] 150: Dielectric structure

[0043] 160: Third Interlayer Dielectric (ILD) Layer

[0044] 200: Feedthrough circuit region

[0045] 300, 500: Method

[0046] 414, 416: Adhesive layer

[0047] 302, 304, 306, 308, 310, 312, 314, 316, 502, 504, 506, 508, 510, 512, 514, 516: Operation step 550: Truncate the metal gate (CMG) feature 550

[0048] a1, b1: Bottom width

[0049] a2, b2: Top width Detailed Implementation

[0050] The following disclosure provides many different embodiments or examples to implement different features of the present invention. The following disclosure provides specific examples of the various components and their arrangements to simplify the present invention. Of course, these are merely illustrative examples and are not intended to define the present invention. For example, if the following disclosure describes forming a first feature on or above a second feature, it indicates that it includes embodiments where the first and second feature are in direct contact, and also includes embodiments where additional feature components may be formed between the first and second feature components, so that the first and second feature components may not be in direct contact. Furthermore, reference numerals and / or text are repeated in various examples of the present invention. This repetition is for simplification and clarity, and not to specify the relationships between the various embodiments and / or configurations discussed.

[0051] Furthermore, spatial terms such as "below," "below," "under," "above," "upper," etc., are used here to readily express the relationship between the device or feature shown in the accompanying drawings and other devices or features. These spatial terms cover not only the orientation shown in the drawings but also different orientations of the device during use or operation. The device may have different orientations (rotated 90 degrees or other orientations), and the spatial symbols used herein also have corresponding explanations.

[0052] Furthermore, when a numerical value or range is described using terms such as "approximately" or "around," the term includes a value within a reasonable range that takes into account variations inherent during manufacturing, as understood by one of skill in the art. For example, based on known manufacturing tolerances for a feature part having a numerically related characteristic, the size or range of the value includes a reasonable range of said value, such as within + / - 10% of said value. For example, a material layer with a thickness of "approximately 5 nm" can cover a size range from 4.25 nm to 5.75 nm, where a manufacturing tolerance associated with the deposited material layer is known to one of skill in the art to be + / - 10%. And when comparing the size or dimensions of one feature part with another feature part, terms such as "substantially identical," "basically the same," or "similar size" can be understood as within + / - 10% of the compared feature parts. Furthermore, the disclosed dimensions of different feature parts may implicitly disclose size ratios between different features.

[0053] This invention relates to a semiconductor structure having a feedthrough circuit region surrounded by a transistor circuit region. The feedthrough circuit region includes feedthrough vias that continuously and uniformly extend from via rails on the front side of the wafer to back metal on the back side of the wafer. The feedthrough vias may be laterally adjacent to and surrounded by source / drain contacts located above source / drain features within the transistor circuit region. The feedthrough vias penetrate deeper than the source / drain contacts to contact the back metal on the back side of the wafer. The feedthrough vias provide direct connection from the front via rails to the back metal, without any other intermediate metal contacts or vias between the front via rails and the back metal. Therefore, the resistance of the feedthrough metal connection is reduced by eliminating any adhesive layer interface between the metal features. The feedthrough vias are formed from the back side of the wafer and may partially penetrate the back surface of the front via rails to break through the adhesive layer of the front via rails, thereby further reducing the feedthrough resistance. Because feedthrough vias are not limited by the patterned dimensions of nearby source / drain contacts, they can be formed wider than the source / drain contacts, thereby further reducing feedthrough resistance. Since feedthrough vias are formed from the back side, their upper surface can be narrower than their lower surface. For landing and stacking, feedthrough vias can be formed as part of a self-aligning process.

[0054] Figure 1A A top view schematic of a semiconductor structure 100 having a feedthrough circuit region 200 surrounded by a transistor circuit region is shown. The transistor circuit region includes an active region 106 extending longitudinally along the x-direction. The active region 106 includes a channel region (the region below the metal gate structure 108) and a source / drain (S / D) region adjacent to the channel region. The active region 106 may be a fin-type active region protruding from a substrate (not shown). Each channel region may include a stack of semiconductor channels for a gate-all-around semiconductor device. Alternatively, each channel region may include a single fin channel for a fin semiconductor device. The source / drain (S / D) region adjacent to the channel region includes epitaxial source / drain (S / D) features.

[0055] Please refer to Figure 1AThe semiconductor structure 100 (or its transistor circuit region) includes a metal gate structure 108 extending longitudinally along the y-direction and disposed above the channel region of the active region 106. For a gate-wound semiconductor device, each metal gate structure 108 surrounds a semiconductor channel stack in the channel region. For a finned semiconductor device, each metal gate structure 108 surrounds the top and sides of a finned channel projecting from the substrate. Each metal gate structure 108 may include a gate electrode above a gate dielectric layer disposed on the channel region of the active region 106. In some embodiments, an interface layer (e.g., a silicon oxide layer) is vertically disposed between the metal gate structure 108 and the gate dielectric layer. The gate dielectric layer includes a high-k dielectric material, such as a material with a dielectric constant greater than that of silicon oxide (k≈3.9). The gate dielectric layer may include HfO, LaO, ZrO, Al2O, TiO, or TaO. The gate electrode includes a suitable conductive material, such as Al, W, Co, TiAl, TiN, or other metal gate materials.

[0056] Please refer to Figure 1A The semiconductor structure 100 (or its transistor circuit region) includes a source / drain (S / D) contact 112 formed above an epitaxial source / drain (S / D) feature in the active region 106. As shown, the source / drain (S / D) contact 112 may be a trench source / drain (S / D) contact extending longitudinally along the y-direction. The source / drain (S / D) contact 112 is positioned on the source / drain (S / D) feature of the active region 106. In some embodiments, such as the one shown, a single source / drain (S / D) contact 112 may be positioned on multiple source / drain (S / D) features in multiple active regions 106. The source / drain (S / D) contact 112 is a device-level contact. In one embodiment, to promote better metal filling of the device-level contacts (avoiding air gaps and voids), the source / drain (S / D) contact 112 includes a metal material with good gap-filling properties (compared to copper), such as Al, W, Co, TiAl, TiN, or ruthenium.

[0057] Please refer to Figure 1A The semiconductor structure 100 includes a dielectric structure 150 disposed above and surrounding the active region 106 and the metal gate structure 108. The dielectric structure 150 includes one or more interlayer dielectric (ILD) layers and has an upper surface substantially coplanar with the upper surface of the source / drain (S / D) junction 112. The dielectric structure 150 extends and exists throughout the transistor circuit region and the feedthrough circuit region 200.

[0058] Please refer to Figure 1AThe semiconductor structure 100 includes a feedthrough circuit region 200. The feedthrough circuit region 200 includes a feedthrough via 114 that fully penetrates the dielectric structure 150 to form a metal interconnect between the front side and the back side of the semiconductor structure 100. Figure 1A In the illustrated embodiment, the feedthrough via 114 can be disposed between the active regions 106 along the y-direction and between the source / drain (S / D) contacts 112 along the x-direction. The feedthrough via 114 is a device-level interconnect and can include a metallic material similar to the source / drain (S / D) contacts 112 to obtain good gap-filling characteristics.

[0059] Please refer to Figure 1A The semiconductor structure 100 includes a front via 116 disposed on the upper surface of the dielectric structure 150. The front via 116 can be positioned onto an underlying metal feature, such as a source / drain (S / D) contact 112 or a feedthrough. As shown, the front via 116 may include a source / drain (S / D) via track 116a extending longitudinally in the x-direction to be positioned onto a plurality of source / drain (S / D) contacts 112. For example, the source / drain (S / D) contacts 112 may include extended source contacts that are longer (or shorter) than drain contacts in the y-direction. The source / drain (S / D) via track 116a is positioned onto the extension and connects the plurality of source (or drain) contacts together. The front via 116 may also include a feedthrough via (FTV) rail 116b located in the feedthrough circuit region 200. The feedthrough via (FTV) rail 116b extends longitudinally in the x and y directions above and around the feedthrough via 114. The feedthrough via (FTV) rail 116b is disposed on the upper surface of the feedthrough via 114.

[0060] The front via 116 is an interconnect connected to a first metal line of a metal interconnect structure (not shown) above the front via 116. The front via 116 can be considered a device-level interconnect and includes a metal material similar to the source / drain (S / D) contact 112 to achieve good gap-filling characteristics. The metal interconnect structure includes additional stacked metal lines vertically connected via additional interconnect vias for signal routing. Compared to device-level contacts, the metal features in the metal interconnect structure can have larger dimensions and bulk areas, allowing these metal features to use different metals or metal alloys or combinations thereof, such as poorer gap-filling metal materials, without sacrificing conductivity. For example, these upper metal features can include materials such as copper, aluminum, tin, silver, or alloys while still achieving good resistivity and cost savings. In other embodiments, these metal features still include a metal material similar to the source / drain (S / D) contact 112. Please note that the device-level features described herein may refer to the active region 106, the metal gate structure 108, the source / drain (S / D) contact 112, the feedthrough via 114, and the front via 116. The metal interconnect structure described herein may refer to an intermediate interconnect feature above the device-level features. Please note that in some embodiments, the front via 116 may be considered part of the metal interconnect structure. Therefore, the front via 116 may include a different metal material than the device-level metal features. For example, the source / drain (S / D) contact 112 and the feedthrough via 114 may include tungsten, and the front via 116 may include copper.

[0061] Please refer to Figure 1A The feedthrough circuit region 200 can longitudinally span multiple spaced intervals between the metal gate structures 108 along the x-direction. The feedthrough circuit region 200 can laterally span between the active regions 106 along the y-direction. In the illustrated embodiment, to reduce unwanted electrical coupling between the feedthrough circuit region 200 and the surrounding transistor circuit regions, the portion of the active region 106 surrounding the feedthrough circuit region 200 has a recessed width (e.g., half the width) in the y-direction.

[0062] Figures 1B-1D Show along Figure 1A A schematic cross-sectional view of the semiconductor structure 100 cut by the B-B', C-C', and D-D' lines. Although Figures 1B-1D Different feature components can be shown in different cross-sectional views, yet they all show the same vertical thickness portion of the semiconductor structure 100. Therefore, Figures 1B-1D The height of each layer in the structure is the same, and it can be accessed through... Figures 1B-1D Compare the heights of different feature components in semiconductor structure 100.

[0063] Figure 1B A cross-sectional view of the feedthrough circuit region 200 along the y-direction is shown. Figure 1B A feedthrough via 114 is shown penetrating the dielectric structure 150. In this invention, the dielectric structure 150 includes a first interlayer dielectric (ILD) layer 130, an etch stop layer 111 above the first interlayer dielectric (ILD) layer 130, and a second interlayer dielectric (ILD) layer 140 above the etch stop layer 111. As shown, the feedthrough via 114 completely penetrates the dielectric structure 150 (including the first interlayer dielectric (ILD) layer 130, the etch stop layer 111, and the second interlayer dielectric (ILD) layer 140). In the illustrated embodiment, the feedthrough via 114 also penetrates the back-side hard mask layer 117 below the lower surface of the first interlayer dielectric (ILD) layer 130. The lower surface of the feedthrough via 114 is positioned on the back-side metal 118. The back-side metal 118 may be part of a back-side metal interconnect structure (not shown) that includes additional stacked back-side metal lines vertically connected via additional interconnect vias for back-side signal routing. Metal features in the back-side metal interconnect structure may have a similar material to the metal features in the front-side metal interconnect structure above the aforementioned front-side via 116. The upper surface of the feedthrough via 114 directly contacts the front-side via 116, for example, a feedthrough via (FTV) type via rail 116b as shown. In the illustrated embodiment, the feedthrough via 114 partially penetrates the lower surface of the feedthrough via (FTV) type via rail 116b. In other embodiments, the feedthrough via 114 does not penetrate the feedthrough via (FTV) type via rail 116b and lands at a fixed point on the lowermost surface of the feedthrough via (FTV) type via rail 116b. The feedthrough via (FTV) type via rail 116b is embedded within a dielectric layer, such as the etch stop layer 113 and the third interlayer dielectric (ILD) layer 160 above the etch stop layer 113. The feedthrough via (FTV) type via rail 116b may extend wider than the feedthrough via 114 in the x and y directions to allow the feedthrough via 114 sufficient landing space.

[0064] For etchant selectivity, etch stop layers 111, 113, and hard mask layer 117 may include dielectric materials different from those of the first interlayer dielectric (ILD) layer 130, the second interlayer dielectric (ILD) layer 140, and the third interlayer dielectric (ILD) layer 160. For example, etch stop layers 111, 113, and hard mask layer 117 may include nitride-based dielectric materials, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or combinations thereof. The first inter-layer dielectric (ILD) layer 130, the second inter-layer dielectric (ILD) layer 140, and the third inter-layer dielectric (ILD) layer 160 comprise silicon oxide or oxide-based dielectric materials formed from tetraethyl orthosilicate, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof.

[0065] Please refer to Figure 1BThe feedthrough via 114 may include an adhesive layer 414 on its outer surface and a filler metal surrounded by the adhesive layer 414. Similarly, the feedthrough via (FTV) type via rail 116b may include an adhesive layer 416 on its outer surface and a filler metal surrounded by the adhesive layer 416. Adhesive layers 414 and 416 act as seed layers, providing better adhesion and surface contact. They also serve as conductive barrier layers to prevent unwanted diffusion or oxidation between the filler metal and surrounding features. However, adhesive layers 414 and 416 have a higher resistivity than the filler metal (e.g., between 2 and 100 times the resistivity). Therefore, this invention contemplates forming the feedthrough via 114 such that it penetrates the adhesive layer 416 surrounding a portion of the filler metal of the feedthrough via (FTV) type via rail 116b. As shown in the figure, the feedthrough via 114 completely penetrates the bottom of the adhesive layer 416 and can partially penetrate a portion of the filler metal of the feedthrough via (FTV) type via rail 116b. This reduces the overall interconnect resistance by penetrating the horizontal adhesive layer interface between the feedthrough via 114 and the feedthrough via (FTV) type via rail 116b. Adhesive layers 414 and 416 may include titanium, titanium nitride, titanium tungsten, titanium aluminide, titanium carbonitride, titanium aluminum nitride, or combinations thereof. The filler metal may include Al, W, Co, Ru, or combinations thereof. In one embodiment, adhesive layers 414 and 416 include titanium nitride, and the filler metal for both the feedthrough via 114 and the feedthrough via (FTV) type via rail 116b is tungsten. In another embodiment, the filler metals used for the feedthrough via 114 and the feedthrough via (FTV) type via rail 116b are different (for example, tungsten is used for the filler metal of the feedthrough via 114, while copper is used for the feedthrough via (FTV) type via rail 116b).

[0066] Please refer to Figure 1BThe feedthrough via 114 continuously and uniformly spans between the back metal 118 and the feedthrough via (FTV) type via rail 116b. The feedthrough via 114 provides direct connection from the front via rail 116b to the back metal 118, and there are no other intermediate metal contacts or vias between the front via rail 116b and the back metal 118. The feedthrough via (FTV) type via rail 116b lands directly on and contacts the upper surface of the feedthrough via 114. The feedthrough via 114 lands directly on and contacts the upper surface of the back metal 118. As described in more detail below, a feedthrough via (FTV) rail 116b is formed from the front side of the semiconductor structure 100, and then a feedthrough via 114 is formed from the back side of the semiconductor structure 100, landing precisely on (or partially passing through) the lower surface of the FTV rail 116b. Because the FTV rail 116b is formed from the front side, it has a narrowing profile from its upper surface to its lower surface. In other words, along the y-direction, the FTV rail 116b has an upper surface that is wider than its lower surface. Since the feedthrough via 114 is formed from the back side, it has a profile that narrows from its lower surface to its upper surface. In other words, along the y-direction, the feedthrough via 114 has a lower surface that is wider than its upper surface. Therefore, the feedthrough via 114 and the narrower portion of the feedthrough via (FTV) type via track 116b are connected to each other. To mitigate the problem of stack-up errors, the feedthrough via 114 can be used as part of a self-alignment process using cut-metal-gate features, as discussed in [the relevant section]. Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B Explanation.

[0067] Figure 1CA schematic cross-sectional view of a semiconductor structure 100 cut along the active region 106 in the x-direction is shown. The active region 106 includes a channel region 106a located between source / drain (S / D) regions 106b. The source / drain (S / D) regions 106b include epitaxial features, doped with n-type or p-type dopants for n-type or p-type transistors, respectively. A metal gate structure 108 is disposed above the channel region 106a. The metal gate structure 108 may surround a channel layer located in the channel region 106a of a GAA device (not shown). A dielectric structure 150 having a first interlayer dielectric (ILD) layer 130, an etch stop layer 111, and a second interlayer dielectric (ILD) layer 140 is disposed above the active region 106. A source / drain (S / D) contact 112 penetrates the second interlayer dielectric (ILD) layer 140, the etch stop layer 111, and the first interlayer dielectric (ILD) layer 130 and is fixedly landed on the source / drain (S / D) region 106b. The etch stop layer 111 can be fixedly landed on the upper surface of the metal gate structure 108, and the metal gate contact 110 can penetrate the second interlayer dielectric (ILD) layer 140 and the etch stop layer 111 to be fixedly landed on the metal gate structure 108. As shown in the figure, the upper surfaces of the source / drain (S / D) contact 112, the dielectric structure 150, and the metal gate contact 110 are substantially coplanar, and the lower surface of the source / drain (S / D) contact 112 is located below the lower surface of the metal gate contact 110. Although not shown, the gate via can penetrate the third interlayer dielectric (ILD) layer 160 and the etch stop layer 113 to land precisely on the metal gate contact 110. In another embodiment, there is no metal gate contact 110, and the gate via can directly penetrate the third interlayer dielectric (ILD) layer 160, the etch stop layer 113, and the second interlayer dielectric (ILD) layer 140 to land precisely on the metal gate structure 108. In this invention, the upper surface of the gate via is located above the upper surface of the source / drain (S / D) contact 112.

[0068] Please refer to now. Figure 1D The front via 116, such as the source / drain (S / D) via 116a, can penetrate the third interlayer dielectric (ILD) layer 160 and the etch stop layer 113 to land precisely on the extension of the source / drain (S / D) junction. Figure 1DA cross-sectional view of a semiconductor structure 100 cut along the source / drain (S / D) via 116a in the x-direction is shown. As shown, the extension of the source / drain (S / D) junction 112 has side and bottom surfaces that directly contact and are surrounded by the dielectric structure 150. Also as shown, in this view, the metal gate structure 108 may extend vertically deeper within the first interlayer dielectric (ILD) layer 130, for example, extending into a shallow trench isolation structure (not shown) (which is part of or below the first interlayer dielectric (ILD) layer 130), or, as shown, directly onto the hard mask layer 117.

[0069] Now, please refer to the following: Figures 1B-1D The lower surfaces of the source / drain (S / D) via 116a and the feedthrough via (FTV) via 116b are substantially coplanar. The source / drain (S / D) contact 112 partially penetrates the dielectric structure 150 (i.e., completely penetrates the second interlayer dielectric (ILD) layer 140, the etch stop layer 111, and partially penetrates the first interlayer dielectric (ILD) layer 130) to land on the source / drain (S / D) region 106b. The feedthrough via 114 completely penetrates the dielectric structure 150 to land on the back metal 118. Since the feedthrough via 114 partially penetrates the feedthrough via (FTV) via 116b, the upper surface of the feedthrough via 114 can be located above the upper surface of the source / drain (S / D) contact 112.

[0070] Figure 2A This diagram shows a top view of a semiconductor structure 100 having a feedthrough circuit region 200 surrounded by a transistor circuit region, according to another embodiment of the present invention. Figure 2A Similar to Figure 1A For the sake of brevity, similar feature components will not be described again. The difference lies in that the feedthrough circuit region 200, with feedthrough via 114 and feedthrough via (FTV) type via rail 116b, has a smaller dimension along the x-direction between the two source / drain (S / D) contacts 112, and the portion of the active region 106 enclosing the feedthrough circuit region 200 has no recess width in the y-direction. In other words, the feedthrough circuit region 200 is more compact and integrates more seamlessly with the surrounding transistor region. As shown, the feedthrough circuit region 200 only replaces a portion of the transistor circuit region, which would otherwise have the source / drain (S / D) contacts 112.

[0071] Figures 2B-2C The following is illustrated according to an embodiment of the present invention: Figure 2AA schematic cross-sectional view of the semiconductor structure 100 cut along lines B-B' and C-C'. Although lines B-B' and C-C' are cut along different portions of the semiconductor structure 100, they have the same length along the x-direction to facilitate... Figure 2B and Figure 2C Compare them side by side. Figure 2B Figure 1B ,but Figure 2B Extending further in the x-direction, it shows an additional source / drain (S / D) contact 112 above another source / drain (S / D) region 106b. Figure 2C Similar to Figure 2B However, there is no source / drain (S / D) contact 112 between the two other source / drain (S / D) contacts 112, and the feedthrough via 114 is located between the two other source / drain (S / D) contacts 112 (or particularly between the extensions of the two other source / drain (S / D) contacts 112 that are not fixedly landed on the source / drain (S / D) region 106b). In this cross-sectional schematic diagram, the feedthrough via 114 and the feedthrough via (FTV) type via rail 116b include adhesive layers 414 and 416, and show a connection with... Figure 1B Similar configurations shown in the cross-section (e.g., feedthrough via 114 penetrating dielectric structure 150 to connect feedthrough via (FTV) type via rail 116b and back metal 118). Although not shown, feedthrough via 114 may also pierce a portion of the metal gate structure 108 spanning the feedthrough circuit region 200.

[0072] Please refer to Figure 2CThe source / drain (S / D) contact 112 has a wider top width a2, which narrows to a narrower bottom width a1. The feedthrough via 114 has a narrower top width b2, which widens downwards to a wider bottom width b1. In this invention, since the feedthrough via 114 is not limited by the patterning constraints of the source / drain (S / D) contact 112, the feedthrough via 114 can be formed wider along the x-direction between the source / drain (S / D) contacts 112. In this invention, the top width b2 of the feedthrough via 114 is wider than the bottom width a1 of the source / drain (S / D) contact 112. This improves the surface contact of the feedthrough via 114 and reduces resistance, maximizing its surface interface with the feedthrough via (FTV) type via rail 116b. In one embodiment, the ratio of the top width b2 to the bottom width a1 is at least 1.25 to achieve improved resistance and prevent top-to-bottom alignment errors. In one embodiment, the ratio of the bottom width b1 to the top width b2 is greater than 1.1. In one embodiment, the bottom width a1 is in the range of approximately 3 nm to 50 nm, and the top width b2 is approximately 20 nm to 60 nm greater than the bottom width a1. In one embodiment, the bottom width b1 is in the range of approximately 25 nm to 120 nm, and the bottom width b1 is approximately 15 nm to 25 nm greater than the top width b2.

[0073] Figure 3 A flowchart of a method 300 for forming a semiconductor structure 100 having a feedthrough via 114 adjacent to a device-level metal contact (e.g., source / drain (S / D) contact 112) according to an embodiment of the present invention is shown. Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B Showing the following Figure 3 The intermediate manufacturing stage of the semiconductor structure 100 formed by the method 300 shown is described below. (Refer to the following...) Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B The description of method 300 illustrates intermediate manufacturing stages for forming the semiconductor structure 100 as shown in Figures 1B-1D and / or 2B-2C. The description of the intermediate manufacturing stages is in contrast to... Figure 2AA cross-sectional schematic diagram of line C-C' in the diagram. Additional operational steps may be provided before, during, and after method 300, and for additional embodiments of method 300, some operations in these operations may be moved, replaced, or removed. It should be noted that reference has been made to... Figures 1A-1D and Figures 2A-2C The aforementioned feature components can also be used to describe Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B Similar marked feature components.

[0074] At operation step 302 of method 300, a semiconductor working component having an active region 106 extending longitudinally along a first direction is received. Each active region 106 includes a channel region 106a between source / drain (S / D) feature components in a source / drain (S / D) region 106b and a gate (e.g., a metal gate structure 108) located above the channel region 106a (see reference). Figure 1C The active region 106 may be formed over a substrate (not shown). The substrate may include silicon (Si) or other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), or diamond. The active region 106 may be surrounded by an isolation structure, such as a shallow trench isolation (STI) structure (not explicitly shown, but may be below or beneath the first interlayer dielectric (ILD) layer 130). The isolation structure may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, combinations thereof, and / or other suitable materials.

[0075] Please refer to now. Figure 4 In step 304 of method 300, a dielectric structure 150 is formed above and around the active region 106 (see also step [number missing]). Figure 1C Operation step 304 may include forming a first interlayer dielectric (ILD) layer 130 over and around the active region 106, forming an etch stop layer 111 over the first interlayer dielectric (ILD) layer 130, and forming a second interlayer dielectric (ILD) layer 140 over the etch stop layer 111. The dielectric structure 150 may be formed by any suitable deposition process, such as chemical vapor deposition. The etch stop layer 111 may be formed above the upper surface of the gate (e.g., metal gate structure 108).

[0076] Please refer to Figure 4In operation step 306 of method 300, a source / drain (S / D) junction 112 of the through-dielectric structure 150 is formed. For example... Figure 4 As shown, the source / drain (S / D) contact 112 penetrates the second interlayer dielectric (ILD) layer 140 and the etch stop layer 111, and partially penetrates the first interlayer dielectric (ILD) layer 130. The source / drain (S / D) contact 112 partially penetrates the interlayer dielectric (ILD) layer 130 to precisely land on the source / drain (S / D) feature components (such as...) in the source / drain (S / D) region 106b. Figure 1C (As shown). The remaining portion of the source / drain (S / D) junction 112 is fixedly dropped onto the unpenetrated portion of the first interlayer dielectric (ILD) layer 130 (as shown). Figure 4 (As shown). The source / drain (S / D) contact 112 can be formed by a patterning process to form a source / drain (S / D) trench exposing the source / drain (S / D) region 106b, and fill the trench with metal features (e.g., resist and metal filler). The patterning process may include depositing photoresist and / or a hard mask over the dielectric structure 150, patterning the photoresist and / or hard mask by a photolithography process to define the portion of the dielectric structure 150 to be etched, and etching the dielectric structure 150 using an etching process. The patterned photoresist and / or hard mask is used as an etching mask to form the source / drain (S / D) trench. After the patterning process, the source / drain (S / D) trench is formed, and metal features are deposited within the source / drain (S / D) trench to form the source / drain (S / D) contact 112. Subsequently, a CMP process can be performed to planarize the upper surface of the source / drain (S / D) junction 112 and the dielectric structure 150. The resulting structure is as follows. Figure 4 As shown.

[0077] Please refer to now. Figure 5 Method 300 performs operation steps 308 and 310. In operation step 308, the method forms a first via (e.g., source / drain (S / D) via rail 116a) that is positioned above one of the source / drain (S / D) contacts 112 (see reference). Figure 1DIn step 310 of method 300, a second via (e.g., a feedthrough via (FTV) type via rail 116b) is formed, positioned above the dielectric structure 150 and isolated from the source / drain (S / D) junction 112. The first and second vias are separated from each other by an etch stop layer 113. Although this invention describes forming the first and second vias (e.g., the source / drain (S / D) via rail 116a and the feedthrough via (FTV) type via rail 116b) in two steps, they can also be formed in the same step. Operation steps 308 and 310 may include depositing an etch stop layer 113, depositing a third interlayer dielectric (ILD) layer 160 on the source / drain (S / D) junction 112 and the upper surface of the second interlayer dielectric (ILD) layer 140 above the etch stop layer 113, depositing the third interlayer dielectric (ILD) layer 160 on the etch stop layer 113, performing a patterning process to form corresponding first and second via trenches in the third interlayer dielectric (ILD) layer 160 and the etch stop layer 113, and filling the via trenches with metal feature components (e.g., adhesive layer and metal filler) to form corresponding first and second vias (e.g., source / drain (S / D) via rails 116a and feedthrough via (FTV) type via rails 116b) in the first and second via trenches. Subsequently, a CMP process can be performed to planarize the upper surfaces of the third interlayer dielectric (ILD) layer 160 and the first and second vias (e.g., source / drain (S / D) via rails 116a and feedthrough (FTV) via rails 116b). It should be noted that the first and second vias (e.g., source / drain (S / D) via rails 116a and feedthrough (FTV) via rails 116b) are located within the same material layer (substantially coplanar upper and lower surfaces) above the dielectric structure 150.

[0078] Please refer to now. Figures 6-7 In operation step 312 of method 300, etching is performed from the back side through the dielectric structure 150 to form a feedthrough trench 135 exposing the lower surface of the second via (e.g., a feedthrough via (FTV) type via rail 116b). Operation step 312 can be performed after forming a front-side metal interconnect structure (not shown) above the dielectric structure 150. In one embodiment, the first and second vias can be part of the front-side metal interconnect structure, wherein additional metal features (e.g., metal lines and interconnect vias located between the metal lines) are formed above the first and second vias. After forming the front-side metal interconnect structure, a carrier wafer can be attached to the working component located on the front side. The carrier wafer provides structural support for preparation of back-side processing. Please refer to... Figure 6At step 312 of method 300, the substrate on which the active region 106 is formed is first thinned. The substrate is thinned from the back side of the working component and may be partially or completely removed. It should be noted that the thinning process can be performed before or after the semiconductor structure 100 is flipped in the z-direction for further back-side processing. In the illustrated embodiment, the substrate is completely removed to expose the lower surface of the first interlayer dielectric (ILD) layer 130. The thinning process may etch away the bottom portion of the isolation structure (e.g., shallow trench isolation (STI)) surrounding the active region 106. Then refer to... Figure 7 Operation step 312 may include depositing a hard mask layer 117 above the exposed lower surface of the first interlayer dielectric (ILD) layer 130. Now refer to Figure 7 In step 312 of method 300, a feedthrough via trench 135 is formed by a patterning process. The patterning process may include depositing photoresist and / or a hard mask (note that the working part can be flipped) on the lower surface of the hard mask layer 117, patterning the photoresist and / or hard mask (note that the working part can be flipped) by photolithography, patterning the photoresist and / or hard mask by photolithography to define the opening of the hard mask layer 117 to be etched, and using the patterned photoresist and / or hard mask as an etching mask and etching through the opening to form the feedthrough via trench 135. Etching through the opening includes completely etching through the hard mask layer 117, the first interlayer dielectric (ILD) layer 130, the etch stop layer 111, and the second interlayer dielectric (ILD) layer 140 to expose the feedthrough via (FTV) type via track 116b. In the illustrated embodiment, there is over-etching that penetrates the bottom portion of the adhesive layer 416. It should be noted that because the feedthrough via (FTV) type via rail 116b is formed from the back side, the profile of the feedthrough via (FTV) type via rail 116b narrows towards the top.

[0079] Please refer to now. Figure 8A , Figure 8B , Figure 9A , Figure 9B In step 314 of method 300, a feedthrough hole 114 is formed within the feedthrough hole groove 135. Please refer to [the relevant documentation / reference]. Figure 8A Operation step 314 includes the compliant deposition of an adhesive layer 414 within the feedthrough trench 135 and above the lower surface of the hard mask layer 117. For example... Figure 8A As shown, the upper horizontal portion of the adhesive layer 414 is in direct contact with the lower horizontal portion of the feedthrough (FTV) type via rail 116b. In another embodiment, as... Figure 8BAs shown, the upper horizontal portion is then removed to reduce the resistivity caused by the adhesive layer interface. It should be noted that previously, by forming the feedthrough trench 135 to penetrate the adhesive layer 416, the resistivity was already reduced by removing one layer of the adhesive layer interface; now, by removing the upper horizontal portion of the adhesive layer 414, the resistivity is further reduced by removing a second layer of the adhesive layer interface. The upper horizontal portion of the adhesive layer 414 can be removed by selective plasma etching. Now please refer to... Figures 9A-9B A metal filler layer for the via is deposited within the via trench 135 and above the adhesive layer 414. In the first embodiment, as... Figure 9A As shown, adhesive layer 414 is disposed on the side surface and upper surface of the via metal filling layer, and the via metal filling layer is separated from the feedthrough (FTV) type via rail 116b (or its metal filling portion) by the upper horizontal portion of adhesive layer 416. In the second embodiment, as... Figure 9B As shown, the adhesive layer 414 is disposed on the side surface of the via metal filler layer, but not on the upper surface of the via metal filler layer, and the upper surface of the via metal filler layer directly contacts the feedthrough (FTV) type via rail 116b (or its metal filler portion). Please refer to... Figure 9A and Figure 9B At step 316 of method 300, back metal 118 is then formed on the lower surface of feedthrough via 114 by any suitable deposition process.

[0080] Figure 10 A flowchart of a method 500 for forming a semiconductor structure 100 having a feedthrough via 114 adjacent to a device-level metal contact (e.g., source / drain (S / D) contact 112) according to another embodiment of the present invention is shown. Method 500 is similar to method 300, and for simplicity, similar features will not be described again. The difference is that method 500 incorporates a cut-off metal gate (CMG) feature 550. The cut-off metal gate (CMG) feature 550 establishes a safe area for etching the feedthrough via trench 135, thereby achieving self-alignment and reducing top-to-bottom stacking errors when forming the feedthrough via 114 on the back side of the feedthrough via (FTV) type via track 116b. Please refer to the following... Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B Method 500 is illustrated, showing an intermediate manufacturing stage for forming a semiconductor structure 100 similar to that shown in Figures 1B-1D and / or 2B-2C, but now incorporating a cut-off metal gate (CMG) feature 550. Reference is made below to... Figure 2AA cross-sectional view along the C-C' line is used to illustrate the intermediate manufacturing stage. Additional operational steps may be provided before, during, and after method 500, and in additional embodiments of method 500, some of these operations may be moved, replaced, or removed. It should be noted that reference has been made to... Figures 1A-1D and Figures 2A-2C The aforementioned feature components can also be used to describe Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B Similar marked feature components.

[0081] At operation step 502 of method 500, a working component having an active region 106 extending longitudinally along a first direction is received. Each active region 106 includes a channel region 106a located between source / drain (S / D) feature components in a source / drain (S / D) region 106b and a gate (e.g., a metal gate structure 108) located above the channel region 106a (see reference). Figure 1C Operation step 502 is similar to operation step 302, and will not be repeated for the sake of brevity.

[0082] Please refer to now. Figure 11 At operation step 504 of method 500, a dielectric structure 150 is formed above and around the active region 106. The dielectric structure 150 includes a first interlayer dielectric (ILD) layer 130 surrounding a cut-metal-gate (CMG) feature 550, an etch stop layer 111 located above the first interlayer dielectric (ILD) layer 130 and the cut-metal-gate (CMG) feature 550, and a second interlayer dielectric (ILD) layer 140 located above the etch stop layer 111. Operation step 504 may include forming a first interlayer dielectric (ILD) layer 130 over and around the active region 106, forming a cut-off metal gate (CMG) feature 550 within the first interlayer dielectric (ILD) layer 130, forming an etch stop layer 111 over the first interlayer dielectric (ILD) layer 130 and the cut-off metal gate (CMG) feature 550, and forming a second interlayer dielectric (ILD) layer 140 over the etch stop layer 111. The cut-off metal gate (CMG) feature 550 is formed by first forming a cut-off metal gate (CMG) trench within the first interlayer dielectric (ILD) layer 130 using a patterning process. Forming the cut-off metal gate (CMG) trench may etch away one or more portions of the metal gate structure 108 extending into the feedthrough circuit region 200 (see reference). Figure 1A and Figure 2A The patterning process may include depositing photoresist and / or a hard mask (not shown) on the upper surface of the first interlayer dielectric (ILD) layer 130, patterning the photoresist and / or hard mask using photolithography to define openings in the hard mask layer 117 to be etched, and using the patterned photoresist and / or hard mask as an etching mask to etch through the openings to form cut-off metal gate (CMG) trenches. Etching through the openings may include completely etching through the extensions of the first interlayer dielectric (ILD) layer 130 and the metal gate structure 108. Next, a dielectric material is deposited within the cut-off metal gate (CMG) trenches to form a cut-off metal gate (CMG) feature 550. The cut-off metal gate (CMG) feature 550 includes a dielectric material different from that of the first interlayer dielectric (ILD) layer 130 to achieve etchant selectivity and a self-aligned process for subsequent formation of the feedthrough via 114. For example, the first interlayer dielectric (ILD) layer 130 comprises an oxide-based dielectric material (e.g., silicon oxide), while the cut-off metal gate (CMG) feature 550 comprises a nitride-based dielectric material (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxynitride, or combinations thereof). After forming the cut-off metal gate (CMG) feature 550, a CMP process can be performed to planarize the upper surfaces of the first interlayer dielectric (ILD) layer 130 and the cut-off metal gate (CMG) feature 550. Subsequently, an etch stop layer 111 and a second interlayer dielectric (ILD) layer 140 are deposited to complete the fabrication of the dielectric structure 150.

[0083] Please refer to Figure 12 In operation step 506 of method 500, a source / drain (S / D) contact 112 is formed through the dielectric structure 150. The source / drain (S / D) contact 112 completely penetrates the second interlayer dielectric (ILD) layer 140 and the etch stop layer 111, and partially passes through the interlayer dielectric (ILD) layer 130, landing precisely on the source / drain (S / D) feature components (such as...) in the source / drain (S / D) region 106b. Figure 1C (As shown). The remaining portion of the source / drain (S / D) junction 112 is fixedly dropped onto the unpenetrated portion of the first interlayer dielectric (ILD) layer 130 (as shown). Figure 12 As shown, a source / drain (S / D) junction 112 is formed such that its upper surface is located above the upper surface of the cut-off metal gate (CMG) feature 550. Operation step 506 is similar to operation step 306, and for the sake of brevity, similar features will not be described again.

[0084] Please refer to now. Figure 13In step 508 of method 500, a first via (e.g., source / drain (S / D) via rail 116a) is formed and grounded at one of the source / drain (S / D) contacts 11 (see reference). Figure 1D In operation step 510 of method 500, a second via (e.g., a feedthrough via (FTV) type via rail 116b) is formed, which is fixedly dropped onto the dielectric structure 150 and isolated from the source / drain (S / D) junction 112. Operation steps 508 and 510 are similar to operation steps 308 and 310, and for the sake of brevity, similar features will not be described again.

[0085] Please refer to now. Figures 14-15 In operation step 512 of method 500, the dielectric structure 150 is etched through from the back side by etching through the cut-off metal gate (CMG) feature 550, the etch stop layer 111, and the second interlayer dielectric (ILD) layer 140 to form a feedthrough via trench 135 exposing the lower surface of the second via (e.g., a feedthrough via (FTV) type via rail 116b). Operation step 512 is similar to operation step 312, and for the sake of brevity, similar features will not be described again. However, the presence of the cut-off metal gate (CMG) feature 550 improves the process of forming the feedthrough via trench 135. The cut-off metal gate (CMG) feature 550 provides etch selectivity to form a safe region, allowing the etching process to etch through the cut-off metal gate (CMG) feature 550 without the risk of etching other unintended areas. Once the cut-off metal gate (CMG) feature 550 is etched through, the remaining etch stop layer 111 and the second interlayer dielectric (ILD) layer 140 self-align to expose the feedthrough via (FTV) via track 116b. If a top-to-bottom stack-up misalignment occurs, different compositions and etch selectivity will limit etching within the CMG feature 550. This reduces the risk of top-to-bottom stack-up errors despite the narrowed top profile of the feedthrough via trench 135.

[0086] Please refer to now. Figure 16A , Figure 16B In operation step 514 of method 500, a feedthrough via 114 is formed within the feedthrough via trench 135. Operation step 514 is similar to operation step 314, and for the sake of brevity, similar features will not be described again. It should be noted that the feedthrough via 114 can be separated from the first interlayer dielectric (ILD) layer 130 by cutting off the remaining unetched portion of the metal gate (CMG) feature 550. Now please refer to Figure 17A , Figure 17BAt step 516 of method 500, back metal 118 is then formed on the lower surface of feedthrough via 114 by any suitable deposition process.

[0087] While not limited to this, the present invention provides advantages of semiconductor structures with feedthrough vias. One example of this advantage is that the feedthrough via completely penetrates the dielectric structure to connect the front via and the back metal. This reduces feedthrough resistance due to fewer adhesive layer interfaces. Another example of this advantage is that over-etching is performed during feedthrough via formation to remove the adhesive layer interfaces. Yet another example of this advantage is that plasma etching is performed during feedthrough via formation to remove additional adhesive layer interfaces. A further example of this advantage is the incorporation of cut-off metal gate dielectric features for self-alignment between the feedthrough via and the feedthrough via rails.

[0088] One embodiment of this utility model provides a semiconductor structure. The semiconductor structure includes: a first circuit region having: an active region extending longitudinally along a first direction, the active region including a channel region located between a plurality of source / drain (S / D) features and a gate located above the channel region; a dielectric structure located above and surrounding the active region; a metal contact passing through an upper surface of the dielectric structure and positioned above one of the source / drain (S / D) features; and a first via positioned on the metal contact. The semiconductor structure includes a second circuit region having: the aforementioned dielectric structure; a feedthrough via penetrating the upper surface and a lower surface of the dielectric structure; and a second via located on the feedthrough via. The first and second vias have substantially coplanar lower surfaces.

[0089] In one embodiment, the feedthrough via partially penetrates the lower surface of the second via. In a further embodiment, the second via includes an adhesive layer and a via filling layer, the adhesive layer being disposed on the side and lower surfaces of the via filling layer, and the feedthrough via completely penetrating the bottom portion of the adhesive layer disposed directly above the via filling layer.

[0090] In one embodiment, the feedthrough via extends continuously and uniformly from the lower surface of the dielectric structure across at least the upper surface of the dielectric structure.

[0091] In one embodiment, the feedthrough via includes an adhesive layer and a via filling layer. The adhesive layer is disposed on the side surface and the top surface of the via filling layer, and the via filling layer is separated from the second via through the adhesive layer.

[0092] In one embodiment, the feedthrough via includes an adhesive layer and a via filling layer. The adhesive layer is disposed on the side surface of the via filling layer but not on the upper surface of the via filling layer, and the via filling layer directly contacts the second via.

[0093] In one embodiment, the lower and side surfaces of the metal contact are embedded in the dielectric structure, and the lower surface of the metal contact is located below the upper surface of the feedthrough via.

[0094] In one embodiment, a lower etch stop layer is embedded in the dielectric structure. The lower etch stop layer is positioned on an upper surface of the gate. The metal contacts and feedthrough vias both penetrate the lower etch stop layer. In a further embodiment, the semiconductor structure further includes an upper etch stop layer, wherein a first via and a second via penetrate the upper etch stop layer to be positioned on the metal contacts and feedthrough vias, respectively.

[0095] In one embodiment, along a first direction, the top width of a feedthrough via is greater than the bottom width of a metal contact.

[0096] Another aspect of this utility model provides a semiconductor structure. The semiconductor structure includes: a first circuit region having: an active region extending longitudinally along a first direction, the active region including a channel region located between a plurality of source / drain (S / D) features and a gate located above the channel region; a dielectric structure located above and surrounding the active region; a metal contact having a first portion extending into the dielectric structure by a first distance to be precisely landed on one of the source / drain (S / D) features; and a first via landing precisely on the metal contact. The semiconductor structure further includes: a second circuit region having: a second portion of the metal contact having a lower surface and side surface directly contacting the dielectric structure; a feedthrough via adjacent to the second portion of the metal contact and extending into the dielectric structure by a second distance; and a second via landing precisely on the feedthrough via. The second distance is greater than the first distance.

[0097] In one embodiment, the semiconductor structure further includes a back-side metal located below a lower surface of the dielectric structure, and a feedthrough via is positioned on an upper surface of the back-side metal.

[0098] In one embodiment, the first circuit region further includes: a second channel region of the active region located between a plurality of second source / drain (S / D) features and a second gate located above the second channel region; and a second metal contact having a first portion extending into the dielectric structure by a first distance to be positioned on one of the second source / drain (S / D) features. The second circuit region further includes a second portion of the second metal contact positioned on another horizontal surface of the dielectric structure, and a feedthrough via laterally disposed between the first metal contact and the second metal contact along a first direction.

[0099] In one embodiment, the feedthrough via has a top width along a first direction and a bottom width along the first direction, with the bottom width being greater than the top width. In another embodiment, the metal contact has a bottom width, and the top width of the feedthrough via is greater than the bottom width of the metal contact.

[0100] In one embodiment, a lower etch stop layer is embedded in the dielectric structure. The lower etch stop layer is positioned on the upper surface of the gate, and the metal contacts and feedthrough vias penetrate the lower etch stop layer.

[0101] In one embodiment, the dielectric structure includes an interlayer dielectric (ILD) layer surrounding a cut-off metal gate (CMG) feature, wherein the cut-off metal gate (CMG) feature separates a feedthrough via from the interlayer dielectric (ILD) layer, the feedthrough via penetrates the cut-off metal gate (CMG) feature, and the interlayer dielectric (ILD) layer and the cut-off metal gate (CMG) feature comprise different dielectric materials.

[0102] Another aspect of this utility model provides a method for forming a semiconductor structure. The method includes: receiving a working component having a plurality of active regions extending longitudinally along a first direction, each active region including a channel region located between a plurality of source / drain (S / D) feature components and a gate located above the channel region; forming a dielectric structure above and surrounding each active region; forming a plurality of metal contacts penetrating the dielectric structure to be fixedly landed on the source / drain (S / D) feature components; forming a first via fixedly landed on one of the metal contacts; forming a second via fixedly landed on the dielectric structure and spaced apart from the metal contacts; etching through the dielectric structure from a back side to form a feedthrough via trench, exposing a lower surface of the second via; and forming a feedthrough via within the feedthrough via trench.

[0103] In one embodiment, the dielectric structure includes a first interlayer dielectric (ILD) layer, and the method further includes: forming a cut-off metal gate (CMG) feature within the first interlayer dielectric (ILD) layer before forming a metal contact, replacing one or more gates located between two of the source / drain (S / D) features along a first direction. Etching through the first interlayer dielectric (ILD) layer includes etching through the cut-off metal gate (CMG) feature to form a feedthrough via trench.

[0104] The foregoing provides a brief overview of the characteristic components of several embodiments of this utility model, enabling those skilled in the art to more readily understand the nature of this utility model. Anyone skilled in the art should understand that this utility model can be readily used as a basis for modifications or designs to other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. It will also be understood by anyone skilled in the art that equivalent structures described above do not depart from the spirit and scope of this utility model, and that modifications, substitutions, and refinements can be made without departing from its spirit and scope.

Claims

1. A semiconductor structure, characterized by, comprising: a first circuit region having: an active region extending longitudinally along a first direction, the active region including a channel region between a plurality of source / drain features and a gate over the channel region; a dielectric structure over and around the active region; a metal contact through an upper surface of the dielectric structure to land over one of the source / drain features; and a first via landing on the metal contact; a second circuit region having: the dielectric structure; a feedthrough via through the upper surface of the dielectric structure and a lower surface of the dielectric structure; and a second via on the feedthrough via, wherein the first via and the second via have coplanar lower surfaces.

2. The semiconductor structure of claim 1, characterized in that wherein the feedthrough via includes a glue layer and a via fill layer, and wherein the glue layer is disposed on side surfaces and an upper surface of the via fill layer, and the via fill layer is separated from the second via by the glue layer.

3. The semiconductor structure of claim 1, characterized in that wherein the feedthrough via includes a glue layer and a via fill layer, and wherein the glue layer is disposed on side surfaces of the via fill layer but not on an upper surface of the via fill layer, and the via fill layer directly contacts the second via.

4. The semiconductor structure of any of claims 1-3, wherein the semiconductor structure is a semiconductor-on-insulator structure. wherein a lower surface and side surfaces of the metal contact are buried within the dielectric structure, and the lower surface of the metal contact is below an upper surface of the feedthrough via.

5. The semiconductor structure of any of claims 1-3, wherein the semiconductor structure is a semiconductor-on-insulator structure. wherein along the first direction, a top width of the feedthrough via is greater than a bottom width of the metal contact.

6. A semiconductor structure, characterized by comprising: a first circuit region having: an active region extending longitudinally along a first direction, the active region including a channel region between a plurality of source / drain features and a gate over the channel region; a dielectric structure over and around the active region; a first metal contact having a first portion penetrating into the dielectric structure by a first distance to land over one of the source / drain features; and a first via landing on the first metal contact; and a second circuit region having: a second portion of the first metal contact having a lower surface and side surfaces directly contacting the dielectric structure; a feedthrough via adjacent to the second portion of the first metal contact and penetrating into the dielectric structure by a second distance; and a second via landing on the feedthrough via, wherein the second distance is greater than the first distance. further comprising:

7. The semiconductor structure of claim 6, wherein, a backside metal under a lower surface of the dielectric structure, and the feedthrough via lands on an upper surface of the backside metal. wherein the first circuit region further comprises:

8. The semiconductor structure of claim 6 or 7, wherein the first and second semiconductor layers are formed of a same material. a second channel region of the active region between a plurality of second source / drain features and a second gate over the second channel region; and a second metal contact having a first portion penetrating into the dielectric structure by a first distance to land over one of the second source / drain features. ​ wherein the second circuit region further comprises a second portion of the second metal contact, the second portion of the second metal contact is positioned to land on another horizontal surface of the dielectric structure, and the feedthrough via is laterally disposed between the first metal contact and the second metal contact along the first direction.

9. The semiconductor structure of claim 6 or 7, wherein, wherein the dielectric structure is embedded in an underlying etch stop layer, wherein the underlying etch stop layer is positioned to land on an upper surface of the gate, and wherein the first metal contact and the feedthrough via both penetrate the underlying etch stop layer.

10. The semiconductor structure of claim 6 or 7, characterized in that wherein the dielectric structure comprises an interlayer dielectric layer surrounding a truncated metal gate feature, wherein the truncated metal gate feature separates the feedthrough via from the interlayer dielectric layer, and the feedthrough via penetrates the truncated metal gate feature, and wherein the interlayer dielectric layer and the truncated metal gate feature comprise different dielectric materials.

11. The semiconductor structure of claim 6 or 7, wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is positioned to land on an upper surface of the gate, and the second dielectric layer is positioned to land on a lower surface of the gate, and wherein the first dielectric layer and the second dielectric layer comprise different dielectric materials.

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