Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure comprises a substrate; and a multilayer metal pattern. The multi-layer metal pattern is disposed on the substrate, wherein a thickness of a first thick metal layer in the multi-layer metal pattern is twice or more than a thickness of a next-layer metal pattern. The first thick metal layer includes a first electrical transmission pattern having a first pattern distribution density; and a first dummy pattern. A first total distribution density of the first electrical transmission pattern and the first dummy pattern is higher than the first pattern distribution density by a first pattern distribution density of less than / equal to 125%.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit parts and components. Tens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. Individual chips are divided by sawing along scribe lines. With advancements in semiconductor technology, stacked semiconductor components (such as 3D integrated circuit (3DIC) packaging) have become an effective alternative for further reducing the physical size of semiconductor devices.

[0003] In stacked semiconductor components, active circuits such as logic, memory, and processor circuits are fabricated on different semiconductor wafers and integrated into a single (3DIC) package using appropriate bonding technologies. The high degree of integration through advanced packaging technologies allows for the production of semiconductor components with enhanced functionality and a smaller footprint, which is advantageous for small devices such as mobile phones, tablets, and digital music players. Utility Model Content

[0004] This invention relates to a semiconductor structure that has sufficient scope for implementation in terms of the feasibility of bonding semiconductor structures.

[0005] According to an embodiment of the present invention, a semiconductor structure includes a substrate and a multilayer metal pattern. The multilayer metal pattern is disposed on the substrate, wherein the thickness of a first thick metal layer in the multilayer metal pattern is twice or more the thickness of a next metal pattern. The first thick metal layer includes a first electrical transport pattern having a first pattern distribution density and a first dummy pattern. The first overall distribution density of the first electrical transport pattern and the first dummy pattern is higher than the first pattern distribution density by less than or equal to 125%. The distance between one of the first dummy patterns and its adjacent first electrical transport pattern or first dummy pattern is 0.5 μm. The metal patterns in each multilayer metal pattern are arranged at intervals, with the interval between metal patterns more adjacent to the substrate being smaller than the interval between metal patterns farther from the substrate. A second thick metal layer in the multilayer metal pattern is disposed on the first thick metal layer, and the thickness of the second thick metal layer is twice or more the thickness of the first thick metal layer. The second thick metal layer includes a second electrical transport pattern having a second pattern distribution density and a second dummy pattern. The second overall distribution density of the second electrical transport pattern and the second dummy pattern is less than or equal to 20% higher than the second pattern distribution density. The distance between one of the second dummy patterns and the second electrical transport pattern or an adjacent second dummy pattern is 0.5 μm. The semiconductor structure also includes a dielectric layer disposed between the first thick metal layer and the second thick metal layer, and the material of the dielectric layer includes silicon nitride. The thickness of the dielectric layer is 15,000 angstroms.

[0006] According to an embodiment of the present invention, a semiconductor structure includes a substrate and a multilayer metal pattern. The multilayer metal pattern is disposed on the substrate, wherein the thickness of a thick metal layer in the multilayer metal pattern is greater than 25,000 angstroms. The thick metal layer includes an electrical transport pattern having a pattern distribution density; and dummy patterns. The overall distribution density of the electrical transport pattern and the dummy patterns is less than or equal to 20% higher than the pattern distribution density. The distance between one of the dummy patterns and an adjacent electrical transport pattern or dummy pattern is 0.5 μm. The semiconductor structure also includes a dielectric layer disposed on the substrate. The thick metal layer is disposed on the dielectric layer, and the material of the dielectric layer includes silicon nitride. Attached Figure Description

[0007] Figure 1 A semiconductor component according to some embodiments of the present invention is illustrated schematically.

[0008] Figure 2 A semiconductor component according to some embodiments of the present invention is illustrated schematically.

[0009] Figure 3 This is a schematic flowchart illustrating the manufacturing of a semiconductor structure according to some embodiments.

[0010] Figure 4 A top view schematically illustrating a thick metal layer in a semiconductor structure according to some embodiments of the present invention is shown.

[0011] Figure 5 A portion of a semiconductor structure according to some embodiments of the present invention is illustrated schematically.

[0012] Figure 6 A portion of a semiconductor structure according to some embodiments of the present invention is illustrated schematically.

[0013] Figure 7 A portion of a semiconductor structure according to some embodiments of the present invention is illustrated schematically. Detailed Implementation

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0015] The following provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended for evaluation. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of the present invention. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “underneath,” “above,” and “above” to describe the relationship between one component or feature and another component as shown in the figure. In addition to the orientations depicted in the figure, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein can be interpreted accordingly.

[0017] Packages and methods of forming the packages are provided according to various exemplary embodiments. Intermediate stages of package formation are shown. Variations of the embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used to indicate the same components.

[0018] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on a redistribution layer or substrate, which allow for the testing of 3D packages or 3DICs; the use of probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with intermediate verification test methods incorporating known good die characteristics to increase yield and reduce costs.

[0019] Figure 1 A semiconductor assembly according to some embodiments of the present invention is schematically illustrated. The semiconductor assembly 10 includes two semiconductor structures 12 and 14 bonded to each other and an external interconnect 16. In some embodiments, each of the semiconductor structures 12 and 14 may include a substrate 110 as part of a wafer substrate, a multilayer metal pattern 120, and a plurality of bonding features 130. The multilayer metal pattern 120 is sequentially stacked on the substrate 110, and the bonding features 130 are disposed on the multilayer metal pattern 120 to contact the other structure. In some embodiments, each of the semiconductor structures 12 and 14 further includes a circuit member 112, such as a transistor, disposed on the substrate 110 on the side of the substrate 110 adjacent to the multilayer metal pattern 12. The multilayer metal pattern 120 establishes an electrical transport path for the circuit member 112. The bonding feature 130 includes a bonding pad 132 and a bonding via 134 disposed between the bonding pad 132 and the multilayer metal pattern 120. Semiconductor structure 12 or semiconductor structure 14 also includes a dielectric structure comprising multiple dielectric layers for separating different patterns of multilayer metal pattern 120 and bonding feature 130. External connectors 16 for connecting external components / devices and bonding semiconductor structure 12 to semiconductor structure 14 are disposed on opposite sides of substrate 110 of semiconductor structure 14. Therefore, semiconductor structure 14 also includes a substrate via 140 extending through the thickness of substrate 110 of semiconductor structure 14, the substrate via 140 establishing signal transmission features through substrate 110.

[0020] In this embodiment, semiconductor structure 12 and semiconductor structure 14 are joined face-to-face, such that circuit components 112 of substrate 110 in semiconductor structure 12 are disposed on the (front) side of substrate 110 facing the (front) side of substrate 110 in semiconductor structure 14 having circuit components 112. In some embodiments, the bonding interface 20 between semiconductor structure 12 and semiconductor structure 14 is a metal-to-metal and dielectric-to-dielectric bonding interface. In this embodiment, semiconductor assembly 10 also includes a redistribution wiring structure 18 disposed on the (back) side of semiconductor structure 14 opposite to semiconductor structure 12. The redistribution wiring structure 18 is located between external connector 16 and semiconductor structure 14. In semiconductor structure 14, a substrate via 140 connects the front-side multilayer metal pattern 120 and the back-side redistribution wiring structure 18.

[0021] Figure 2 A semiconductor component according to some embodiments of the present invention is illustrated schematically. Figure 2 The semiconductor component 30 includes two semiconductor structures 12 and 14 bonded together and an external connector 16. Semiconductor structure 12 is similar to... Figure 1 The described semiconductor structure 12 includes a substrate 110, a multilayer metal pattern 120, and a bonding feature 130. Semiconductor structure 14 is similar. Figure 1 The described semiconductor structure 14 includes a substrate 110, a multilayer metal pattern 120, a bonding feature 130', and a substrate via 140. Each of the semiconductor structures 12 and 14 also includes a dielectric structure comprising multiple dielectric layers separating the different patterns of the multilayer metal pattern 120 and the bonding features 130 / 130'.

[0022] In semiconductor assembly 30, each of semiconductor structures 12 and 14 also includes a circuit member 112. The substrate 110 of semiconductor structure 12 is oriented with the circuit member 112 facing the external connector 16, and the substrate 110 of semiconductor structure 14 is also oriented with the circuit member 112 facing the external connector 16, such that semiconductor structures 12 and 14 are bonded to each other in a face-to-back manner. Furthermore, the bonding feature 130' of semiconductor structure 140 in semiconductor assembly 14 can be implemented separately through bonding pad 132, but the present invention is not limited thereto.

[0023] In the semiconductor structures 12 and 14 of semiconductor components 10 and 30, respectively, bonding vias 134 are disposed on a multilayer metal pattern 120, and bonding pads 132 are disposed at the ends of the bonding vias 134. In the semiconductor structure 14 of semiconductor component 30, bonding pads 132 are configured to connect to substrate vias 140. The bonding pads 132 on semiconductor structure 12 and on semiconductor structure 14 are in contact with each other. In some embodiments, the bonding pads 132 on semiconductor structure 12 and on semiconductor structure 14 are made of the same material. After bonding, the boundary between the bonding pads 132 on semiconductor structure 12 and on semiconductor structure 14 may be difficult to determine. In some embodiments, the bonding pads 132 on semiconductor structure 12 and on semiconductor structure 14 may have different lateral dimensions to form a stepped structure that helps to define the bonding interface 20. In some embodiments, bonding pads 132 on semiconductor structure 12 and bonding pads 132 on semiconductor structure 14 may be imperfectly aligned to form an interlaced structure that helps to define the bonding interface 20.

[0024] In some embodiments, the multilayer metal pattern 120 in each of the semiconductor structures 12 and 14 in semiconductor components 10 and 30 may be implemented using a similar or identical design as described below. In some embodiments, the multilayer metal pattern 120 is sequentially disposed on the front side of a substrate 110 having circuit components 112 and includes a first thick metal layer 122, a second thick metal layer 124, and other metal layers 126. In each of the semiconductor structures 12 and 14, the metal layer 126 is closer to the substrate 110 than the first thick metal layer 122 and the second thick metal layer 124. The first thick metal layer 122 and the second thick metal layer 124 are the two thickest layers in the multilayer metal pattern 120.

[0025] In some embodiments, the first thick metal layer 122 and metal layer 126 constitute an interconnect structure of semiconductor structure 12 or semiconductor structure 14, and in some embodiments, a total of 13 to 21 metal layers constitute the interconnect structure, but the present invention is not limited thereto. In some embodiments, the thickness of the first thick metal layer 122 is greater than that of any metal layer 126. The first thick metal layer 122 may be the thickest metal layer of the interconnect structure. In some embodiments, the thickness of the first thick metal layer 122 is twice or more the thickness of a metal layer 126 adjacent to the first thick metal layer 122. In some embodiments, the thickness of the first thick metal layer 122 is in the range of 8,000 angstroms to 12,000 angstroms, and the thickness of each metal layer 126 is in the range of greater than 0 angstroms to 3,000 angstroms.

[0026] In some embodiments, each metal layer in the interconnect structure establishes a plurality of signal transmission features arranged at a specified pitch greater than 126 nm. In some embodiments, the metal patterns in each metal pattern 120 are arranged at a pitch such that the pitch of a metal pattern 120 closer to the substrate 110 is smaller than the pitch of another metal pattern 120 farther from the wafer substrate 110. The pitch of the signal transmission features established by the first thick metal layer 122 may be greater than the pitch of the signal transmission features established by any metal layer 126. In some embodiments, the pitch of the signal transmission features established by the first thick metal layer 122 may be in the range of 700 nm to 2,000 nm. In some embodiments, the pitch of the signal transmission features of the metal layer 126 closest to the substrate 110 may be less than 150 nm and greater than 126 nm. In some embodiments, the metal layers in the interconnect structure comprise metals or metal alloys, such as copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), or combinations thereof.

[0027] A second thick metal layer 124 in semiconductor structure 12 or 14 is disposed on the first thick metal layer 122 to rearrange the electrical connections of the multilayer metal pattern 120 and provide contact features for the bonding feature 130. In some embodiments, the thickness of the second thick metal layer 124 may be twice or more the thickness of the first thick metal layer 122. For example, the thickness of the second thick metal layer 124 may be in the range of about 25,000 angstroms to about 30,000 angstroms. In some embodiments, the thickness of the second thick metal layer 124 may be about 28,000 angstroms. In some embodiments, the second thick metal layer 124 establishes signal transmission features, and the spacing of the signal transmission features of the second thick metal layer 124 may be greater than 720 nm, but the present invention is not limited thereto.

[0028] In some embodiments, the materials of the first thick metal layer 122 and the second thick metal layer 124 may have a modulus greater than 100 GPa and a coefficient of thermal expansion (CTE) less than 20 × 10⁻⁶ / K @ 20 °C. In some embodiments, the materials of the first thick metal layer 122 and the second thick metal layer 124 may include Cu, with a modulus of 110 GPa and a CTE of 17 × 10⁻⁶ / K @ 20 °C. Semiconductor assembly 10 and semiconductor assembly 30 are formed by bonding two semiconductor structures 12 and 14 together through bonding features 130 / 130' integrally formed on substrate 110 without the use of external bumps, conductor pillars, etc. Warpage that occurs during the fabrication of semiconductor structures 12 or 14 at the wafer-level process affects bonding yield. In semiconductor structures 12 and 14, due to their large thickness and modulus, the first thick metal layer 122 and the second thick metal layer 124 may be more sensitive to fabrication-induced warpage than the other layers (metal layer 126) of the multilayer metal pattern 120.

[0029] In some embodiments, each layer of a multilayer metal pattern in a semiconductor structure can be fabricated based on given pattern parameters to ensure fabrication feasibility. Each pattern parameter of each layer in the multilayer metal pattern 120 may include a range of metal density, a range of metal thickness, and other parameters of the metal pattern. In some embodiments, each pattern parameter may be specified within a given range based on the capabilities of the semiconductor manufacturing plant and the feasibility of the manufacturing process. In some embodiments, warpage induced during the manufacturing process is a significant factor in the fabrication of semiconductor components, as undesirable warpage often leads to manufacturing failures and / or low yields, poor product quality, etc. The warpage of a semiconductor structure is related to the curvature (1 / Ri, Ri: radius of curvature) of the substrate on which each layer of metal pattern is formed. In some embodiments, curvature can be calculated using the Stoney equation. For example, the calculated curvature of all metal pattern layers can be calculated based on the Stoney equation, and the calculated curvature of all metal pattern layers formed on the wafer substrate can be combined to determine / simulate the warpage of the model structure. In some embodiments, in addition to the physical properties of the substrate, warpage is also positively correlated with the coefficient of thermal expansion (CTE) of each layer, the thickness of each layer, and the distribution density of each layer. In addition, materials with higher modulus and greater thickness are more sensitive to warping.

[0030] Figure 3 This is a schematic flowchart illustrating the manufacturing of a semiconductor structure according to some embodiments. It can be employed... Figure 3 The method 1000 shown is used to fabricate semiconductor structures 12 or 14. Method 1000 may include step 1010 of providing a thick metal density range for the model structure. In some embodiments, the model structure may include a wafer substrate and a multilayer metal pattern stacked on the wafer substrate. In some embodiments, the model structure may also include other components and / or layers formed on the wafer substrate for fabricating the semiconductor structure. The multilayer metal pattern described in step 1010 may refer to… Figure 1 and Figure 2 The multilayer metal pattern 120 is shown. Here, the thick metal density range defines the distribution density of the metal pattern of the thick metal layer in the multilayer metal pattern within a given range, and the given range can be from a lower limit thick metal (TM) density value to an upper limit TM density value. Furthermore, the thickness of the thick metal layer is twice or more the thickness of one of the metal pattern layers adjacent to the thick metal layer. For example, the thick metal density range depicted in method 1000 refers to... Figure 1 and Figure 2 Manufacturing parameters for the pattern distribution density of the first thick metal layer 122 or the second thick metal layer 124 as described herein.

[0031] In some embodiments, the warpage range of the model structure is preferably within a target warpage range from a lower target value to an upper target value. In some embodiments, negative warpage may affect manufacturing. Figure 1and Figure 2 The semiconductor components 10 and 30 shown cause disadvantages. For example, a target warpage range from +50 μm (lower target value) to +250 μm (upper target value) would be beneficial for bonding. Figure 1 and Figure 2 The semiconductor structures 12 and 14 are depicted. When the lower limit of the warpage range is negative or below the target lower limit value, the warpage range is undesirable and therefore requires modification, but the present invention is not limited thereto. In some embodiments, even when the lower limit of the warpage range is greater than the target lower limit value, the warpage range can still be modified for design considerations.

[0032] In this embodiment, method 1000 also includes step 1020 of modifying the thick metal density range to constrain the warpage range of the model structure. In some embodiments, the constrained warpage range of the model structure is closer to, meets, or is within the target warpage range. For example, the lower limit of the constrained warpage range is closer to the lower limit target value of the warpage target range than before constraint. In some embodiments, modifying the thick metal density range may include increasing the lower limit TM density value of the thick metal density range. In some embodiments, modifying the thick metal density range may also include decreasing the upper limit TM density value of the thick metal density range. In some embodiments, modifying the thick metal density range may include reducing the range size of the thick metal density range, i.e., constraining the thick metal density range.

[0033] In some embodiments, the thick metal layer depicted in method 1000 may be Figure 1 and Figure 2 The first thick metal layer 122 shown has a thickness in the range of 8,000 angstroms to 12,000 angstroms and a high modulus greater than 100 GPa. For Figure 1 and Figure 2 The first thick metal layer 122 shown, with a 1% increase in metal density, results in a 3.6 μm increase in warpage of the model structure. For Figure 1 and Figure 2 The first thick metal layer 122 shown can have its thick metal density range modified by increasing the lower limit TM density value of the thick metal density range by an amount less than or equal to (≤) 125%, for example, (modified lower limit TM density value - initial lower limit TM density value) / initial lower limit TM density value ≤ 125%. For example, the initial lower limit TM density value could be 20%, and the modified lower limit TM density value could be 45%, but this invention is not limited thereto. Figure 1 and Figure 2The modification of the thick metal density range of the first thick metal layer 122 shown may further include reducing the upper limit TM density value of the thick metal density range by a margin of less than or equal to ≤6%, for example, (modified upper limit TM density value - initial upper limit TM density value) / initial upper limit TM density value ≤6%. For Figure 1 and Figure 2 The first thick metal layer 122 shown has its thickness density range modified to constrain the size of the thick metal density range to less than or equal to (≤) 46%, for example, (initial thick metal density range size - modified thick metal density range size) / initial thick metal density range size ≤ 46%, which provides sufficient design flexibility. In some embodiments, Figure 1 and Figure 2 The pattern distribution density of the metal layer 126 shown can be Figure 1 and Figure 2 The modified lower limit TM density value of the first thick metal layer 122 shown is two or more times.

[0034] In some embodiments, the thick metal layer depicted in method 1000 may be Figure 1 and Figure 2 The second thick metal layer 124 shown has a thickness greater than 25,000 angstroms. For Figure 1 and Figure 2 The second thick metal layer 124 shown shows that a 1% increase in the thickness of the metal layer will result in a 4.6 μm increase in the warpage of the model structure. For Figure 1 and Figure 2 The second thick metal layer 124 shown can modify the thick metal density range by increasing the lower limit TM density value of the thick metal density range by an amount less than or equal to (≤) 20%, for example: (modified lower limit TM density value - initial lower limit TM density value) / initial lower limit TM density value ≤ 20%. For example, the initial lower limit TM density value can be 50%, and the modified lower limit TM density value can be about 60%, but the present invention is not limited thereto. Figure 1 and Figure 2 The second thick metal layer 124 shown can have its thickness density modified by a margin of ≤33%, constraining the range of the thick metal density range, for example, (initial thick metal density range size - modified thick metal density range size) / initial thick metal density range size ≤33%. Figure 1 and Figure 2 The second thick metal layer 124 shown can maintain the upper limit TM density value of the thick metal density range without modification to ensure a sufficient range size of the thick metal density range.

[0035] In some embodiments, method 100 further includes step 1030 of fabricating a semiconductor structure by forming a multilayer metal pattern on a wafer substrate based on a modified thick metal density range. Specifically, the thick metal layers in the multilayer metal pattern are formed based on a modified thick metal density range. In some embodiments, a multilayer metal pattern is formed on a wafer substrate using method 1000, and the wafer substrate having the multilayer metal pattern is diced into grains to obtain, as... Figure 1 and Figure 2 The semiconductor structure 12 or semiconductor structure 14 is shown. Based on the modified thick metal density range obtained in step 1020, the warpage of the wafer substrate having multilayer metal patterns thereon can be controlled to approach or meet the target warpage range, for example, +50 μm to +250 μm, which is advantageous. Figure 1 and Figure 2 The depicted semiconductor structure 12 and semiconductor structure 14 are joined together.

[0036] In some embodiments, step 1030 of fabricating the semiconductor structure may further include forming an upper dielectric layer over a multilayer metal pattern. The upper dielectric layer may be made of silicon nitride. Additionally, the warpage range of the model structure described in step 1020 can be further constrained by modifying the thickness range of the upper dielectric layer. In some embodiments, the specified thickness range of the upper dielectric layer is 5,000 angstroms to 9,000 angstroms. In some embodiments, when the warpage range obtained by individually modifying the thick metal density range is undesirable, the lower limit of the specified thickness range of the upper dielectric layer may be reduced to 2,000 angstroms to 4,000 angstroms. In some embodiments, when the warpage range obtained by individually modifying the thick metal density range is not ideal, the upper limit of the specified thickness range of the upper dielectric layer may be increased to 11,000 angstroms to 15,000 angstroms.

[0037] Figure 4 A top view schematically illustrating a thick metal layer in a semiconductor structure according to some embodiments of the present invention is shown. Figure 4 The thick metal layer 200 in the middle can be a metal layer with a large thickness, for example... Figure 1 and Figure 2 The first thick metal layer 122 or the second thick metal layer 124 in the middle. The wiring of the thick metal layer 200 can be Figure 1 and Figure 2 An embodiment of the first thick metal layer 122 or the second thick metal layer 124 in the middle, and can utilize Figure 3The present invention is manufactured using method 1000, but is not limited thereto. The thick metal layer 200 includes an electrical transmission pattern 210 and a dummy pattern 220. The electrical transmission pattern 210 is a metal pattern that establishes electrical signal transmission features, and the dummy pattern 220 is a metal pattern that is electrically suspended and does not transmit electrical signals. In some embodiments, one or more conductor features 40, such as conductor vias, are provided on the electrical transmission pattern 210 to connect the electrical transmission pattern 210 to another metal pattern. In cross-sectional views, the conductor features 40 may be positioned below or above the electrical transmission pattern 210 to connect the transmission pattern 210 to the metal pattern of other layers. However, no conductor features 40 are arranged on the dummy pattern 220.

[0038] In some embodiments, the electrical transport pattern 210 of the thick metal layer 200 may be designed based on an initially given thick metal density range as described in step 1010 of method 1000. For example, the electrical transport pattern 210 is arranged to have a distribution density not greater than a lower limit TM density value of the given thick metal density range. To satisfy the initially given lower limit TM density value, when the distribution density of the electrical transport pattern 210 is lower than the initially given lower limit TM density value, a dummy pattern 220 is added to the thick metal layer 200. As shown in steps 1020 and 1030, the lower limit TM density value needs to be increased when the given thick metal density range used to form the thick metal layer 200 needs to be modified to satisfy or approach a warp target range. Therefore, even if the distribution density of the electrical transport pattern 210 is equal to the initial lower limit TM density value, a dummy pattern 220 is further added to the thick metal layer 200 to achieve a desired pattern density within the modified thick metal density range. In some embodiments, the total distribution density of the electrical transmission pattern 210 and the dummy pattern 220 is greater than the pattern distribution density of the electrical transmission pattern 210 by a margin of less than or equal to 125% of the pattern distribution density of the electrical transmission pattern 210.

[0039] In some embodiments, the distance D1 between one of the dummy patterns 220 and an adjacent one of the electrical transmission patterns 210 ranges from about 0.3 μm to about 0.7 μm, for example, about 0.5 μm, and the distance D2 between two adjacent dummy patterns 220 ranges from about 0.3 μm to about 0.7 μm. In some embodiments, for a thick metal layer 200 having a thickness in the range of 8,000 angstroms to 12,000 angstroms, the spacing P210 of the electrical transmission patterns 210 can be from 700 nm to 2,000 nm. In some embodiments, for a thick metal layer 200 having a thickness greater than 25,000 angstroms, the spacing P210 of the electrical transmission patterns 210 can be greater than 720 nm.

[0040] Figure 5A portion of a semiconductor structure according to some embodiments of the present invention is illustrated schematically. Figure 5 The structure shown is Figure 1 and Figure 2 The first thick metal layer 122 and the second thick metal layer 124 in the semiconductor structure 12 or 14 shown are for illustrative purposes. Figure 5 The middle part is omitted Figure 1 and Figure 2 Some components of the semiconductor structure 12 or 14 shown. For example... Figure 5 As shown, the first thick metal layer 122 includes a plurality of first electrical transmission patterns 122S and a plurality of first dummy patterns 122D. For descriptive purposes, Figure 5 The first electrical transmission pattern 122S in the diagram is filled with a single shaded line, and Figure 5 The first dummy pattern 122D is filled with double shaded lines. In some embodiments, the first electrical transport pattern 122S and the first dummy pattern 122D are formed to be embedded in the dielectric structure 310 and covered by the dielectric layer 320. A second thick metal layer 124 is disposed on the dielectric layer 320. The second thick metal layer 124 includes a plurality of second electrical transport patterns 124S disposed above the first thick metal layer 122. A passivation layer 330 conformally covers the dielectric layer 320 and the second electrical transport patterns 124S. A polymer layer 340 is disposed above the passivation layer 330 to fill the space between the second electrical transport patterns 124S. In some embodiments, bonding features 130 (e.g., Figure 1 and Figure 2 The via 134 depicted is configured to penetrate the polymer layer 340 to contact the second electrical transport pattern 124S. An upper dielectric layer 350 is disposed on the polymer layer 340 above the second thick metal layer 124. The upper dielectric layer 350 is located on... Figure 1 and Figure 2 Above all layers of the multi-layered metal pattern 120 shown.

[0041] The dielectric structure 310 may include undoped quartz glass (USG) or silicon oxide. The dielectric layer 320 may be formed of silicon nitride, and the thickness of the dielectric layer 320 may range from about 2,000 angstroms to about 11,000 angstroms, for example, about 15,000 angstroms. The dielectric layer 320 may include two or more sublayers collectively referred to as an insulating structure. In some embodiments, one or more passive components (not shown) may be disposed between the sublayers of the dielectric layer 320 to be embedded within the dielectric layer 320. The passive components may include resistors, capacitors, or diodes. In some embodiments, the passive components may include metal-insulator-metal (MIM) capacitors. The passivation layer 330 may include silicon nitride. The polymer layer 340 may be deposited using spin coating and may be formed of a polymeric material such as polyimide. The upper dielectric layer 350 may be made of the same material as the dielectric layer 320, such as silicon nitride. The thickness of the upper dielectric layer 350 is in the specified range of 5,000 angstroms to 9,000 angstroms.

[0042] In some embodiments, the first thick metal layer 122 is Figure 1 and Figure 2 The illustrated multilayer metal pattern 120 is one layer and has a thickness twice or more than that of the adjacent layer metal pattern 120, such as a metal layer 126 below a first thick metal layer 122. In some embodiments, the thickness T122 of the first thick metal layer 122 can be from 8,000 angstroms to 12,000 angstroms, for example, 8,500 angstroms. In some embodiments, the second thick metal layer 124 is... Figure 1 and Figure 2 The second thick metal layer 124 is one of the 120 layers of the metal pattern depicted, and has a thickness at least twice that of the next layer of metal pattern 120 (e.g., the first thick metal layer 122). In some embodiments, the thickness T124 of the second thick metal layer 124 may be greater than 25,000 angstroms, for example, 28,000 angstroms. In some embodiments, the first thick metal layer 122 and the second thick metal layer 124 are... Figure 1 and Figure 2 The two thickest layers in the multilayer metal pattern 120 depicted by the semiconductor structure 12 or 14.

[0043] Figure 5 The first thick metal layer 122 shown can be used Figure 3The method 1000 shown is used to manufacture the first electrical transport pattern 122S. In some embodiments, the first electrical transport pattern 122S may be designed to have a pattern distribution density based on the thick metal density range described in step 1010. In some embodiments, after performing step 1020, it may be determined that the calculated warpage is undesirable at the pattern distribution density of the first electrical transport pattern 122S, and therefore step 1020 is performed to obtain a modified thick metal density range. The first thick metal layer 122 is manufactured by adding a first dummy pattern 122D to meet the modified thick metal density range. Therefore, the overall distribution density of the first electrical transport pattern 122S and the first dummy pattern 122D is greater than the pattern distribution density of the first electrical transport pattern 122S to a degree less than or equal to 125% of the pattern distribution density of the first electrical transport pattern 122S, for example: overall pattern distribution density of the first electrical transport pattern 122S and the first dummy pattern 122D - pattern distribution density of the first electrical transport pattern 122S / pattern distribution density of the first electrical transport pattern 122S ≤ 125%.

[0044] In the first thick metal layer 122, the first electrical transport pattern 122S is electrically connected to the second thick metal layer 124 through conductive vias (not shown) passing through the dielectric layer 320, and the first dummy pattern 122D is an electrically floating metal pattern. In some embodiments, the spacing P122 of the first electrical transport patterns 122S can be from 700 nm to 2,000 nm. The distance D1A between one of the first dummy patterns 122D and an adjacent one of the first electrical transport patterns 122S is approximately 0.5 μm, and the distance D2A between two adjacent ones of the first dummy patterns 122D is approximately 0.5 μm.

[0045] In some embodiments, the first thick metal layer 122 may be Figure 1 and Figure 2 The depicted interconnect structure is formed in one layer of the metal layer 126 using the same process. Each metal pattern of the first thick metal layer 122 may include a seed layer 122a with a U-shaped structure and a fill metal 122b with a U-shaped structure filling the seed layer 122a. In some embodiments, the seed layer 122a and the fill metal 122b may be flush with the top surface TS122 of the metal pattern, and the sidewalls S122b of the fill metal 122b are isolated from the dielectric structure 310 through the seed layer 122a. In other words, the sidewalls S122b of the fill metal 122b are in contact with the seed layer 122a. Each metal pattern of the second thick metal layer 124 includes a seed layer 124a and a metal feature 124b on the seed layer 124a. The passivation layer 330 contacts the sidewalls S124b of the metal feature 124b and the sidewalls S124a of the seed layer 124a. The metal feature 124b may have an arcuate top surface TS124. Each joining feature 130 (e.g., Figure 1 and Figure 2The through-hole 132 depicted includes a seed layer 130a with a U-shaped structure and a filler metal 130b with a U-shaped structure filling the seed layer 130a. The bottom of the seed layer 130a contacts the arcuate top surface TS124. In some embodiments, one or more pad / barrier layers may also be provided along the seed layers 122a, 124a and 130a.

[0046] Figure 6 A portion of a semiconductor structure according to some embodiments of the present invention is illustrated schematically. Figure 6 The structure shown is Figure 1 and Figure 2 The first thick metal layer 122 and the second thick metal layer 124 in the semiconductor structure 12 or 14 shown are for illustrative purposes. Figure 6 The middle part is omitted Figure 1 and Figure 2 Some components of the semiconductor structure 12 or 14 shown. Additionally, Figure 6 The components described in Figure 5 The components described in the figures are similar, therefore the same reference numerals in the two figures refer to the same or similar components.

[0047] exist Figure 6 In this structure, a first thick metal layer 122 is embedded in the dielectric structure 310 and includes a first electrical transport pattern 122S. A dielectric layer 320 is disposed on the first thick metal layer 122 and has a large thickness, for example, 15,000 angstroms. A second thick metal layer 124 is disposed on the dielectric layer 320, and its thickness T124 is twice or more than the thickness T122 of the first thick metal layer 122 adjacent to the second thick metal layer 124. In some embodiments, the thickness T124 of the second thick metal layer 124 is greater than 25,000 angstroms. A passivation layer 330 conformally covers the dielectric layer 320 and the second thick metal layer 124. A polymer layer 340 fills the high-low structure formed by the second thick metal layer 124. An upper dielectric layer 350 is disposed on the flat surface of the polymer layer 340.

[0048] In an embodiment, the second thick metal layer 124 includes a second electrical transmission pattern 124S and a second dummy pattern 124D. For descriptive purposes, Figure 6 The second electrical transmission pattern 124S in the diagram is filled with a single shaded line, and Figure 6 The second dummy pattern 124D is filled with double shaded lines. The second electrical transmission pattern 124S establishes a signal transmission feature, and the second dummy pattern 124D is electrically floating. In some embodiments, the second electrical transmission pattern 124S is through a conductor feature (see reference). Figure 4The conductor feature 40 is electrically connected to the corresponding bonding feature 130 and / or electrically connected to the first electrical transmission pattern 122S. The second dummy pattern 124D is isolated from other metal patterns through dielectric materials such as dielectric layer 320, passivation layer 330, and polymer layer 340.

[0049] Figure 6 The second thick metal layer 124 shown can be used Figure 3 The method 1000 shown is used to manufacture the second electrical transport pattern 124S. In some embodiments, the second electrical transport pattern 124S may be designed to have a pattern distribution density based on the thick metal density range described in step 1010. In some embodiments, after performing step 1020, it may be determined that the calculated warpage is undesirable at the pattern distribution density of the second electrical transport pattern 124S, and therefore step 1020 is performed to obtain a modified thick metal density range. The second thick metal layer 124 is manufactured to meet the modified thick metal density range by inserting a second dummy pattern 124D. Therefore, the overall distribution density of the second electrical transport pattern 124S and the second dummy pattern 124D is greater than the pattern distribution density of the second electrical transport pattern 124S, by a factor that is less than or equal to 20% of the pattern distribution density of the second electrical transport pattern 124S, for example: (overall pattern distribution density of the second electrical transport pattern 124S and the second dummy pattern 124D - pattern distribution density of the second electrical transport pattern 124S) / initial pattern distribution density of the second electrical transport pattern 124S ≤ 20%. In some embodiments, the distance D1B between one of the second dummy patterns 124D and an adjacent second electrical transmission pattern 124S is approximately 0.5 μm, and the distance D2B between two adjacent second dummy patterns 124D is approximately 0.5 μm. In some embodiments, the spacing P124 of the second electrical transmission patterns 124S can be greater than 720 nm.

[0050] Figure 7 A portion of a semiconductor structure according to some embodiments of the present invention is illustrated schematically. Figure 7 The structure shown is Figure 1 and Figure 2 The first thick metal layer 122 and the second thick metal layer 124 in the semiconductor structure 12 or 14 shown are for illustrative purposes. Figure 6 The middle part is omitted Figure 1 and Figure 2 Some components of the semiconductor structure 12 or 14 shown. Additionally, Figure 7 The described components and Figure 5 and Figure 6 The components described in the figures are similar, therefore the same reference numerals in the three figures refer to the same or similar components.

[0051] Figure 7In the embedded dielectric structure 310, the first thick metal layer 122 includes a first electrical transport pattern 122S and a first dummy pattern 122D, such as... Figure 5 As shown. A dielectric layer 320 is disposed on the first thick metal layer 122, having a large thickness, for example, 15,000 angstroms. Figure 6 As shown, a second thick metal layer 124 is disposed on the dielectric layer 320 and includes a second electrical transport pattern 124S and a second dummy pattern 124D. A passivation layer 330 conformally covers the dielectric layer 320 and the second thick metal layer 124. A polymer layer 340 fills the interlaced structure formed by the second thick metal layer 124. An upper dielectric layer 350 is disposed on the polymer layer 340.

[0052] In the embodiment, the first thick metal layer 122 and the second thick metal layer 124 are composed of Figure 3 The method 1000 shown is used to create the pattern. The first overall distribution density of the first electrical transmission pattern 122S and the first dummy pattern 122D is greater than the first pattern distribution density of the first electrical transmission pattern 122S by a margin of less than or equal to 125% of the first pattern distribution density of the first electrical transmission pattern 122S. The second overall distribution density of the second electrical transmission pattern 124S and the second dummy pattern 124D is greater than the second pattern distribution density of the second electrical transmission pattern 124S by a margin of less than or equal to 20% of the second pattern distribution density of the second electrical transmission pattern 124S.

[0053] In some embodiments, when the warpage calculated at step 1020 of method 1000 is undesirable, the manufacturing parameters of the upper dielectric layer 350 can be further adjusted to achieve the desired stress. For example, the manufacturing conditions of the upper dielectric layer 350 can be adjusted to increase or decrease the stress of the upper dielectric layer 350. In some embodiments, a specified thickness range of the upper dielectric layer 350 can be modified. For example, the lower limit of the specified thickness range of the upper dielectric layer 350 can be adjusted to 2,000 angstroms to 4,000 angstroms. For example, the upper limit of the specified thickness range of the upper dielectric layer 350 can be adjusted to 11,000 angstroms to 15,000 angstroms. In some embodiments, Figure 5 and Figure 6 The upper dielectric layer 350 may have a modified thickness, for example, greater than 9,000 angstroms, up to 11,000 angstroms to 15,000 angstroms; or less than 5,000 angstroms, as low as 2,000 angstroms to 4,000 angstroms.

[0054] In view of the above, a method for manufacturing a semiconductor structure is provided by modifying the range of thick metal density of one or more thick metal layers to be formed on a wafer substrate. The warpage range occurring during manufacturing will meet or approach the target warpage range. The method for manufacturing a semiconductor structure according to embodiments improves the feasibility of bonding semiconductor structures. In the semiconductor structure, the thick metal layer may have a dummy pattern layer to achieve an ideal metal pattern distribution density. In addition, the modified thick metal density range according to embodiments provides sufficient leeway for designing and improving the feasibility of bonding semiconductor structures.

[0055] According to some other embodiments of the present invention, a method of manufacturing a semiconductor structure includes providing a thick metal density range for a model structure, wherein the model structure includes a wafer substrate and a multilayer metal pattern stacked on the wafer substrate; modifying the thick metal density range to constrain the warpage range of the model structure to a target warpage range; and manufacturing the semiconductor structure by forming a metal pattern layer on the wafer substrate, wherein a thick metal layer in the metal pattern layer is formed based on the modified thick metal density range, and the thickness of the thick metal layer is twice or more than that of one of the metal pattern layers adjacent to the thick metal layer. The warpage range is constrained by increasing the lower limit of the warpage range. Manufacturing the semiconductor structure also includes forming an upper dielectric layer on the multilayer metal pattern, and further constraining the warpage range by modifying the thickness range of the upper dielectric layer. The thickness of the thick metal layer ranges from 8,000 angstroms to 12,000 angstroms, and modifying the thick metal density range includes increasing the lower limit of the thick metal density range by an amount ≤125% of the original lower limit thick metal density value. The size of the range of the thick metal density range is constrained by an amount ≤46% of the original thick metal density range. Modifying the thick metal density range includes reducing the upper limit of the thick metal density range by ≤6% of the original upper limit. For thick metal layers with a thickness greater than 25,000 angstroms, modifying the thick metal density range also includes increasing the lower limit of the thick metal density range by ≤20% of the original lower limit. The modification constrains the size of the thick metal density range by ≤33% of the original range. The target warpage range is 50 μm to 250 μm.

[0056] According to some other embodiments of the present invention, a semiconductor structure includes a substrate and a multilayer metal pattern. The multilayer metal pattern is disposed on the substrate, wherein the thickness of a first thick metal layer in the multilayer metal pattern is twice or more the thickness of a next metal pattern. The first thick metal layer includes a first electrical transport pattern having a first pattern distribution density and a first dummy pattern. The first overall distribution density of the first electrical transport pattern and the first dummy pattern is higher than the first pattern distribution density by less than or equal to 125%. The distance between one of the first dummy patterns and its adjacent first electrical transport pattern or first dummy pattern is 0.5 μm. The metal patterns in each multilayer metal pattern are arranged at intervals, with the interval between metal patterns more adjacent to the substrate being smaller than the interval between metal patterns farther from the substrate. A second thick metal layer in the multilayer metal pattern is disposed on the first thick metal layer, and the second thick metal layer has a thickness twice or more than the thickness of the first thick metal layer. The second thick metal layer includes a second electrical transport pattern having a second pattern distribution density and a second dummy pattern. The second overall distribution density of the second electrical transport pattern and the second dummy pattern is less than or equal to 20% higher than the second pattern distribution density. The distance between one of the second dummy patterns and the second electrical transport pattern or an adjacent second dummy pattern is 0.5 μm. The semiconductor structure also includes a dielectric layer disposed between the first thick metal layer and the second thick metal layer, and the material of the dielectric layer includes silicon nitride. The thickness of the dielectric layer is 15,000 angstroms.

[0057] According to some other embodiments of the present invention, the semiconductor structure includes a substrate and a multilayer metal pattern. The multilayer metal pattern is disposed on the substrate, wherein the thickness of a thick metal layer in the multilayer metal pattern is greater than 25,000 angstroms. The thick metal layer includes an electrical transport pattern having a pattern distribution density; and dummy patterns. The overall distribution density of the electrical transport pattern and the dummy patterns is less than or equal to 20% higher than the pattern distribution density. The distance between one of the dummy patterns and an adjacent electrical transport pattern or dummy pattern is 0.5 μm. The semiconductor structure also includes a dielectric layer disposed on the substrate. The thick metal layer is disposed on the dielectric layer, and the material of the dielectric layer includes silicon nitride.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor structure, characterized in that, include: Base; as well as A multi-layer metal pattern is disposed on the substrate, wherein the thickness of a first thick metal layer in the multi-layer metal pattern is twice or more the thickness of a next layer of metal pattern, and the first thick metal layer comprises: The first electrical transmission pattern has a first pattern distribution density; as well as The first dummy pattern, the first electrical transmission pattern, and the first overall distribution density of the first dummy pattern are higher than the first pattern distribution density by less than or equal to 125%.

2. The semiconductor structure according to claim 1, characterized in that, The distance between one of the first dummy patterns and the first electrical transmission pattern or one of the adjacent patterns in the first dummy pattern is 0.5 μm.

3. The semiconductor structure according to claim 1, characterized in that, The metal patterns in each of the multilayer metal patterns are arranged at intervals, with the interval between the metal patterns in the layer more adjacent to the substrate being smaller than the interval between the metal patterns in the layer farther from the substrate.

4. The semiconductor structure according to claim 1, characterized in that, The second thick metal layer in the multilayer metal pattern is disposed on the first thick metal layer, and the thickness of the second thick metal layer is twice or more than the thickness of the first thick metal layer.

5. The semiconductor structure according to claim 4, characterized in that, The second thick metal layer includes: A second electrical transmission pattern, having a second pattern distribution density; and The second dummy pattern, the second electrical transmission pattern, and the second overall distribution density of the second dummy pattern are higher than the second pattern distribution density by less than / equal to 20%, wherein the distance between one of the second dummy patterns and the second electrical transmission pattern or one of the adjacent second dummy patterns is 0.5 μm.

6. The semiconductor structure according to claim 4, characterized in that, It also includes a dielectric layer disposed between the first thick metal layer and the second thick metal layer, and the material of the dielectric layer includes silicon nitride.

7. The semiconductor structure according to claim 6, characterized in that, The dielectric layer has a thickness of 15,000 angstroms.

8. A semiconductor structure, characterized in that, include: Base; as well as A multi-layer metal pattern is disposed on the substrate, wherein the thickness of the thick metal layer in the multi-layer metal pattern is greater than 25,000 angstroms, and the thick metal layer comprises: Electrical transmission pattern, having a pattern distribution density; as well as A dummy pattern, wherein the overall distribution density of the electrical transmission pattern and the dummy pattern is 20% higher than the pattern distribution density by less than or equal to 20%.

9. The semiconductor structure according to claim 8, characterized in that, The distance between one of the dummy patterns and the electrical transmission pattern or the adjacent dummy pattern is 0.5 μm.

10. The semiconductor structure according to claim 8, characterized in that, It also includes a dielectric layer disposed on the substrate, the thick metal layer disposed on the dielectric layer, and the material of the dielectric layer includes silicon nitride.

Images