Lamp electronic pulse test generating circuit
The lamp testing circuit, with its dual independent charging system and high-voltage discharge switch, solves the problem of low efficiency in traditional testing methods, enabling flexible voltage condition switching and positive/negative polarity testing, thereby improving testing efficiency and accuracy while reducing costs.
Patent Information
- Application Number
- CN202423276647.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2034-12-30
AI Technical Summary
Traditional lighting testing methods are inefficient, difficult to switch between different voltage conditions flexibly, and cannot test positive and negative high voltage pulses simultaneously, which increases testing costs and uncertainties.
It employs two independent charging systems and a high-voltage discharge switch, combined with an analog quantity generation module, an optocoupler control module, and an output level control chip, to achieve voltage step-by-step cyclic testing and positive/negative high-voltage switching, thereby enhancing testing flexibility and accuracy.
It improves the efficiency and accuracy of lighting fixture testing, simplifies the testing process, reduces costs, and ensures testing safety and equipment reliability.
Smart Images
Figure CN223808494U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic equipment test field especially, and it is a kind of electronic impulse test generating circuit of lamp. BACKGROUND
[0002] In the LED lighting industry, performance testing of lamps is a key link to ensure product quality and reliability. With the continuous progress of technology and the increasing complexity of lamp design, higher requirements are put forward for the anti-high-voltage pulse start interference ability of lamps. LED lamps can provide sufficient energy in a short time to make the lamps quickly reach the normal working state. However, this start-up method can also cause potential damage to the electronic components of the lamps, especially under long-time or high-frequency pulse interference. In order to ensure that the lamps can operate stably in harsh electrical environments, the lamps must be tested for anti-high-voltage pulse start interference to evaluate whether the performance and structure of the lamps remain intact and whether damage or performance degradation occurs when subjected to high-voltage pulses of a certain voltage value and number of times. Traditional testing methods usually use a single voltage source and discharge circuit, and the testing process is tedious and inefficient. Test personnel need to manually adjust the voltage value and wait for the charging circuit to return to the initial state after each test before proceeding to the next test. This not only consumes a lot of time and effort, but also increases uncertainty and errors in the testing process. In addition, traditional testing equipment also has limitations in testing polarity. Since most lamps need to withstand high-voltage pulses of both positive and negative polarities, and traditional testing equipment can usually only test a single polarity, testers need to use two devices or perform complex polarity conversion operations to complete comprehensive testing. This not only increases testing costs but also reduces testing efficiency. Therefore, how to improve the flexibility of switching between different voltage conditions in lamp testing and make the testing more efficient and accurate is a technical problem to be solved. SUMMARY
[0003] The utility model aims at overcoming the defects of the prior art and provides an electronic impulse test generating circuit for lamps, which realizes efficient testing of lamps under different conditions through two independent charging systems and discharge high-voltage switches. Only by switching the switch position and testing voltage can the cycle high-voltage test, voltage step cycle test and positive and negative high-voltage switching test be realized.
[0004] The utility model can achieve the purpose by the following technical solutions:
[0005] According to one aspect of the utility model, an electronic impulse test generating circuit for lamps is provided, characterized in that it comprises a lamp to be tested, a test voltage switching module, an analog quantity generating module, an optocoupler control module and an output level control chip.
[0006] Two ends of the to-be-tested lamp are connected with a first switch, a second switch, a third switch and a fourth switch in a test voltage switching module.
[0007] In the test voltage switching module, the first switch, the second switch, the third switch and the fourth switch are single-pole double-throw switches, the first switch and the second switch are connected with a first high-voltage power supply, and the third switch and the fourth switch are connected with a second high-voltage power supply.
[0008] In the analog quantity generation module, a 4-pin connection of the analog quantity generation chip is connected with the first high-voltage power supply connection in the test voltage switching module, and a 7-pin connection of the analog quantity generation chip is connected with the second high-voltage power supply connection in the test voltage switching module.
[0009] In the optical coupling control module, a first optical coupling, a second optical coupling and a third optical coupling are connected to a NOT gate isolation chip; a 16-pin of the NOT gate isolation chip is connected with the first switch, a 15-pin is connected with the second switch, a 14-pin is connected with the third switch, and a 13-pin is connected with the fourth switch.
[0010] An output level control chip is connected and drives the first optical coupling, the second optical coupling and the third optical coupling in the optical coupling control module.
[0011] Further, the to-be-tested lamp 1 is connected with a normal working voltage source through the first switch, the second switch, the third switch and the fourth switch.
[0012] Further, in the test voltage switching module, a fifth switch is connected in series with a first resistor R16, and then connected with two output ends of the first high-voltage power supply.
[0013] Further, two ends of the first high-voltage power supply are further connected with a tenth capacitor.
[0014] Further, in the test voltage switching module, a sixth switch is connected in series with a second resistor, and then connected with two output ends of the second high-voltage power supply.
[0015] Further, two ends of the second high-voltage power supply are further connected with an eleventh capacitor.
[0016] Further, a 1-pin of the first optical coupling is connected with VCC, a 3-pin is connected with the output level control chip, and a 5-pin is connected with a 1-pin and a 2-pin of the NOT gate isolation chip.
[0017] Further, a 1-pin of the second optical coupling is connected with VCC, a 3-pin is connected with the output level control chip, and a 5-pin is connected with a 3-pin and a 4-pin of the NOT gate isolation chip.
[0018] Further, a 1-pin of the third optical coupling is connected with VCC, a 3-pin is connected with the output level control chip, and a 5-pin is connected with a 5-pin and a 6-pin of the NOT gate isolation chip.
[0019] Further, the circuit further comprises a current mutual inductance acquisition module, and the current mutual inductance acquisition is connected in the test voltage switching module and connected to the output level control chip F1 through the digital-analog converter U6.
[0020] Compared with the prior art, the utility model has the following beneficial effects:
[0021] (1) improve test efficiency and flexibility: through two independent charging systems and discharge high-voltage switch, realize the efficient test of different conditions of lamps and lanterns, two systems can test two different voltage values simultaneously, and can carry out the quick switching test of positive and negative voltage, shorten the charging preparation time of single loop, improve the test efficiency, also strengthen the flexibility of test, satisfy the test demand of lamps and lanterns in complex electrical environment.
[0022] (2) enhance test accuracy and safety: the linkage test mechanism is introduced in the circuit, the test situation of the measured load is collected and judged in real time through monitoring the current change on the power line, the current value change collected in the test exceeds the allowable range, namely, it is judged that the test load is damaged, and the test is stopped immediately, and the test failure prompt is sent, the test accuracy is improved, and the safety in the test process is ensured, the equipment damage or personnel injury caused by improper test is avoided.
[0023] (3) simplify test process and reduce cost: compared with the traditional test method, the utility model adopts automatic test process, and manual adjustment of voltage value or waiting for charging loop to recover to initial state is not needed, and since the circuit supports high-voltage pulse test of positive and negative polarity, two devices or complex polarity conversion operation are not needed, so that the test process is simplified, and the test cost is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 It is the connection diagram of lamp electronic pulse test generating circuit.
[0025] Marking in the drawing: 1, lamp to be tested;V1, normal working voltage source;P1, current mutual inductance acquisition;U1B, first comparator;U2, first high-voltage power supply;U3, second high-voltage power supply;U4, non-gate isolation chip;U5, analog quantity generation chip;U6, digital-analog converter;F1, output level control chip;S1, first switch;S2, second switch;S3, third switch;S4, fourth switch;S5, fifth switch;S6, sixth switch;C10, tenth capacitor;C11, eleventh capacitor;JP1, first optocoupler;JP2, second optocoupler;JP3, third optocoupler;R16, first resistor;R17, second resistor;SWA, first output level of output level control chip;SWB, second output level of output level control chip;SWC, third output level of output level control chip. Detailed Implementation
[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present utility model. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present utility model.
[0027] like Figure 1 The diagram shows a lamp electronic pulse test generating circuit, characterized by comprising a lamp under test 1, a test voltage switching module, an analog signal generation module, an optocoupler control module, and an output level control chip F1; the two ends of the lamp under test 1 are connected to a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4 in the test voltage switching module; in the test voltage switching module, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are single-pole double-throw switches, the first switch S1 and the second switch S2 are connected to a first high-voltage power supply U2, and the third switch S3 and the fourth switch S4 are connected to a second high-voltage power supply U3; in the analog signal generation module, the analog signal generation module... Pin 4 of analog signal generation chip U5 is connected to the first high-voltage power supply U2 in the test voltage switching module; pin 7 of analog signal generation chip U5 is connected to the second high-voltage power supply U3 in the test voltage switching module; the first optocoupler JP1, the second optocoupler JP2, and the third optocoupler JP3 in the optocoupler control module are connected to the NOT gate isolation chip U4; pin 16 of the NOT gate isolation chip U4 is connected to the first switch S1, pin 15 is connected to the second switch S2, pin 14 is connected to the third switch S3, and pin 13 is connected to the fourth switch S4; the output level control chip F1 is connected to and drives the first optocoupler JP1, the second optocoupler JP2, and the third optocoupler JP3 in the optocoupler control module.
[0028] The lamp under test 1 is connected to the normal operating voltage source V1 through the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4.
[0029] In the test voltage switching module, the fifth switch S5 is connected in series with the first resistor R16, and then connected to the two output terminals of the first high-voltage power supply U2. The two ends of the first high-voltage power supply U2 are also connected to the tenth capacitor C10. In the test voltage switching module, the sixth switch S6 is connected in series with the second resistor R17, and then connected to the two output terminals of the second high-voltage power supply U3. The two ends of the second high-voltage power supply U3 are also connected to the eleventh capacitor C11.
[0030] The pin 1 of the first photo-coupler JP1 is connected with VCC, the pin 3 is connected with the output level control chip F1, and the pin 5 is connected with the pin 1 and the pin 2 of the non-gate isolation chip U4. The pin 1 of the second photo-coupler JP2 is connected with VCC, the pin 3 is connected with the output level control chip F1, and the pin 5 is connected with the pin 3 and the pin 4 of the non-gate isolation chip U4. The pin 1 of the third photo-coupler JP3 is connected with VCC, the pin 3 is connected with the output level control chip F1, and the pin 5 is connected with the pin 5 and the pin 6 of the non-gate isolation chip U4.
[0031] The circuit further comprises a current mutual inductance collection module, and the current mutual inductance collector P1 is connected in the test voltage switching module and connected to the output level control chip F1 through the first comparator U1B and the digital-analog converter U6.
[0032] During the operation of the circuit in the embodiment, at the beginning of the test, the output level control chip F1 controls the output level control chip first output level SWA and the output level control chip second output level SWB to be low level, and the output level control chip third output level SWC to be high level, so as to drive the first photo-coupler JP1 and the second photo-coupler JP2 to enter the working state, and the third photo-coupler JP3 to enter the cut-off state, thereby controlling the output of the photo-coupler, and making the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 be at high level through the non-gate isolation chip U4, and the fifth switch S5 and the sixth switch S6 be at low level. The first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are turned on at high level and turned off at low level. At this time, the normal working voltage source V1 of the lamp to be tested 1 is started, the output level control chip F1 controls the analog quantity generation chip U5 to generate high level and output to the first high-voltage power supply U2 and the second high-voltage power supply U3. After receiving the high level, the first high-voltage power supply U2 and the second high-voltage power supply U3 charge the tenth capacitor C10 and the eleventh capacitor C11. When the time for the cyclic high-voltage test reaches the preset time, the output level control chip F1 controls the output level control chip first output level SWA and the output level control chip second output level SWB to make the two output levels output high and low levels according to the preset time interval, so as to control the first switch S1 and the second switch S2, and the third switch S3 and the fourth switch S4 to switch the switch state according to the time interval. That is, the tenth capacitor C10 and the eleventh capacitor C11 are cyclically connected to the discharge circuit, and the effect of cyclic high-voltage test is achieved. When the output of the analog quantity generation chip U5 controlled by the output level control chip F1 increases according to the preset voltage step, the discharge of the tenth capacitor C10 and the eleventh capacitor C11 also increases according to the voltage step, thereby achieving the effect of voltage step cyclic test. When the first high-voltage power supply U2 and the second high-voltage power supply U3 controlled by the output level control chip F1 generate reverse voltage, the effect of positive and negative high-voltage switching test is achieved.
[0033] In addition, the current mutual inductance acquisition module is used in the circuit, the current mutual inductance collector P1 is connected in the test voltage switching module, is connected to the output level control chip F1 through the first comparator U1B and the digital analog converter U6. The size of the current on the test loop is collected through the current mutual inductance collector P1, is transmitted to the first comparator U1B and the digital analog converter U6, is further transmitted to the output level control chip F1. When the current exceeds the threshold value, it is determined that the test loop is damaged, the output level control chip F1 controls the third output level SWC of the output level control chip to be low, and the output of the analog quantity generation chip U5 to the first high-voltage power supply U2 and the second high-voltage power supply U3 is turned off. The third optocoupler JP3 drives the fifth switch S5 and the sixth switch S6 to be closed, so that the remaining electric quantity in the tenth capacitor C10 and the eleventh capacitor C11 is consumed through the first resistor R16 and the second resistor R17, and a test failure prompt is sent out.
[0034] The above merely illustrates the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A lamp electronic pulse test generation circuit, characterized by, It includes a lamp to be tested (1), a test voltage switching module, an analog quantity generation module, an optical coupling control module and an output level control chip (F1); Both ends of the lamp to be tested (1) are connected with the first switch (S1), the second switch (S2), the third switch (S3) and the fourth switch (S4) in the test voltage switching module. In the test voltage switching module, the first switch (S1), the second switch (S2), the third switch (S3) and the fourth switch (S4) are single-pole double-throw switches, the first switch (S1) and the second switch (S2) are connected with the first high-voltage power supply (U2), and the third switch (S3) and the fourth switch (S4) are connected with the second high-voltage power supply (U3). In the analog quantity generation module, the 4-pin of the analog quantity generation chip (U5) is connected with the first high-voltage power supply (U2) in the test voltage switching module, and the 7-pin of the analog quantity generation chip (U5) is connected with the second high-voltage power supply (U3) in the test voltage switching module. In the optical coupling control module, the first optical coupling (JP1), the second optical coupling (JP2) and the third optical coupling (JP3) are connected to the NOT gate isolation chip (U4); the 16-pin of the NOT gate isolation chip (U4) is connected with the first switch (S1), the 15-pin is connected with the second switch (S2), the 14-pin is connected with the third switch (S3), and the 13-pin is connected with the fourth switch (S4). The output level control chip (F1) drives the first optical coupling (JP1), the second optical coupling (JP2) and the third optical coupling (JP3) in the optical coupling control module.
2. A lamp electronic pulse test generator circuit according to claim 1, characterized in that, The lamp to be tested (1) is connected with the normal working voltage source (V1) through the first switch (S1), the second switch (S2), the third switch (S3) and the fourth switch (S4).
3. A lamp electronic pulse test generator circuit according to claim 1, characterized in that, In the test voltage switching module, the fifth switch (S5) is connected in series with the first resistor (R16), and then connected with the two output ends of the first high-voltage power supply (U2).
4. A lamp electronic pulse test generator circuit according to claim 3, characterized in that, The two ends of the first high-voltage power supply (U2) are also connected with the tenth capacitor (C10).
5. A lamp electronic pulse test generating circuit according to claim 1, characterized in that, In the test voltage switching module, the sixth switch (S6) is connected in series with the second resistor (R17), and then connected with the two output ends of the second high-voltage power supply (U3).
6. A lamp electronic pulse test generating circuit according to claim 5, characterized in that, The two ends of the second high-voltage power supply (U3) are also connected with the eleventh capacitor (C11).
7. A lamp electronic pulse test generating circuit according to claim 1, characterized in that, The 1-pin of the first optical coupling (JP1) is connected with VCC, the 3-pin is connected with the output level control chip (F1), and the 5-pin is connected with the 1-pin and the 2-pin of the NOT gate isolation chip (U4).
8. A lamp electronic pulse test generator circuit according to claim 1, characterized in that, The 1-pin of the second optical coupling (JP2) is connected with VCC, the 3-pin is connected with the output level control chip (F1), and the 5-pin is connected with the 3-pin and the 4-pin of the NOT gate isolation chip (U4).
9. A lamp electronic pulse test generating circuit according to claim 1, characterized in that, The 1-pin of the third optical coupling (JP3) is connected with VCC, the 3-pin is connected with the output level control chip (F1), and the 5-pin is connected with the 5-pin and the 6-pin of the NOT gate isolation chip (U4).
10. The electronic pulse test generator circuit for a lamp as defined in Claim 1, wherein, The circuit further includes a current mutual inductance acquisition module, and the current mutual inductance collector (P1) is connected in the test voltage switching module and connected to the output level control chip (F1) through the digital-to-analog converter (U6).