Full-automatic test circuit for embedded board card

Abstract

The utility model relates to a full-automatic test circuit for an embedded board card. The full-automatic test circuit comprises a test module, the test module is electrically connected with the processor; the processor is electrically connected with a background server; the test module comprises an input and output opposite test module, a USB test module, a key test module, a PCI E test module and an ADC test module; the input and output opposite measurement module comprises a plurality of current-limiting resistors Ra; a belongs to N; two ends of the resistor Ra are connected with GPIa lines and are connected with a corresponding end Pa and a corresponding end Ta; the end Pa and the end Ta are used as IO configuration for testing; the USB test module comprises a plurality of USB signal lines, and a resistor Rb is arranged on each USB signal line; two ends of the USB signal line are electrically connected with corresponding ports of the conversion chips U5 and U6 respectively; the device is reasonable in design, compact in structure and convenient to use.

Description

TECHNICAL FIELD

[0001] The utility model relates to embedded technology field, concretely relates to full -automatic test circuit for embedded board card. BACKGROUND

[0002] Generally in embedded board card factory detection, need to connect all external equipment of board card, and through assembly line artificial detection all functions in proper order. In the function detection process, some test items need to pass through artificial according to phenomenon to draw a conclusion, exist misjudgment, cannot guarantee 100 percent accuracy. The flow of board card factory detection needs to consume a large amount of artificial cost and time cost, can reduce the economic efficiency of enterprise. INVENTION CONTENTS

[0003] The utility model solves the technical problem that generally provides a kind of full -automatic test circuit for embedded board card. For the embedded board card that needs to be factory detected, can reduce detection time and improve detection efficiency, reduce misjudgment rate and increase judgment accuracy, reduce artificial cost and time cost.

[0004] To solve the above problems, the technical scheme adopted by the utility model is:

[0005] A kind of full -automatic test circuit for embedded board card, including test module;

[0006] Test module is electrically connected processor;Processor is electrically connected the server of background;

[0007] Processor reports test result through RS232 data interface, the rate and stability of RS232 transmission signal can satisfy actual demand, and RS232 interface can be designed on all models of board to be tested and used

[0008] Test module includes input output pair test module, USB test module, key test module, display type interface test, audio interface test, PCIE test module and / or ADC test module;

[0009] Input output pair test module includes a plurality of current-limiting resistors R a ;a∈N;Resistor R a Two ends of GPI a Line is connected with corresponding end P a With end T a ;Every two IOs form a pair, and the pair of IOs is connected by resistance, for testing.

[0010] End P a With end T a As the IO configuration of test;

[0011] The USB test module includes several USB signal lines, and resistors R are installed on the USB signal lines. b ;

[0012] The two ends of the USB signal line are electrically connected to the corresponding ports of the conversion chips U5 and U6, respectively;

[0013] In the conversion chip U5, pins 7 and 8 are connected to VCC in one path and grounded through parallel capacitors C25 and C26 in the other path. Pins 3 and 29 are grounded. Pin 9 is connected to VCC in one path through resistor R84 and grounded through capacitor C27 in the other path.

[0014] The button test module includes transistor Q1; in transistor Q1, the collector is connected to the processor reset pin SYS_WARMRESET, the emitter is grounded, and the base is grounded through resistor R69 and connected to F15 GPIO3 through resistor R67 as an I / O pin.

[0015] The collector is grounded through capacitors C15 and C16 connected in parallel;

[0016] PCIE test module, including chips U10 and U4;

[0017] The ADC test module includes several voltage divider resistors R connected in series between VCC3V3 and GND. i R i+1 , i∈N; in adjacent voltage divider resistors R i With R i+1 There is a node AIN at the node. j ;j∈N;

[0018] Node AIN j As a test tap.

[0019] Furthermore, pin 25 of converter chip U5 is connected to pin 26 of converter chip U6 through resistor R86; pin 26 of converter chip U5 is connected to pin 25 of converter chip U6 through resistor R87.

[0020] Several USB signal lines are configured with one group of USB devices as the master to send data, and at least one group of USB devices as the slave to receive data.

[0021] The USB HOST of the USB test module connects to the USB DEVICE device.

[0022] Furthermore, when F15 GPIO3_13 is in a low-level state, transistor Q1 is not turned on, and SYS_WARMRESET is at the default level;

[0023] When F15 GPIO3_13 outputs a high level, transistor Q1 is turned on, and SYS_WARMRESET is grounded at this time.

[0024] Further, the chip U10 and the chip U4 are external Ethernet transceivers connected through a network cable;

[0025] The chip U10 and the chip U4 are connected to the PCIE interface of the board card to be tested respectively;

[0026] For the chip U10, the pins 12, 21 and 20 are connected to the DVD through corresponding resistors respectively; the pins 15 and 16 are electrically connected to the clock circuit respectively; the pins 13, 14, 17 and 18 are connected to the PCIE port through corresponding capacitors respectively; the pin 19 is connected to the ground through the capacitor C70 in one way and connected to the DVDD through the resistor R132 in another way; the pin 31 is connected to the ground through the resistor R133, and the pins 25-27 are connected to the LED signal; the pins 28 and 29 are electrically connected to the crystal oscillator circuit; the pins 11 and 32 are connected to the PCIE 3v3 through the parallel capacitors C45-C47.

[0027] Further, the test module is mounted on the test board, and the board card to be tested is connected to the test board through the adapter board.

[0028] The test fixture is used for plugging and unplugging the board card to be tested mounted on the adapter board.

[0029] The utility model discloses a full -automatic test circuit for embedded board card factory detection, and the board card to be tested can be automatically function test as long as connecting to test circuit, can detect whether the minimum system of board card to be tested can normally operate, whether the welding is normal, and whether the function can normally work. Its connection is divided into three forms, the first kind is the board card to the board connector, the second kind is the board card to the plane grid array package (LGA), and the third kind is the board card to the stamp hole connection mode.

[0030] In order to ensure that the same set of test circuit can be compatible with the above three connection modes simultaneously, the test circuit is designed as two parts of adapter board and test board, and different adapter boards correspond to mounting different kinds of test board cards. Three kinds of adapter boards can be mounted on the test board. Since the connector and the test fixture mounted on the adapter board are repeatedly plugged and unplugged, the connector and the test fixture become the vulnerable parts in the whole test circuit. This design can not only ensure that a plurality of different kinds of board cards can be tested, but also can realize maintenance by replacing the adapter board when the connector is damaged, thereby reducing the maintenance cost.

[0031] The same set of test circuit can be compatible with a plurality of different test board cards. The whole test circuit resource is rich, and can test high-end embedded platform, and can also realize compatible test for low-end processor with less resources.

[0032] For the common resources of embedded platform, the test circuit is designed and implemented in the following aspects:

[0033] 1. For the common input and output functions, the input and output test mode is designed on the test circuit. It can achieve 1-to-1 test of input and output (IO) pins, and also can achieve 1-to-2 test for input and output pins that cannot be paired 1-to-1.

[0034] 2. For universal serial bus (USB) resource test, two test methods are designed on the test circuit. One is USB HOST connecting USB DEVICE, and in this way, whether the USB device is successfully mounted under the USB HOST is judged for test. The other way is to connect two USB ports to USB-to-serial chips respectively, and then connect the sending port of serial port 1 to the receiving port of serial port 2, and connect the sending port of serial port 2 to the receiving port of serial port 1. In this way, data can be sent / received on the two USB-converted serial ports, and data verification can be performed.

[0035] 3. For the physical keys such as "reset key" and "power key" in embedded devices, the test circuit simulates the operation of physical keys by controlling the conduction of triode, and then performs logical judgment. For example, for testing "reset key", a number is written in the register of the processor of the board under test, and then the number is increased by one in the next start. If the number is greater than the set value, it is judged that the second start is successful, and it can be judged that the reset is successful.

[0036] 4. For the PCIE interface in embedded devices, a PCIE-to-Gigabit / Multigigabit Ethernet controller is connected in the test circuit. First, whether the corresponding device is successfully mounted on the PCIE is tested, and then the network is tested by connecting two Ethernet interfaces to further judge the performance of the PCIE in the processor.

[0037] 5. For the display interface, a protocol conversion chip is used to convert the camera signal into the test board card, so that the display interface and the camera interface can be tested at the same time. For the case that the resources are not enough for 1-to-1 pairing test, the same video protocol can be converted, and then the high-speed switch is used for switching to test respectively. For example, the test board card has HDMI and MIPI_DSI two groups of video output, but only one group of MIPI_CSI video input interface. At this time, DHMI and MIPI_DSI can be converted into MIPI_CSI respectively, and then the high-speed switch is used for switching to test.

[0038] 6. For the audio interface test of embedded devices, the processor plays a 1KHZ audio, and the signal is transmitted back to the processor through the microphone interface after being processed by the test circuit. In the processor, the sound waveform is transmitted back, and if the condition is met, it means that the test is passed.

[0039] 7. Test the analog-to-digital converter (ADC) for embedded devices. The test circuit is divided by resistance, and the analog-to-digital converter is connected to the tap of the voltage dividing resistance. The test is performed by comparing the theoretically calculated voltage value with the actual voltage value collected by the analog-to-digital converter.

[0040] The test circuit controls the power-on enable by an external signal, and realizes the mutual switching between automatic test and manual test.

[0041] The utility model discloses can realize detection function, can fast, accurate, automation to the detection of embedded board card, can fast detection whether all functions are normal before the embedded board card factory, saves manpower and material resources and time for enterprise, simplifies the detection process, improves detection accuracy, improves the economic benefit of enterprise. Its design is reasonable, and the cost is low, and it is solid and durable, safe and reliable, simple to operate, time-saving and labor-saving, saves funds, compact structure and convenient to use. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 It is the test flow diagram of the utility model.

[0043] Figure 2 It is the input and output pair test circuit schematic diagram of the utility model.

[0044] Figure 3 It is the principle schematic diagram of USB test of the utility model.

[0045] Figure 4 It is the key test circuit schematic diagram of the utility model.

[0046] Figure 5 It is the PCIE test part circuit schematic diagram of the utility model.

[0047] Figure 6 It is the PCIE test circuit schematic diagram of the utility model.

[0048] Figure 7 It is the ADC test principle diagram of the utility model.

[0049] Figure 8 It is the overall block diagram of the utility model.

[0050] Figure 9 It is the audio interface test schematic diagram of the utility model.

[0051] Figure 10 It is the board card schematic diagram of the utility model.

[0052] Figure 11 It is the display interface test schematic diagram of the utility model.

[0053] 1, to be measured bottom plate; 2, adapter plate; 3, test plate. DETAILED DESCRIPTION

[0054] As Figures 1-11 , the specific test process is, first, install the test plate; then, test; second, test result upload server; third, remove the test plate for the next test.

[0055] An automatic test circuit for embedded board, comprising a test module;

[0056] The test module is electrically connected to the processor; the processor is electrically connected to the server of the background;

[0057] The test module includes an input-output test module, a USB test module, a key test module, a display test interface, an audio test interface, a PCIE test module and / or an ADC test module;

[0058] The input-output test module includes a plurality of current-limiting resistors R a a∈N; the two ends of the resistor R a are connected to the GPI a line and the corresponding end P a and the end T a ;

[0059] The end P a and the end T a are configured as test IO;

[0060] The USB test module includes a plurality of USB signal lines, and a resistor R b is arranged on the USB signal line;

[0061] The two ends of the USB signal line are respectively electrically connected to the corresponding ports of the conversion chips U5 and U6;

[0062] In the conversion chip U5, pin 7 and pin 8 are connected to VCC in one way and to ground through the parallel connection of capacitors C25 and C26 in the other way, pin 3 and pin 29 are connected to ground, pin 9 is connected to VCC through resistor R84 in one way and to ground through capacitor C27 in the other way;

[0063] The key test module includes a triode Q1; in the triode Q1, the collector is connected to the processor reset pin SYS_WARMRESET, the emitter is connected to ground, the base is connected to ground through resistor R69 in one way and to F15 GPIO3 through resistor R67 in the other way as IO;

[0064] The collector is connected to ground through the parallel connection of capacitors C15 and C16;

[0065] The PCIE test module includes chips U10 and U4;

[0066] The ADC test module includes several voltage divider resistors R connected in series between VCC3V3 and GND. i R i+1 , i∈N; in adjacent voltage divider resistors R i With R i+1 There is a node AIN at the node. j ;j∈N;

[0067] Node AIN j As a test tap.

[0068] Chips U10 and U4 are external Ethernet transceivers, connected via Ethernet cable;

[0069] Chip U10 and chip U4 are respectively connected to the PCIe interface of the board under test;

[0070] For chip U10, pins 12, 21, and 20 are connected to the DVD drive through their corresponding resistors; pins 15 and 16 are electrically connected to the clock circuit; pins 13, 14, 17, and 18 are connected to the PCIe port through their corresponding capacitors; pin 19 is grounded through capacitor C70 on one side and connected to the DVD drive through resistor R132 on the other side; pin 31 is grounded through resistor R133; pins 25-27 are connected to the LED signal; pins 28 and 29 are electrically connected to the crystal oscillator circuit; pins 11 and 32 are connected to PCIe 3V3 through parallel capacitors C45-47.

[0071] like Figure 2 By properly configuring the IO resources of the embedded board, the effect of IO testing can be achieved. Figure 2 Eight examples of I / O pairing tests are provided. When configuring resources, the possibility of solder bridging during processor soldering should be considered; therefore, adjacent soldered pins should not be selected for I / O pairing tests. I / Os with consistent voltage levels should also be selected for pairing. The driving and sinking current capabilities of the I / Os should be considered. For example, GPIO4_21 and GPIO4_30 have strong driving capabilities, so a 10K resistor R106 is selected as the current-limiting resistor. In the GPIO5_07 and GPIO5_16 group, the driving capability is weaker, so a 1K resistor R112 is selected as the current-limiting resistor.

[0072] During testing, first configure one I / O in each group as an output and the other as an input. Then, output the I / O high and low levels, and test the input I / O. Finally, swap the input and output I / O, configuring the previously output I / O as an input and the previously input I / O as an output, and repeat the test steps.

[0073] The principle of USB testing is as follows: Figure 3, respectively, the two groups of USB signals are converted into serial port signals by conversion chip, the sending pin of serial port 1 is connected to the receiving pin of serial port 2, and the sending pin of serial port 2 is connected to the receiving pin of serial port 1. The first group of USB is configured as a host, responsible for sending data, and the second group of USB is configured as a slave, responsible for receiving data, and the function test is performed by checking the data integrity. Finally, the host and slave roles are exchanged for reverse testing.

[0074] The circuit design is compatible with USB direct measurement. By welding R86 and R87, and welding R57 and R59, the USB HOST can be connected to the USB DEVICE, and the test is performed by judging whether the USB device is successfully mounted under the USB HOST.

[0075] The key test principle is shown in Figure 4 .

[0076] SYS_WARMRESET is a processor reset pin, and F15 GPIO3_13 is an IO. When F15 GPIO3_13 is low, transistor Q1 is not conductive, and SYS_WARMRESET is the default level. When F15 GPIO3_13 outputs high, transistor Q1 is conductive, and SYS_WARMRESET is equivalent to ground at this time, which simulates pressing the reset button. At this time, the system restarts. Write a number in the register of the processor of the board under test, and set the value in the register to increase by one when starting again. If it is greater than the set value, it is determined that the second start is successful, and it can be determined that the reset is successful.

[0077] The PCIE test principle is shown in Figure 5 and Figure 6 .

[0078] The PCIE interface is externally connected to a PCIE-to-Ethernet transceiver, and then two Ethernet are connected together through a network cable. The network performance is tested by flow, and the performance of PCIE can be tested.

[0079] If the embedded board card resource is relatively tight, there is only one PCIE interface, or there are odd number of PCIE devices on the board card, and it is impossible to test two by two, it can be tested by matching other resources. Common solutions, such as matching USB-to-Ethernet transceivers. It can also be tested by matching the original Ethernet transceiver of the embedded board card.

[0080] For special embedded board cards, it can be determined only by testing whether the device is successfully mounted on the PCIE interface, and checking whether the device node exists.

[0081] See Figure 7The voltage value is tested by comparing the theoretically calculated voltage value with the actually tested voltage value after the voltage is divided by configuring the resistance value and connecting the tap of the series resistance to the input of the ADC. AN0, AN1, AN2, AN3, AN4, AN5, AN6 and AN7 in the figure are the taps of the series resistance to be tested, and 8-way ADC is supported to simultaneously test, and if more way ADC resource is needed to test, the number of series resistance can be increased. 1% and higher precision resistance is used for welding to prevent the error of resistance value from affecting the actual voltage division.

[0082] As Figure 11 , the display interface test is shown. HDMI video signal is converted into MIPI_CSI signal. The board card to be tested displays a specific video through HDMI, and after the video is converted into MIPI_CSI signal through U13, the signal is transmitted back to the board card to be tested through the MIPI interface. The test is performed by comparing the output video with the feedback video content.

[0083] The utility model fully describes is in order to disclose more clearly, and for prior art will not enumerate one by one.

[0084] Finally, it should be noted that: the above examples are used to illustrate the technical solutions of the utility model, but not to limit them; although the utility model has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement to part of the technical features; as the person skilled in the art combines the multiple technical solutions of the utility model, it is obvious; these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the utility model examples. The technical contents not described in the utility model are all known technologies.

Claims

1. A fully automated test circuit for embedded board cards, characterized by: The test module is electrically connected with the processor, and the processor is electrically connected with the server in the background; The test module includes an input-output test module, a USB test module, a key test module, a display test interface, an audio test interface, a PCIE test module and / or an ADC test module; The USB signal line is electrically connected with the corresponding port of the conversion chip U5 and U6 at both ends; The input / output testing module includes several current-limiting resistors R. a ; a∈N; in resistor R a Connecting both ends to GPI a The line is connected to the corresponding terminal P. a With end T a ; End P a With end T a IO configuration as test; The USB test module comprises a plurality of USB signal lines, and resistors R are arranged on the USB signal lines b ; In the conversion chip U5, the pins 7 and 8 are connected with VCC in one way and with ground through the parallel capacitors C25 and C26 in the other way, the pins 3 and 29 are connected with ground, and the pin 9 is connected with VCC through the resistor R84 in one way and with ground through the capacitor C27 in the other way; The key test module includes a triode Q1, in which the collector is connected with the reset pin SYS_WARMRESET of the processor, the emitter is connected with ground, the base is connected with ground through the resistor R69 in one way and with F15 GPIO3 through the resistor R67 in the other way as an IO; The collector is connected with ground through the parallel capacitors C15 and C16; The PCIE test module includes the chips U10 and U4; The pin 25 of the conversion chip U5 is connected with the pin 26 of the conversion chip U6 through the resistor R86; The ADC test module comprises several voltage dividing resistors R i , R i+1 connected in series between VCC3V3 and GND i ; there are nodes AIN i+1 at the nodes of adjacent voltage dividing resistors R j ; j e N Node AIN j As test taps.

2. The fully automated test circuit for embedded board cards of claim 1, wherein: The pin 26 of the conversion chip U5 is connected with the pin 25 of the conversion chip U6 through the resistor R87; A group of USB configurations are used as the host to send data, and at least one group of USB configurations are used as the slave to receive data; The USB HOST of the USB test module is connected with the USB DEVICE. When the F15 GPIO3_13 is in a low level state, the triode Q1 is not conductive, and SYS_WARMRESET is in a default level; 3. The fully automated test circuit for embedded board cards of claim 1, wherein: When the F15 GPIO3_13 outputs a high level state, the triode Q1 is conductive, and SYS_WARMRESET is connected with ground. The chips U10 and U4 are external Ethernet transceivers connected through a network cable; 4. The fully automated test circuit for embedded board cards of claim 1, wherein: The chips U10 and U4 are connected with the PCIE interface of the board card to be tested respectively; For the chip U10, the pins 12, 21 and 20 are connected with the DVD through corresponding resistors respectively, the pins 15 and 16 are electrically connected with a clock circuit respectively, the pins 13, 14, 17 and 18 are connected with the PCIE port through corresponding capacitors respectively, the pin 19 is connected with ground through the capacitor C70 in one way and with DVDD through the resistor R132 in the other way, the pin 31 is connected with ground through the resistor R133, the pins 25-27 are connected with LED signals, the pins 28 and 29 are electrically connected with a crystal oscillator circuit, and the pins 11 and 32 are connected with PCIE 3v3 through the parallel capacitors C45-C47. The test module is mounted on a test board, and the board card to be tested is connected to the test board through an adapter board; 5. The fully automatic test circuit for embedded board cards according to any one of claims 1 to 4, characterized in that: The adapter board includes a board card for a board-to-board connector, a board card for a land grid array package connector and a board card for a postage stamp hole connector; The test fixture is used for plugging and installing the board card to be tested on the adapter board. ​

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