Storage control circuit and micro-processing chip

Abstract

The embodiment of the utility model provides a storage control circuit and a micro-processing chip, the storage control circuit comprises a processing module and a storage module, and the storage module comprises a first memory and a second memory; the processing module is respectively connected with the first memory and the second memory; the first memory stores user data; wherein the access speed of the second memory is higher than that of the first memory, and the anti-interference capability of the second memory is lower than that of the first memory; and the processing module is used for controlling the first memory and the second memory, and transferring the user data of the first memory to the second memory after the first power-on. The storage control circuit stores the user data in the first memory in a test packaging stage to protect the data security; in the use stage of the user, the user data are stored in the second memory, the reading speed is high, and the efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuits, in particular to a storage control circuit and a micro-processing chip. BACKGROUND

[0002] Phase-Change Memory (PCM) is a new type of memory that uses phase-change material to realize data storage in the difference of conductive properties between crystalline and amorphous states, and has the advantages of low cost, fast read-write speed, high process compatibility, single-bit variability, etc., and is one of the strong competitors to replace Flash as the new generation of mainstream non-volatile memory.

[0003] However, phase-change memory is not resistant to high temperature, and if the chip wafer test (CP) results, user data and other data are stored in the phase-change memory, once the temperature in the process of chip packaging, welding, etc. exceeds the crystallization temperature of the phase-change material, the phase-change material may change phase, causing the loss of stored data. However, if the above data is stored in a non-volatile memory, for programs that need to read user data multiple times, the slow access speed of the non-volatile memory will result in poor program performance. CONTENT OF THE INVENTION

[0004] The embodiments of the present application provide a storage control circuit and a micro-processing chip to achieve the effect of protecting data security.

[0005] In a first aspect, the embodiments of the present application provide a storage control circuit, comprising a processing module and a storage module, the storage module comprising a first memory and a second memory;

[0006] The processing module is connected with the first memory and the second memory respectively; the first memory stores user data; wherein the access speed of the second memory is faster than that of the first memory, and the anti-interference ability of the second memory is lower than that of the first memory.

[0007] The processing module is used to control the first memory and the second memory, and to transfer the user data of the first memory to the second memory after the first power-on.

[0008] In the present embodiment, the processing module controls the transfer of the user data of the first memory to the second memory after the first power-on, and the access speed of the second memory is higher than that of the first memory, which can improve the access speed of the user data; the user data is stored in the first memory before the first power-on, which can improve the anti-interference ability of the user data and avoid loss or error.

[0009] In one of the embodiments, the storage control circuit further comprises a verification module connected with the processing module and the storage module.

[0010] The first memory and the second memory each store user data, and the checking module is configured to check the user data in the first memory and the second memory and generate a control signal when the user data in the first memory and the second memory is inconsistent.

[0011] The processing module is configured to transfer the user data in the first memory to the second memory according to the control signal.

[0012] In the embodiment, the checking module checks the data before data transfer, the processing module controls the user data in the first memory to be transferred to the second memory when the user data in the first memory and the second memory is inconsistent, and no data transfer is needed when the user data in the first memory and the second memory is consistent, thereby reducing the frequency of data transfer.

[0013] In one of the embodiments, the storage control circuit further comprises a temperature sensor connected to the processing module.

[0014] The temperature sensor is arranged on the storage control circuit or the second memory and is configured to detect the temperature of the storage control circuit or the second memory and generate a temperature signal.

[0015] The processing module is configured to perform a data transfer operation according to the temperature signal, and the data transfer operation is configured to transfer the user data stored in the first memory to the second memory.

[0016] In one of the embodiments, the processing module is configured to perform the data transfer operation according to the temperature signal, and the data transfer operation comprises:

[0017] When the temperature indicated by the temperature signal is higher than a first preset temperature value, reading the user data in the second memory and writing the user data into the first memory.

[0018] When the temperature indicated by the temperature signal first drops from higher than the first preset temperature value to lower than a second preset temperature value, reading the user data in the first memory and writing the user data into the second memory. In the embodiment, the processing module performs the transfer operation according to the temperature signal, so that the high user data access speed can be maintained when the temperature is normal during the user use stage, and the user data can be protected from loss or error when the temperature is abnormal; the first preset temperature and the second preset temperature can be the same or different, and when the first preset temperature is higher than the second preset temperature, the processing module can be prevented from frequently performing the data transfer operation due to temperature fluctuations.

[0019] In one of the embodiments, the first memory comprises a first storage area, a second storage area and a third storage area.

[0020] The first storage area is configured to store system parameters, the second storage area is configured to store system parameter flag bits corresponding to the system parameters, and the third storage area is configured to store user data.

[0021] The system parameter flag is used to reflect the state of the system parameter.

[0022] In one embodiment, the circuit further comprises a system configuration module, the system configuration module comprising a system parameter configuration register group and a system parameter state register group.

[0023] The system parameter state register group is used to read the system parameter flag in the first memory, and if the system parameter flag is valid, the system parameter state register group sends a configuration instruction to the system parameter configuration register group.

[0024] The system parameter configuration register group is used to read the system parameter corresponding to the system parameter flag in the first memory according to the configuration instruction, and write the system parameter into the system parameter configuration register group, thereby completing the system parameter configuration.

[0025] In one embodiment, the first storage area comprises N system parameter flags, and the second storage area comprises N system parameters.

[0026] The system parameter state register group reads the next system parameter flag after confirming that the system parameter flag is invalid or the system parameter configuration register group completes the system parameter configuration of the current system parameter flag.

[0027] In this embodiment, when the system parameter state register group confirms that the system parameter flag is invalid, the system parameter state register group skips the system configuration of the current system parameter, thereby accelerating the system configuration speed.

[0028] In one embodiment, the processing module has a conditional interface, the conditional interface being used to receive a condition signal, and the processing module being used to transfer the user data of the first memory to the second memory according to the condition signal.

[0029] In one embodiment, the first memory is a non-volatile memory, and the second memory is a phase change memory.

[0030] In a second aspect, the embodiments of the present application provide a micro processing chip, comprising the storage control circuit as any of the above.

[0031] The storage control circuit and the micro processing chip provided by the embodiment of the application, the storage control circuit comprises a processing module and a storage module, the storage module comprises a first storage and a second storage; the processing module is connected with the first storage and the second storage respectively; the first storage stores user data; wherein the access speed of the second storage is faster than that of the first storage, and the anti-interference capability of the second storage is lower than that of the first storage; the processing module is used for controlling the first storage and the second storage, and is used for transferring the user data of the first storage to the second storage after first power-on. The storage control circuit stores the user data in the first storage in the test packaging stage, and protects the data safety; in the user use stage, the user data is stored in the second storage, the reading speed is fast, and the efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] The drawings incorporated by reference in the specification and forming a part of the specification, show embodiments consistent with the application, and together with the specification serve to explain the principles of the application.

[0033] Figure 1 The schematic diagram of the storage control circuit provided by the embodiment of the application;

[0034] Figure 2 The structural schematic diagram of the storage control circuit provided by the embodiment of the application;

[0035] Figure 3 The structural schematic diagram of the first storage provided by the embodiment of the application;

[0036] Figure 4 The structural schematic diagram of the system configuration module provided by the embodiment of the application;

[0037] Figure 5 The schematic diagram of the system parameter and the system parameter flag bit provided by the embodiment of the application.

[0038] Reference signs:

[0039] 110, processing module; 120, storage module; 130, check module; 140, system configuration module; 121, first storage; 122, second storage; 141, system parameter state register group; 142, system parameter configuration register group; 1211, first storage area; 1212, second storage area; 1213, third storage area.

[0040] Through the above drawings, the specific embodiments of the application have been shown, and more detailed description will be given hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the application by any means, but to illustrate the concept of the application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0041] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, like reference numerals refer to like elements, unless the context clearly dictates otherwise. The following description of exemplary embodiments is not representative of all possible embodiments consistent with the present application. Instead, it is merely an example of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.

[0042] Glossary in this application:

[0043] MTP (Multi-Time Programmable Memory): allows multiple programming and erasing operations, suitable for applications that require multiple updates of data; MTP memory usually has good high-temperature resistance and data retention capability.

[0044] OTP (One-Time Programmable Memory): can only be programmed once, and the data cannot be changed thereafter. This type of memory is suitable for applications that require permanent storage of data, and has high stability and high-temperature resistance.

[0045] Due to manufacturing process deviations, low dropout regulators (LDO), RC oscillators, sensors and other circuits need to be calibrated during wafer testing and the calibration values are stored in the on-chip non-volatile memory for use in the chip system initialization stage. In addition, user data is also written into the on-chip non-volatile memory for user use. If the above data is stored in flash memory, for programs that need to read user data multiple times, the slow access speed of flash memory will result in poor program performance. The read and write performance of phase change memory is better than that of flash memory. However, phase change memory is written 0 or 1 by causing different temperature changes through electrical pulses. If these data are stored in phase change memory, after high-temperature processes such as packaging and soldering, data loss may occur.

[0046] The storage control circuit provided in the present application includes a processing module and a storage module, the storage module includes a first memory and a second memory; the processing module is connected with the first memory and the second memory respectively; the first memory stores user data; wherein the access speed of the second memory is faster than that of the first memory, and the anti-interference ability of the second memory is lower than that of the first memory; the processing module is used for controlling the first memory and the second memory, and transferring the user data of the first memory to the second memory after the first power-on. The storage control circuit stores user data in the first memory during the test packaging stage, and protects the data safety; in the user use stage, the user data is stored in the second memory, and the reading speed is fast, which improves the efficiency.

[0047] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes can not be described again in some examples. The embodiments of the present application will be described below with reference to the drawings.

[0048] As shown in Figure 1 Figure 1 A schematic diagram of a storage control circuit provided by an embodiment of the present application is shown, the storage control circuit comprising a processing module 110 and a storage module 120, the storage module 120 comprising a first storage 121 and a second storage 122; the processing module 110 is connected with the first storage 121 and the second storage 122 respectively; the first storage 121 stores user data; wherein the access speed of the second storage 122 is faster than that of the first storage 121, and the anti-interference ability of the second storage 122 is lower than that of the first storage 121; the processing module 110 is used to control the first storage 121 and the second storage 122, and to transfer the user data of the first storage 121 to the second storage 122 after the first power-on.

[0049] Specifically, the first storage 121 has a higher anti-interference ability and is suitable for long-term and stable data storage, but the access speed is relatively slow, and the second storage 122 has a faster access speed and is suitable for operations requiring fast reading and writing. However, the anti-interference ability of the second storage is low and is not suitable for use in extreme environments, for example, high temperature in the present application. If the user data is stored in the second storage 122, it needs to go through high-temperature processes such as packaging and welding during the test packaging stage, which may cause the user data to be lost, so the user data is stored in the first storage during the test packaging stage, and during the user use stage, the processing module 110 copies or transfers the user data in the first storage 121 to the second storage 122 after the first power-on, so as to ensure that the user data can be quickly accessed after the storage control circuit starts, and the response speed is improved. The present application utilizes the performance of the first storage 121 and the second storage 122 to ensure data security and data integrity, and improve the response speed; secondly, only one storage is needed to store user data, saving storage resources.

[0050] In one embodiment, the processing module 110 reads and writes the first storage 121 and the second storage 122 through a system bus.

[0051] In one embodiment, the processing module 110 has a conditional interface, the conditional interface is used to receive a condition signal, and the processing module 110 is used to transfer the user data of the first storage to the second storage according to the condition signal.

[0052] ​Specifically, the condition signal can be a power-on signal for the storage control circuit at the first power-on, can be an environmental signal such as a temperature signal, or can be a control signal. The several cases of the condition signal are described in the following embodiment.

[0053] In one embodiment, the first memory 121 is a memory with strong environmental interference resistance, such as a multi-program memory, a one-time programming memory, a flash memory, an erasable programmable read-only memory (EPROM), etc. The second memory 122 is a memory with excellent performance but weak environmental interference resistance, such as a phase change memory.

[0054] In one embodiment, the first memory 121 is a non-volatile memory; and the second memory 122 is a phase change memory.

[0055] In one embodiment, as shown in FIG. 1, Figure 2 Figure 2 FIG. 1 is a structural schematic diagram of a storage control circuit according to an embodiment of the present application. The storage control circuit further includes a verification module 130 connected with the processing module 110 and the storage module 120; the first memory 121 and the second memory 122 each store user data, and the verification module 130 is configured to verify the user data in the first memory 121 and the second memory 122 and generate a control signal when the user data in the first memory 121 and the second memory 122 are inconsistent; and the processing module 110 is configured to transfer the user data in the first memory 121 to the second memory 122 according to the control signal.

[0056] Specifically, the user data is stored in the first memory and the second memory. When the environment is harsh (for example, the temperature is high) or when the harsh environment is maintained for a period of time (for example, the high temperature is maintained for a certain period of time), the verification module 130 first verifies the user data in the first memory 121 and the second memory 122. If the verification results are different, it indicates that the user data in the second memory 122 is lost or incorrect, and the processing module 110 writes the user data in the first memory 121 to the second memory 122. If the verification results are the same, the user data does not need to be written to the second memory 122, thereby reducing unnecessary steps. In addition, if the user data in the first memory 121 and the user data in the second memory 122 are different, the processing module 110 can only write part of the user data to the second memory 122. The part of the user data is the part of the user data that is different between the second memory 122 and the first memory 121, thereby reducing the data processing amount of the processing module 110 and reducing the program occupation of the processing module 110. The embodiment can ensure the data consistency in the memory and prevent data damage or loss.

[0057] ​In one of the embodiments, the storage control circuit further comprises a temperature sensor connected to the processing module 110; the temperature sensor is arranged on the storage control circuit or the second memory 122, and is configured to detect the temperature of the storage control circuit or the second memory 122 and generate a temperature signal; the processing module 110 is configured to perform a data migration operation according to the temperature signal, and the data migration operation comprises transferring user data stored in the first memory to the second memory or transferring user data stored in the second memory to the first memory.

[0058] Specifically, the temperature sensor can be arranged outside the storage control circuit, or can be arranged inside the storage control circuit, and the specific position of the temperature sensor is determined by the actual situation, which is not limited in the present application. When the temperature is too high, the user data is transferred from the second memory to the first memory; when the temperature is relatively low, the user data is transferred from the first memory 121 to the second memory 122; after the user data is written from the first memory to the second memory, the user data stored in the first memory can be cleared, thereby saving storage resources. The present embodiment can accurately ensure the safety of the user data according to the temperature of the second memory 122 or the storage control circuit, and avoid data loss caused by the second memory 122 due to the temperature being too high.

[0059] In one of the embodiments, the processing module 110 is configured to perform a data migration operation according to the temperature signal, comprising: reading the user data in the second memory 122 and writing the user data into the first memory 121 when the temperature represented by the temperature signal is higher than a first preset temperature value; reading the user data in the first memory 121 and writing the user data into the second memory 122 when the temperature represented by the temperature signal first drops from being higher than the first preset temperature value to being lower than a second preset temperature value.

[0060] Specifically, the second memory 122 faces the risk of data loss when its temperature exceeds the first preset temperature value. The first and second preset temperature values ​​can be obtained based on testing conditions or the operating temperature of the second memory 122. The processing module 110 is used to read user data from the second memory 122 and write it into the first memory 121 when the temperature represented by the temperature signal is higher than the first preset temperature value, thus preventing newly stored user data from being damaged due to excessive temperature. When the temperature represented by the temperature signal first drops from above the first preset temperature value to below the second preset temperature value, the processing module 110 reads user data from the first memory 121 and writes it into the second memory 122. At this time, the temperature of the second memory 122 will not cause data loss, and storing user data in the second memory 122 can speed up access and improve efficiency. Optionally, the second preset temperature value can be the same as or lower than the first preset temperature value; when the second preset temperature value is lower than the first preset temperature value, frequent data migration caused by temperature fluctuations can be avoided.

[0061] In one embodiment, the processing module 110 may also control the migration of user data based on user input or other types of sensors.

[0062] In one embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a first memory 121 provided in an embodiment of this application. The first memory 121 includes a first storage area 1211, a second storage area 1212, and a third storage area 1213; the first storage area 1211 is used to store system parameters; the second storage area 1212 is used to store system parameter flag bits corresponding to the system parameters; the third storage area 1213 is used to store user data; the system parameter flag bits are used to reflect the status of the system parameters.

[0063] In one embodiment, the storage control circuit further includes a system configuration module 140, which includes a system parameter status register group 141 and a system parameter configuration register group 142. Figure 4 As shown, Figure 4 This is a schematic diagram of the system configuration module 140 provided in an embodiment of this application. The system parameter status register group 141 is used to read the system parameter flag bit in the first memory 121. If the system parameter flag bit is valid, the system parameter status register group 141 sends a configuration command to the system parameter configuration register group 142. The system parameter configuration register group 142 reads the system parameters corresponding to the system parameter flag bit in the first memory 121 according to the configuration command, and writes the system parameters into the system parameter configuration register group 142 to complete the system parameter configuration.

[0064] Specifically, the system parameters include but are not limited to in-chip circuit calibration parameters, system configuration parameters. The system parameter flag bit indicates whether the corresponding system parameter is valid. The user data refers to the custom parameters used by the user in the user usage stage, including but not limited to user keys, algorithm parameters. In the test packaging stage, the storage control circuit needs to perform circuit calibration test to obtain the required calibration value, such as Figure 5 Figure 5 The schematic diagram of system parameters and system parameter flag bits provided by an embodiment of the present application is shown. The calibration value is written into the specified address of the first storage area 1211 by the system configuration module 140, and the valid flag value is written into the system parameter flag bit address corresponding to the calibration value. After completing the writing operation of all calibration values and system parameter flag bits, the packaging and soldering process is entered. The first memory 121 is a high-temperature-resistant non-volatile memory such as MTP (Multi-Time Programmable Memory) or OTP (One-Time Programmable Memory), which can ensure the stability of data in a high-temperature environment. The storage control circuit enters the user usage stage, and after the first power-on, the system initialization program, i.e., the system parameter configuration, is executed.

[0065] Specifically, after the power-on, the system configuration module 140 reads the system parameters for system configuration. After completing the configuration of the system parameters, the processing module 110 reads the user data in the first memory 121 and writes the user data into the second memory 122.

[0066] In one embodiment, the first storage area 1211 includes N system parameter flag bits, and the second storage area 1212 includes N system parameters; the system parameter state register group 141 reads the next system parameter flag bit after confirming that the system parameter flag bit is invalid or the system parameter configuration register group 142 completes the configuration of the system parameter corresponding to the system parameter flag bit.

[0067] Please refer to Figure 5 ​The first storage area 1211 has n 32-bit system parameters, the second storage area 1212 has n 32-bit system parameter flag bits, and the third storage area 1213 has m+1 user data. The system parameter 1 flag bit address is 0x000, the system parameter 1 address is 0x004, the system parameter n flag bit is 0x000+8(n-1), the system parameter n address is 0x000+8(n-1)+4, the user data 1 address is 0x000+8n, the user data 2 address is 0x000+8n+4, the user data m address is 0x000+8(n+m / 2-1 / 2), and the user data m+1 address is 0x000+8(n+m / 2). The specific working logic of the system parameter configuration is as follows. After power-on, when the first storage area 1211 is in an idle state, the system parameter 1 status register reads the 32-bit system parameter 1 flag bit from the address 0x000 of the first storage area 1211. If the system parameter 1 flag bit is in a valid state, the system parameter 1 status register sends a configuration instruction to the system parameter 1 configuration register, the system parameter 1 configuration register reads the 32-bit system parameter 1 from the address 0x004 of the first storage area 1211 according to the configuration instruction, and the system configuration module 140 performs system configuration according to the system parameter 1 in the system parameter 1 configuration register. After the system parameter 1 completes the system configuration, the system parameter 2 system configuration process is entered. If the system parameter 1 flag bit is in an invalid state, the system parameter 1 configuration register reads the system parameter 1 and the subsequent system configuration process are skipped, and the system parameter 2 system configuration process is directly entered. In this way, n system parameter system configurations are completed, then the processing module 110 reads the user data 1 from the third storage area 1213 and writes it into the second storage 122, and after sequentially reading m+1 user data from the third storage area 1213 and writing them into the second storage 122, the user program is executed.

[0068] In the embodiment, if the system parameter flag bit is invalid, the system parameter that does not need to be configured can be directly skipped, and the system parameter configuration speed is accelerated.

[0069] The embodiment of the application provides a micro-processing chip, which comprises the storage control circuit as any of the above.

[0070] The division of the modules is only a logical function division, and in actual implementation, another division manner can be used, for example, a plurality of modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed modules can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0071] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e. may be located in one place, or may also be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0072] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0073] Finally, it should be noted that: other embodiments of the present application will be easily conceived by those skilled in the art after considering the specification and practicing the schemes disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application that follow the general principles of the present application and include known or customary technical means in the art not disclosed by the present application, and is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is only limited by the appended claims.

Claims

1. A memory control circuit, characterized by comprising: The storage control circuit comprises a processing module and a storage module, and the storage module comprises a first memory and a second memory; The processing module is connected with the first memory and the second memory respectively; the first memory stores user data; the second memory has a faster access speed than the first memory, and the anti-interference capability of the second memory is lower than that of the first memory; The processing module is configured to control the first memory and the second memory, and to transfer the user data of the first memory to the second memory after first power-on.

2. The storage control circuit according to claim 1, characterized by The storage control circuit further comprises a verification module connected with the processing module and the storage module; The first memory and the second memory both store user data, and the verification module is configured to verify the user data in the first memory and the second memory, and to generate a control signal when the user data in the first memory and the second memory are inconsistent; The processing module is configured to transfer the user data of the first memory to the second memory according to the control signal.

3. The storage control circuit of claim 1, wherein, The storage control circuit further comprises a temperature sensor connected with the processing module; The temperature sensor is arranged on the storage control circuit or the second memory, and is configured to detect the temperature of the storage control circuit or the second memory and generate a temperature signal; The processing module is configured to perform a data migration operation according to the temperature signal, and the data migration operation comprises transferring the user data stored in the first memory to the second memory or transferring the user data stored in the second memory to the first memory.

4. The storage control circuit according to claim 3, characterized by The processing module is configured to perform a data migration operation according to the temperature signal, and the data migration operation comprises: When the temperature represented by the temperature signal is higher than a first preset temperature value, reading the user data in the second memory and writing the user data into the first memory; When the temperature represented by the temperature signal first drops from higher than the first preset temperature value to lower than a second preset temperature value, reading the user data in the first memory and writing the user data into the second memory.

5. The storage control circuit of claim 1, wherein, The first memory comprises a first storage area, a second storage area and a third storage area; The first storage area is configured to store system parameters; the second storage area is configured to store system parameter flag bits corresponding to the system parameters; and the third storage area is configured to store the user data; The system parameter flag bits are configured to reflect the state of the system parameters.

6. The storage control circuit of claim 5, wherein, The circuit further comprises a system configuration module, and the system configuration module comprises a system parameter configuration register group and a system parameter state register group; The system parameter state register group is configured to read the system parameter flag bits in the first memory, and to send a configuration instruction to the system parameter configuration register group if the system parameter flag bits are valid. The system parameter configuration register group reads the system parameter corresponding to the system parameter flag bit in the first memory according to the configuration instruction, and writes the system parameter into the system parameter configuration register group, thereby completing system parameter configuration.

7. The storage control circuit of claim 6, wherein, The first storage area includes N system parameter flag bits, and the second storage area includes N system parameters. The system parameter state register group reads the next system parameter flag bit after confirming that the system parameter flag bit is invalid or the system parameter configuration register group completes system parameter configuration corresponding to the current system parameter flag bit.

8. The storage control circuit of claim 1, wherein, The processing module has a condition interface for receiving a condition signal, and the processing module is configured to transfer user data of the first memory to the second memory according to the condition signal.

9. The storage control circuit of claim 1, wherein, The first memory is a non-volatile memory, and the second memory is a phase change memory.

10. A microprocessing chip, characterized by A storage control circuit comprising any one of claims 1-9.

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