Simple bidirectional time-delay high-frequency filter circuit
By using a simple bidirectional delay high-frequency filter circuit and controlling the charging and discharging of the filter capacitor with a current mirror group, the problems of high-frequency signal accumulation and increased circuit size in integrated circuits are solved, achieving efficient high-frequency signal filtering and cost savings.
Patent Information
- Application Number
- CN202520038715.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-08
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2035-01-08
AI Technical Summary
In existing integrated circuits, unipolar RC filter circuits cause high-frequency signal accumulation and output. Unidirectional high-frequency filter circuits can only filter out one type of pulse wave, and multiple filter circuits connected in series increase the circuit size and cost.
A simple bidirectional delay high-frequency filter circuit is adopted. The charging and discharging of the filter capacitor is controlled by a current mirror group. The high-frequency signal is filtered bidirectionally by an inverter to avoid signal accumulation. The current mirror group is connected to the initialization control tube to achieve the simplicity and small area of the circuit.
It effectively filters out high-frequency glitches in digital signals, avoids signal accumulation and output, and saves integrated circuit area and cost.
Smart Images
Figure CN223809759U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of integrated circuit, especially a simple bidirectional delay high frequency filter circuit. BACKGROUND
[0002] In integrated circuits, it is often necessary to monitor the change of some signal voltage (compared with a reference voltage) by a comparator, when the monitored signal changes to be close to the reference voltage, because of signal fluctuation, power fluctuation, circuit noise, reference voltage fluctuation and other signal interference, the comparator will output high frequency noise, which can easily cause system misjudgment and abnormality. Some problems of the prior art:
[0003] (1) Single pole RC filter circuit, continuous high frequency signal will accumulate output, which can cause poor filtering effect and error signal;
[0004] (2) Unidirectional high frequency filter circuit, which can only filter high pulse wave or low pulse wave;
[0005] (3) Two unidirectional high frequency filter circuits are connected in series, which increases the circuit size and the area cost of integrated circuits.
[0006] Therefore, a simple circuit is needed to filter out high frequency signals in digital signals, so that the monitoring signal voltage result can be accurately transmitted to the system, while saving cost. INVENTION CONTENTS
[0007] In view of the above problems existing in the field of integrated circuits, the utility model provides a simple bidirectional delay high frequency filter circuit, which is used for filtering out high frequency signals in digital signals. in When the high and low level pulse changes and the change state is maintained, the filter capacitor is charged or discharged by the current mirror group, so as to control the voltage signal of the input inverter, effectively filter out the high frequency burr interference signal in the digital signal, and the high frequency signal cannot be accumulated and output.
[0008] To achieve the above purpose, the embodiments of the utility model adopt the following technical scheme:
[0009] A simple bidirectional delay high frequency filter circuit, comprising an inverter, an internal circuit, a filter capacitor and an initialization control tube, and being provided with an input voltage V in , an output voltage V out , a power voltage V dd and a reset signal, the input end of the internal circuit is connected with the input voltage V in , the output end is connected with the filter capacitor and the input end of the inverter, the output end of the inverter is connected with an output stage, and the output stage is connected with the output voltage V outThe initialization control tube is connected with the internal circuit and inputs a reset signal, and the simple high-frequency filter circuit with bidirectional delay further comprises a current mirror group connected with the power supply voltage V dd and the internal circuit and the initialization control tube, and the current mirror group comprises a first current mirror and a second current mirror, the first current mirror controls charging of the filter capacitor, and the second current mirror controls discharging of the filter capacitor.
[0010] According to an aspect of the present application, the first current mirror comprises a first PMOS tube and a second PMOS tube, the gate and the drain of the first PMOS tube are connected, the drain of the first PMOS tube is connected with a first current source, the source is connected with the power supply voltage V dd , the gate is connected with the gate of the second PMOS tube, the other end of the first current source is grounded, the source of the second PMOS tube is connected with the power supply voltage V dd , and the drain is connected with the initialization control tube, the first PMOS tube and the second PMOS tube both work in the saturation region, and the second PMOS tube is arranged as a current source.
[0011] According to an aspect of the present application, the second current mirror comprises a first NMOS tube and a second NMOS tube, the gate and the drain of the first NMOS tube are connected, the drain of the first NMOS tube is connected with a second current source, the source is grounded, the gate is connected with the gate of the second NMOS tube, the other end of the second current source is connected with the power supply voltage V dd , the source of the second NMOS tube is grounded, and the drain is connected with the internal circuit, the first NMOS tube and the second NMOS tube both work in the saturation region, and the second NMOS tube is arranged as a current sink.
[0012] According to an aspect of the present application, the initialization control tube comprises a third PMOS tube and a fourth NMOS tube, the gate of the third PMOS tube is connected with the reset signal, the source is connected with the drain of the second PMOS tube, and the drain is connected with the internal circuit; the gate of the fourth NMOS tube is connected with the reset signal, the source is grounded, and the drain is connected with the input end of the inverter.
[0013] According to an aspect of the present application, the internal circuit comprises a first filter unit and a second filter unit, the first filter unit comprises a fourth PMOS tube and a third NMOS tube, the gate of the fourth PMOS tube is connected with the input voltage V in , the source is connected with the drain of the third PMOS tube, and the drain is connected with the input end of the inverter; the gate of the third NMOS tube is connected with the input voltage V in , the source is connected with the drain of the second NMOS tube, and the drain is connected with the input end of the inverter.
[0014] According to one aspect of the utility model, the second filter unit includes fifth PMOS tube, sixth PMOS tube, fifth NMOS tube and sixth NMOS tube, the source of fifth PMOS tube is accessed power supply voltage V dd , the grid of fifth PMOS tube is accessed the output end of inverter, the drain of fifth PMOS tube is accessed the source of sixth PMOS tube, the grid of sixth PMOS tube is accessed input voltage V in , the drain of sixth PMOS tube is accessed the input end of inverter, the source of fifth NMOS tube is grounded, the grid of fifth NMOS tube is accessed the output end of inverter, the drain of fifth NMOS tube is accessed the source of sixth NMOS tube, the grid of sixth NMOS tube is accessed input voltage V in , the drain of sixth NMOS tube is accessed the input end of inverter.
[0015] According to one aspect of the utility model, when the reset signal is high level, third PMOS tube is disconnected, fourth NMOS tube is turned on, the input end voltage signal of inverter is low level, the output end voltage signal is high level, fifth PMOS tube is disconnected, fifth NMOS tube is turned on, and output voltage V out Is high level.
[0016] According to one aspect of the utility model, when the reset signal is low level, third PMOS tube is turned on, fourth NMOS tube is disconnected, and the simple bidirectional delay high-frequency filter circuit is enabled.
[0017] According to one aspect of the utility model, when the input voltage V in Changes from high level to low level and keeps, fourth PMOS tube is turned on, third NMOS tube is disconnected, sixth PMOS tube is turned on, sixth NMOS tube is disconnected, second PMOS tube is charged as current source to filter capacitor, the input end voltage signal of inverter reaches the flip threshold value, and is flipped from low level to high level, and the output end voltage of inverter becomes low level, fifth NMOS tube is disconnected, fifth PMOS tube is turned on, and output voltage V out Changes to low level.
[0018] According to one aspect of the utility model, when the input voltage V in Changes from low level to high level and keeps, fourth PMOS tube is disconnected, third NMOS tube is turned on, sixth PMOS tube is disconnected, sixth NMOS tube is turned on, and second NMOS tube is discharged as current leakage to filter capacitor, the input end voltage signal of inverter reaches the flip threshold value, and is flipped from high level to low level, and the output end voltage of inverter becomes high level, fifth NMOS tube is turned on, fifth PMOS tube is disconnected, and output voltage V out Changes to high level.
[0019] The utility model implementation's advantage: through the current mirror group access power supply voltage V ddand is connected with internal circuit and initialization control tube, input voltage V in When high and low level pulse changes and keeps the change state, the filter capacitor is charged or discharged by the current mirror group, so that the voltage signal of the input inverter reaches the flip threshold, thereby controlling the voltage signal of the output end of the inverter, through the bidirectional high-frequency filter circuit, the high-frequency burr interference signal in the digital signal is effectively filtered out, the high-frequency signal cannot be accumulated and output, the circuit is simple, only one capacitor, the integrated circuit layout area is small, and cost is saved. BRIEF DESCRIPTION OF DRAWINGS
[0020] In order to more clearly illustrate the technical scheme in the embodiments of the utility model, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained by those skilled in the art without creative labor on the premise of the drawings.
[0021] Figure 1 The circuit structure diagram of the simple bidirectional delay high-frequency filter circuit is described in the utility model.
[0022] Figure 2 The waveform comparison diagram of the reset signal, input voltage, inverter input end voltage signal and output voltage in the simple bidirectional delay high-frequency filter circuit is described in the utility model. DETAILED DESCRIPTION
[0023] The technical scheme in the embodiments of the utility model will be clearly and completely described in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only some embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the utility model.
[0024] As Figure 1 shown, a simple bidirectional delay high-frequency filter circuit includes an inverter U1, an internal circuit, a filter capacitor C0 and an initialization control tube. The circuit is filtered by the filter capacitor C0, and is provided with an input voltage V in , an output voltage V out , a power supply voltage V dd and a reset signal RESETB. The input end of the internal circuit is connected with the input voltage V in , and the output end is connected with the input end of the inverter U1. The output end of the inverter U1 is connected with an output stage U2, and the output stage U2 outputs V out, the initialization control tube is connected with the internal circuit and accesses the reset signal RESETB, and initialization of the internal circuit is controlled through the reset signal RESETB. The simple bidirectional delay high-frequency filter circuit further comprises a current mirror group, the current mirror group accesses a power supply voltage V dd , and is connected with the internal circuit and the initialization control tube, and an input voltage V in , when high and low level pulse changes and the changed state is maintained, the current mirror group charges or discharges the filter capacitor C0, so that the voltage signal U 1-i of the input end of the inverter U1 reaches the flip threshold, thereby controlling the voltage signal U 1-o of the output end of the inverter U1.
[0025] The first current mirror comprises a first PMOS tube PM1 and a second PMOS tube PM2, the gate and the drain of the PM1 are interconnected, the drain of the PM1 is connected with a first current source I1, the source is connected with a power supply voltage V dd , and the gate is connected with the gate of the PM2, the other end of the first current source I1 is connected with the ground; the source of the PM2 is connected with the power supply voltage V dd , and the drain is connected with the initialization control tube, the PM1 and the PM2 both work in the saturation region, and the PM2 is set as a current source. The second current mirror comprises a first NMOS tube NM1 and a second NMOS tube NM2, the gate and the drain of the NM1 are interconnected, the drain of the NM1 is connected with a second current source I2, the source is connected with the ground, and the gate is connected with the gate of the NM2, the other end of the second current source I2 is connected with the power supply voltage V dd , and the source of the NM2 is connected with the ground, and the drain is connected with the internal circuit, the NM1 and the NM2 both work in the saturation region, and the NM2 is set as a current leakage.
[0026] The initialization control tube comprises a third PMOS tube PM3 and a fourth NMOS tube NM4. The gate of the PM3 is connected with the reset signal RESETB, the source is connected with the drain of the PM2, and the drain is connected with the internal circuit; the gate of the NM4 is connected with the reset signal RESETB, the source is connected with the ground, and the drain is connected with the input end of the inverter U1.
[0027] The internal circuit comprises a first filter unit and a second filter unit, the first filter unit comprises a fourth PMOS tube PM4 and a third NMOS tube NM3, the gate of the PM4 is connected with an input voltage V in , the source is connected with the drain of the PM3, and the drain is connected with the input end of the inverter U1; the gate of the NM3 is connected with the input voltage V in, the source of the NM2 is connected to the drain of the NM2, the drain is connected to the input of the inverter U1; the positive of the filter capacitor CO is connected to the input of the inverter U1, the negative is connected to the ground. The second filter unit comprises a fifth PMOS tube PM5, a sixth PMOS tube PM6, a fifth NMOS tube NM5 and a sixth NMOS tube NM6, the source of the PM5 is connected to the power supply voltage V dd , the gate is connected to the output of the inverter U1, the drain is connected to the source of the PM6; the gate of the PM6 is connected to the input voltage V in , the drain is connected to the input of the inverter U1; the source of the NM5 is connected to the ground, the gate is connected to the output of the inverter U1, the drain is connected to the source of the NM6; the gate of the NM6 is connected to the input voltage V in , the drain is connected to the input of the inverter U1.
[0028] As shown in Figure 2 , at the beginning, the reset signal RESETB is high, PM3 is off, NM4 is on, the input voltage signal U 1-i of the U1 is low, the output voltage signal U 1-o is high, PM5 is off, NM5 is on, the output voltage V out is high. When the reset signal RESETB becomes low, PM3 is on, NM4 is off, initialization is performed, and the circuit is enabled. When the input voltage V in is high, PM6 is off, NM6 is on, U 1-i is low through NM6 and NM5, and the initial state is maintained.
[0029] When the input voltage V in starts to input a low level pulse from high level, PM4 is on, NM3 is off, PM6 is on, and NM6 is off. At this time, only the current source PM2 charges CO, and U 1-i correspondingly generates an upward triangular ramp. If the input voltage V in inputs a low level pulse for a short time, the amplitude of U 1-i does not reach the flip threshold of U1, and the output U 1-o of U1 is high. When the input voltage V in returns to high level, NM6 resumes conduction, U 1-i is low through NM6 and NM5, and the output voltage V out still remains high. If the input voltage V in continues to input a low level pulse, the low level time is long, the amplitude of U 1-i reaches the flip threshold of U1, and the output U 1-o of U1 is low, NM5 is off, PM5 is on, U 1-i is high through PM6 and PM5, and the output voltage Vout becomes low.
[0030] When the input voltage V in When a high level pulse is input from low level, NM3 is turned on, PM4 is turned off, NM6 is turned on, PM6 is turned off, at this time, the current source NM2 discharges C0, U 1-i A downward triangular slope is generated correspondingly. in The input high level pulse is short, U 1-i The voltage amplitude does not reach the flip threshold of U1, U1 outputs U 1-o is low, when the input voltage V in When it returns to low level, PM6 is turned on again, U 1-i Through PM6, PM5, the output voltage V out is still kept low. When the input voltage V in The input high level pulse is kept, the high level time is long, U 1-i The voltage amplitude reaches the flip threshold of U1, U1 outputs U 1-o is high, PM5 is turned off, NM5 is turned on, U 1-i Through NM5, NM6, the output voltage V out becomes high.
[0031] The utility model discloses the advantages of implementation: through the current mirror group access power voltage V dd And be connected with internal circuit and initialization control pipe, when the input voltage V in Carry out high low level pulse change and keep the change state, through the current mirror group to filter capacitor C0 charge or discharge, make the voltage signal of input inverter reach flip threshold, thereby control the voltage signal of inverter output end, through the high frequency filter circuit of two -way, effectively filter the high frequency burr interference signal in digital signal, high frequency signal can not accumulate output, the circuit is simple, only one capacitor, realize the integrated circuit layout area small, save the cost.
[0032] The above, only for the specific implementation mode of the utility model, but the protection scope of the utility model is not limited to this, any skilled person in the art in the utility model disclosed technical range can easily think of the change or replacement, all should be covered in the protection scope of the utility model. Therefore, the protection scope of the utility model should be accurate with the protection scope of the claim.
Claims
1. A simple bidirectional delay high-frequency filter circuit, comprising an inverter, internal circuitry, a filter capacitor, and an initialization control transistor, and equipped with an input voltage V. in Output voltage V out Power supply voltage V dd And a reset signal, the input terminal of the internal circuit is connected to the input voltage V. in The output terminal is connected to the filter capacitor and the input terminal of the inverter. The output terminal of the inverter is connected to the output stage, and the output stage outputs the voltage V. out The initialization control transistor is connected to the internal circuit and receives a reset signal, characterized in that... The concise bidirectional delay high-frequency filter circuit further comprises a current mirror group connected to a power supply voltage V dd and connected to internal circuits and an initialization control tube, the current mirror group comprising a first current mirror and a second current mirror, the first current mirror controlling charging of the filter capacitor, and the second current mirror controlling discharging of the filter capacitor.
2. A compact high-frequency filter circuit with bi-directional time delay according to claim 1, characterized in that The first current mirror comprises a first PMOS tube and a second PMOS tube, the gate and the drain of the first PMOS tube are interconnected, the drain of the first PMOS tube is connected to a first current source, the source is connected to a power supply voltage V dd , the gate is connected to the gate of the second PMOS tube, the other end of the first current source is grounded, the source of the second PMOS tube is connected to a power supply voltage V dd , the drain is connected to the initialization control tube, and the first PMOS tube and the second PMOS tube both work in the saturation region, wherein the second PMOS tube is set as a current source.
3. A compact bidirectional time-delay high-frequency filter circuit according to claim 2, characterized in that The second current mirror comprises a first NMOS transistor and a second NMOS transistor, the gate and the drain of the first NMOS transistor are interconnected, the drain of the first NMOS transistor is connected to a second current source, the source is connected to ground, and the gate is connected to the gate of the second NMOS transistor, the other end of the second current source is connected to a power supply voltage V dd , the source of the second NMOS transistor is connected to ground, and the drain is connected to the internal circuit, and the first NMOS transistor and the second NMOS transistor both work in the saturation region, wherein the second NMOS transistor is set as a current leakage.
4. A compact bidirectional time-delay high-frequency filter circuit according to claim 3, characterized in that The initialization control tube comprises a third PMOS tube and a fourth NMOS tube, a gate of the third PMOS tube is connected with a reset signal, a source of the third PMOS tube is connected with a drain of the second PMOS tube, and a drain of the third PMOS tube is connected with the internal circuit; a gate of the fourth NMOS tube is connected with the reset signal, a source of the fourth NMOS tube is connected with the ground, and a drain of the fourth NMOS tube is connected with an input end of the inverter.
5. A compact bidirectional time-delay high-frequency filter circuit according to claim 4, characterized in that The internal circuit comprises a first filter unit and a second filter unit, the first filter unit comprises a fourth PMOS tube and a third NMOS tube, the gate of the fourth PMOS tube is connected to an input voltage V in , the source is connected to the drain of the third PMOS tube, and the drain is connected to the input end of the inverter; the gate of the third NMOS tube is connected to an input voltage V in , the source is connected to the drain of the second NMOS tube, and the drain is connected to the input end of the inverter.
6. A compact bidirectional time-delay high-frequency filter circuit according to claim 5, characterized in that The second filter unit comprises a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube, the source of the fifth PMOS tube is connected to a power supply voltage V dd , the gate is connected to the output of the inverter, and the drain is connected to the source of the sixth PMOS tube, the gate of the sixth PMOS tube is connected to an input voltage V in , and the drain is connected to the input of the inverter; the source of the fifth NMOS tube is connected to ground, the gate is connected to the output of the inverter, the drain is connected to the source of the sixth NMOS tube, the gate of the sixth NMOS tube is connected to an input voltage V in , and the drain is connected to the input of the inverter.
7. A compact bidirectional time-delay high-frequency filter circuit according to claim 6, characterized in that When the reset signal is high, the third PMOS transistor is off, the fourth NMOS transistor is on, the input voltage signal of the inverter is low, the output voltage signal of the inverter is high, the fifth PMOS transistor is off, and the fifth NMOS transistor is on, so that the output voltage V out is high.
8. A compact bidirectional time-delay high-frequency filter circuit according to claim 7, characterized in that When the reset signal is a low level, the third PMOS tube is turned on, the fourth NMOS tube is turned off, and the simple bidirectional delay high-frequency filter circuit is enabled.
9. A compact bidirectional time-delay high-frequency filter circuit according to any one of claims 1 to 7, characterized in that The input voltage V in When the high level changes to low level and keeps, the fourth PMOS pipe is turned on, the third NMOS pipe is turned off, the sixth PMOS pipe is turned on, the sixth NMOS pipe is turned off, the second PMOS pipe charges the filter capacitor as a current source, the input voltage signal of the inverter reaches the flip threshold value, and flips from low level to high level, the output voltage of the inverter becomes low level, the fifth NMOS pipe is turned off, the fifth PMOS pipe is turned on, and the output voltage V out Changes to low level.
10. A compact bidirectional time-delay high-frequency filter circuit according to any one of claims 1 to 7, characterized in that The input voltage V in When the low level changes to high level and remains, the fourth PMOS tube is disconnected, the third NMOS tube is turned on, the sixth PMOS tube is disconnected, the sixth NMOS tube is turned on, the second NMOS tube discharges the filter capacitor as a current leakage, the input voltage signal of the inverter reaches the flip threshold value, and flips from high level to low level, the output voltage of the inverter becomes high level, the fifth NMOS tube is turned on, the fifth PMOS tube is disconnected, and the output voltage V out becomes high level.