Semiconductor power device

Abstract

The embodiment of the utility model provides a semiconductor power device. The semiconductor power device comprises a substrate, an epitaxial layer, a gate electrode, a gate oxide layer and Schottky metal. The epitaxial layer comprises a well region arranged on one side of the groove; the source region is arranged on one side, facing the top surface of the epitaxial layer, of the well region; the first shielding region is positioned on one side, far away from the trench, of the source region and the well region; the second shielding region is positioned on one side, far away from the source region and the well region, of the groove; the third shielding region is positioned on one side, far away from the source region and the well region, of the second shielding region; the first, second and third shielding areas are arranged at intervals; the epitaxial layer further comprises a first sub-region located between the second shielding region and the third shielding region; the Schottky metal is arranged on the top surface of the epitaxial layer, is respectively connected with the second shielding region, the third shielding region and the first sub-region, and is insulated from the gate electrode. According to the embodiment of the utility model, the gate oxide layer can be protected, the reliability of the device is improved, the reverse recovery speed can be improved, and the switching loss is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor devices, especially relates to a semiconductor power device. BACKGROUND

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a metal-oxide-semiconductor field effect transistor, and silicon carbide MOSFET is more widely used compared with silicon-based devices of the same voltage level due to its high voltage resistance and low on-resistance characteristics. However, compared with silicon, silicon carbide MOSFET has a higher critical breakdown field, so the gate oxide layer in the silicon carbide MOSFET also has a high electric field strength, especially when the device is converted from a planar type to a trench type, the reliability problem caused by the high field strength of the gate oxide layer is dramatically increased. SUMMARY

[0003] Therefore, to overcome at least some of the defects and deficiencies in the prior art, one embodiment of the utility model provides a semiconductor power device which can protect the gate oxide layer, improve device reliability, and improve reverse recovery speed and reduce switching loss.

[0004] The utility model embodiment provides a semiconductor power device, which comprises: a substrate; an epitaxial layer arranged on the substrate, and a concave trench formed on a side of the epitaxial layer away from the top surface of the substrate; the epitaxial layer comprises: a well region arranged on one side of the trench; a source region arranged on a side of the well region facing the top surface of the epitaxial layer; a first shielding region located on a side of the source region and the well region away from the trench; a second shielding region located on a side of the trench away from the source region and the well region; a third shielding region located on a side of the second shielding region away from the source region and the well region; the first shielding region, the second shielding region and the third shielding region are arranged at intervals; the epitaxial layer further comprises a first sub-region between the second shielding region and the third shielding region; a gate electrode arranged in the trench; a gate oxide layer arranged in the trench and isolated between the gate electrode and the epitaxial layer; a Schottky metal arranged on the top surface of the epitaxial layer and connected with the second shielding region, the first sub-region and the third shielding region respectively; and the Schottky metal is insulated from the gate electrode.

[0005] In some embodiments, the Schottky metal includes a main body part and an extension part, the main body part covers the top surface of the epitaxial layer and is connected with the second shielding region, the first sub-region and the third shielding region respectively, the extension part extends from the main body part to the trench along the depth direction of the trench; the extension part is insulated from the gate electrode by the gate oxide layer, and the side of the extension part away from the gate electrode is connected with the second shielding region; the second shielding region further extends to the bottom end of the extension part and is connected with the bottom end of the extension part.

[0006] In some embodiments, the gate oxide layer includes a first sub-layer between the gate electrode and the source region and the well region, and a second sub-layer between the gate electrode and the extension part, the thickness of the second sub-layer is greater than the thickness of the first sub-layer.

[0007] In some embodiments, the distance from the end of the second shielding region close to the substrate to the substrate is less than the distance from the bottom of the trench to the substrate.

[0008] In some embodiments, the end of the second shielding region close to the substrate extends to the side of the bottom of the trench facing the substrate; and the minimum distance between the second shielding region and the first shielding region is less than the minimum distance between the side of the gate electrode away from the first shielding region and the first shielding region.

[0009] In some embodiments, the minimum distance between the second shielding region and the first shielding region is less than the minimum distance between the trench and the first shielding region.

[0010] In some embodiments, the sum of the width of the second shielding region on the side of the trench away from the source region and the well region and the width of the third shielding region is a first width, the width of the first sub-region is a second width, and the ratio of the first width to the second width is 0.7-0.8.

[0011] In some embodiments, an ohmic contact layer is further included, and the ohmic contact layer is arranged between the Schottky metal and the epitaxial layer.

[0012] In some embodiments, the Schottky metal is titanium or an alloy of titanium.

[0013] In some embodiments, a source metal is further included, the source metal is arranged on the side of the epitaxial layer away from the substrate, and the source metal is connected with the Schottky metal, the source region and the first shielding region respectively; the gate electrode is insulated from the source metal.

[0014] The above embodiments of this utility model have at least one or more of the following beneficial effects: By setting shielding regions (including a first shielding region, a second shielding region, and a third shielding region) on both sides of the trench, the distribution of electric field lines is changed when the semiconductor power device is energized, which can protect the gate oxide layer below the gate electrode and improve reliability. Furthermore, it can reduce the gd capacitance (capacitance between the gate and drain), improve the switching speed of the device, and reduce switching losses. Moreover, by setting Schottky metal to be connected to the second shielding region, the first sub-region, and the third shielding region respectively, a Schottky diode structure can be formed on one side of the trench. This fully utilizes the area in the epitaxial layer while integrating a Schottky diode in the trench-type MOSFET device, resulting in faster reverse recovery speed. Attached Figure Description

[0015] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0016] Figure 1 This is a schematic diagram of the structure of a semiconductor power device provided in one embodiment of the present invention.

[0017] Figure 2 A schematic diagram of the structure obtained in one step of the fabrication process of the semiconductor power device provided in this embodiment of the present invention.

[0018] Figure 3 for Figure 2 A schematic diagram of the structure obtained in the next step.

[0019] Figure 4 for Figure 3 A schematic diagram of the structure obtained in the next step.

[0020] Figure 5 for Figure 4 A schematic diagram of the structure obtained in the next step.

[0021] Figure 6 for Figure 5 A schematic diagram of the structure obtained in the next step.

[0022] Figure 7 for Figure 6 A schematic diagram of the structure obtained in the next step.

[0023] Figure 8 for Figure 7 A schematic diagram of the structure obtained in the next step.

[0024] Figure 9 for Figure 8 A schematic diagram of the structure obtained in the next step.

[0025] Figure 10 forFigure 9 A schematic view of the structure obtained after one of the following steps.

[0026] Figure 11 A schematic view of the structure obtained after one of the following steps. Figure 10 A schematic view of the structure obtained after one of the following steps.

[0027] Figure 12 A schematic view of the structure obtained after one of the following steps. Figure 11 A schematic view of the structure obtained after one of the following steps.

[0028] Figure 13 A schematic view of the structure obtained after one of the following steps.

[0029]

Explanation of reference numerals

[0030] 10, substrate; 20, epitaxial layer; 21, drift region; 22, trench; 23, well region; 24, source region; 25, first shield region; 26, second shield region; 27, third shield region; 28, first sub-region; 30, gate electrode; 40, gate oxide layer; 41, first sub-layer; 42, second sub-layer; 50, Schottky metal; 51, main body portion; 52, extension portion; 60, source metal; 70, field oxide layer; 80, ohmic contact layer; 20a, epitaxial layer material; 26a, first implant region; 30a, gate electrode material; 40a, first oxide layer material; 40b, second oxide layer material; 70a, third oxide layer material. DETAILED DESCRIPTION

[0031] In order to make the above objectives, characteristics and advantages of the present application more apparent, clear and understandable, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0032] In order to make the above objectives, characteristics and advantages of the present application more apparent, clear and understandable, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0033] It should be noted that the terms "first", "second", and the like in the description and in the claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the utility model embodiments described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0034] It should also be noted that the division of multiple embodiments in the utility model is only for the convenience of description, and should not constitute a special limitation. The features in various embodiments can be combined and mutually referenced without contradiction.

[0035] As Figure 1 The utility model embodiments provide a semiconductor power device, specifically a trench type MOSFET device, and the semiconductor power device includes a substrate 10, an epitaxial layer 20, a gate electrode 30, a gate oxide layer 40 and a Schottky metal 50.

[0036] The epitaxial layer 20 is provided on the substrate 10, and the epitaxial layer 20 is formed with a concave trench 22 away from the top surface side of the substrate 10. The epitaxial layer 20 includes a well region 23, a source region 24, a first shielding region 25, a second shielding region 26, a third shielding region 27 and a first sub-region 28. The well region 23 is provided on one side of the trench 22. The source region 24 is provided on the top surface side of the well region 23 facing the epitaxial layer 20. The first shielding region 25 is located on the side of the source region 24 and the well region 23 away from the trench 22. The second shielding region 26 is located on the side of the trench 22 away from the source region 24 and the well region 23. The third shielding region 27 is located on the side of the second shielding region 26 away from the source region 24 and the well region 23. The first shielding region 25, the second shielding region 26 and the third shielding region 27 are spaced apart from each other. The first sub-region 28 is located between the second shielding region 26 and the third shielding region 27.

[0037] The gate electrode 30 is provided in the trench 22. The gate oxide layer 40 is provided in the trench 22 and is isolated between the gate electrode 30 and the epitaxial layer 20.

[0038] The Schottky metal 50 is provided on the top surface of the epitaxial layer 20 and is connected with the second shielding region 26, the first sub-region 28 and the third shielding region 27 respectively. The Schottky metal 50 is insulated from the gate electrode 30.

[0039] The semiconductor power device provided by the embodiment is specifically a silicon carbide MOSFET device. The substrate 10 is a silicon carbide substrate. The epitaxial layer 20 further comprises a drift region 21, a well region 23, a source region 24, a first shielding region 25, a second shielding region 26 and a third shielding region 27, which are ion implantation regions obtained by ion implantation in the bulk material of the epitaxial layer 20. The first sub-region 28 has the same material and doping type as the drift region 21. According to whether the doping type of the drift region 21 is N-type doping or P-type doping, the semiconductor power device of the embodiment can be divided into an N-type field effect tube or a P-type field effect tube. For example, when the drift region 21 is N-type doping, the semiconductor power device is an N-type field effect tube. When the drift region 21 is N-type doping, the source region 24 is also N-type doping, and the well region 23 is P-type doping. When the drift region 21 is P-type doping, the source region 24 is also P-type doping, and the well region 23 is N-type doping. Specifically, in the embodiment, the drift region 21 is specifically N-type doping, the source region 24 is an N+ (N-type heavy doping) implantation region, the well region 23 is a P- (P-type light doping) implantation region, and the first shielding region 25, the second shielding region 26 and the third shielding region 27 are P+ (P-type heavy doping) implantation regions.

[0040] The gate electrode 30 is, for example, a poly layer, and the gate oxide layer 40 can be a silicon oxide material. The Schottky metal 50 can be titanium or an alloy of titanium. The Schottky metal 50 and the gate electrode 30 can be insulated by the gate oxide layer 40, or other insulating materials can be additionally provided to achieve insulation. Among them, a drain is further provided on the side of the substrate 10 away from the bottom surface of the epitaxial layer 20, for example, and the electrical property of the drain corresponds to that of the drift region 21. When the drift region 21 is N-type doping, the drain is an N electrode.

[0041] In this embodiment, by setting a first shielding region 25, a second shielding region 26, and a third shielding region 27 respectively, a depletion region can be formed between the shielding regions on both sides of the trench 22 (including the first shielding region 25, the second shielding region 26, and the third shielding region 27) during reverse-biased depletion. This changes the distribution of the electric field lines when the semiconductor power device is powered on, preventing the highest electric field from reaching the bottom of the gate oxide layer 40. This protects the gate oxide layer 40 below the gate electrode 30 and improves reliability. Furthermore, it reduces the gd capacitance (capacitance between the gate and drain), increases the switching speed, and reduces switching losses. Additionally, by connecting the Schottky metal 50 to the second shielding region 26, the first sub-region 28, and the third shielding region 27 respectively, a JBS (Junction Barrier Schottky) type Schottky diode structure can be formed on one side of the trench 22. This fully utilizes the area in the epitaxial layer 20 located on the side of the trench 22 away from the well region 23 and the source region 24, while integrating a Schottky diode in the trench-type MOSFET device allows for faster reverse recovery. Furthermore, in this embodiment, pn-bonded Schottky junctions alternately appear below the Schottky metal 50. When reverse biased, the depletion regions of the pn junctions on both sides of the Schottky contact portion expand in the N-type epitaxial layer and connect to form a pinch-off barrier. This barrier layer can shield the high electric field, reduce the electric field intensity at the metal-semiconductor interface, and suppress the barrier reduction effect and tunneling leakage current caused by the high electric field.

[0042] In some embodiments, this embodiment further includes a source metal 60, which is disposed on the side of the epitaxial layer 20 away from the substrate 10, and is connected to the Schottky metal 50, the source region 24, and the first shielding region 25, respectively. The gate electrode 30 is insulated from the source metal 60. The source metal 60 may be, for example, made of aluminum alloy. (Refer to...) Figure 1 As shown, a field oxide layer 70 is further disposed between the source metal 60 and the gate electrode 30. The field oxide layer 70 may be made of the same material as the gate oxide layer 40. In some embodiments, the field oxide layer 70 and the gate oxide layer 40 can be combined to achieve insulation between the Schottky metal 50 and the gate electrode 30, thereby preventing GS (source and gate) leakage. The field oxide layer 70 has an opening on the Schottky metal 50 through which the source metal 60 is connected to the Schottky metal 50. The width of this opening may be equal to the width between the second shielding region 26 and the third shielding region 27.

[0043] In some embodiments, the Schottky metal 50 includes a main portion 51 and an extension portion 52. The main portion 51 covers the top surface of the epitaxial layer 20 and is connected to the second shielding region 26, the first sub-region 28 and the third shielding region 27, respectively. The extension portion 52 extends from the main portion 51 to the inside of the trench 22 along the depth direction of the trench 22. The extension portion 52 is insulated from the gate electrode 30 by the gate oxide layer 40, and the side of the extension portion 52 facing away from the gate electrode 30 is connected to the second shielding region 26. The end of the second shielding region 26 close to the substrate 10 also extends to the bottom end of the extension portion 52 and is connected to the bottom end of the extension portion 52. In the present embodiment, by extending the extension portion 52 of the Schottky metal 50 into the trench, the gd capacitance can be reduced, and the leakage current can be further reduced. In particular, the end of the second shielding region 26 close to the substrate 10 extends to the bottom end of the extension portion 52 and is connected to the bottom end of the extension portion 52, i.e., the second shielding region 26 also includes a portion extending between the extension portion 52 and the drift region 21, which can increase the contact area of the Schottky metal 50 and the second shielding region 26 while preventing leakage.

[0044] In some embodiments, the gate oxide layer 40 includes a first sub-layer 41 between the gate electrode 30 and the source region 24 and the well region 23, and a second sub-layer 42 between the gate electrode 30 and the extension portion 52. The thickness of the second sub-layer 42 is greater than the thickness of the first sub-layer 41. For example, the thickness of the first sub-layer 41 is 0.04-0.06 microns, and the thickness of the second sub-layer 42 is 0.5-0.7 microns. Specifically, the thickness of the first sub-layer 41 is 0.05 microns, and the thickness of the second sub-layer 42 is 0.5 microns. That is, the first sub-layer 41 is thinner, and the second sub-layer 42 is thicker. That is, the gate oxide between the gate electrode 30 and the well region 23 is thinner, which can ensure a lower on-voltage; and the gate oxide between the gate electrode 30 and the Schottky metal 50 is thicker, which can better prevent leakage.

[0045] In some embodiments, the distance from the end of the second shielding region 26 close to the substrate 10 to the substrate 10 is less than the distance from the bottom of the trench 22 to the substrate 10. That is, the bottom of the second shielding region 26 is lower than the bottom of the trench 22, which can better ensure that the depletion region formed between the second shielding region 26 and the first shielding region 25 protects the gate oxide layer 40. In particular, the bottom of the first shielding region 25 is flush with the bottom of the second shielding region 26, i.e., the distance between the bottom of the first shielding region 25 and the substrate 10 is equal to the distance between the bottom of the second shielding region 26 and the substrate 10. In some embodiments, the bottom of the third shielding region 27 is flush with the bottom of the first shielding region 25 (and / or the second shielding region 26), i.e., the distance between the bottom of the third shielding region 27 and the substrate 10 is equal to the distance between the bottom of the first shielding region 25 (and / or the second shielding region 26) and the substrate 10.

[0046] In some embodiments, the second shielding region 26 extends to the bottom of the trench 22 on one side of the substrate 10 close to one end of the substrate 10, and the minimum distance between the second shielding region 26 and the first shielding region 25 is smaller than the minimum distance between the side of the gate electrode 30 away from the first shielding region 25 and the first shielding region 25. As shown in Figure 1 the minimum distance between the second shielding region 26 and the first shielding region 25, i.e. the distance between the rightmost edge of the second shielding region 26 and the leftmost edge of the first shielding region 25, and the maximum distance between the gate electrode 30 and the first shielding region 25, i.e. the distance between the leftmost edge of the gate electrode 30 and the leftmost edge of the first shielding region 25. That is, the second shielding region 26 extends at least partially under the gate electrode 30, which can improve the protection effect on the bottom of the gate oxide layer 40.

[0047] In some embodiments, the minimum distance between the second shielding region 26 and the first shielding region 25 is smaller than the minimum distance between the trench 22 and the first shielding region 25. As shown in Figure 1 the orientation shown in the figure, i.e. the distance between the rightmost edge of the second shielding region 26 and the leftmost edge of the first shielding region 25 is smaller than the distance between the rightmost edge of the trench 22 and the leftmost edge of the first shielding region 25. That is, the portion of the second shielding region 26 extending to the bottom of the trench 22 does not exceed the side of the trench 22 close to the first shielding region 25, so that the second shielding region 26 and the first shielding region 25 maintain a proper distance, preventing the problem of excessive current density caused by the two being too close.

[0048] In some embodiments, the width of the second shielding region 26 on the side of the trench 22 away from the source region 24 and the well region 23 is equal to the width of the third shielding region 27, and the width of the first sub-region 28 is a second width, and the ratio of the first width to the second width is 0.7-0.8. The width of the second shielding region 26 on the side of the trench 22 away from the source region 24 and the well region 23 is shown as D1 in Figure 1 the figure, the width of the third shielding region 27 is shown as D2 in Figure 1 the figure, and the first width is the sum of D1 and D2. The width of the first sub-region 28, i.e. the second width, i.e. the spacing distance between the second shielding region 26 and the third shielding region 27, is shown as D3 in Figure 1 the figure. That is, (D1+D2) / D3=0.7-0.8. In some specific embodiments, the ratio of the first width to the second width is 3:4, and the range of the ratio of the first width to the second width can ensure better protection effect on the gate oxide layer 40 while ensuring better function of the Schottky diode formed, so as to obtain a proper overall performance.

[0049] In some embodiments, referring to Figure 13The power semiconductor device provided in this embodiment also includes an ohmic contact layer 80, which is disposed between the Schottky metal 50 and the epitaxial layer 20. The ohmic contact layer 80 can be made of nickel or a nickel alloy to achieve good conductivity between the Schottky metal 50 and the second shielding region 26, the first sub-region 28 and the third shielding region 27.

[0050] The semiconductor power device provided in the above embodiments of this utility model can be obtained through the following process.

[0051] Step S1: Grow an epitaxial layer material 20a on substrate 10. After step S1, the desired result is obtained. Figure 2 The structure shown.

[0052] Step S2: Ion implantation is performed on the epitaxial layer material 20a to form a well region 23, a source region 24, a first shielding region 25, a first implantation region 26a, and a third shielding region 27. After step S2 is completed, the result is as follows: Figure 3 The structure shown.

[0053] Step S3: A trench 22 is formed on the top of the epitaxial material layer 20a. The portion of the first injection region 26a located in the area of ​​the trench 22 is removed to form the second shielding region 26. The structure obtained in step S3 can be referred to... Figure 4 As shown, an epitaxial layer 20 with trenches 22 is obtained.

[0054] Step S4: Form the first oxide layer material 40a within the trench 22. (Refer to...) Figure 5 As shown, the first oxide layer material 40a covers the sidewalls and bottom wall of the trench 22.

[0055] Step S5: Form the gate electrode material 30a on the first oxide layer material 40a within the trench 22. (Refer to...) Figure 6 The gate electrode material 30a and the first oxide layer material 40a are shown filling the trench 22.

[0056] Step S6: Remove the portion of the first oxide layer material 40a and the gate electrode material 30a away from the source region 24 and the well region 23. The remaining portion of the gate electrode material 30a forms the gate electrode 30. The structure obtained in step S6 can be referred to... Figure 7 As shown, a gap space is formed between the gate electrode 30 and the second shielding region 26.

[0057] Step S7: Form the second oxide layer material 40b. (Refer to...) Figure 8 As shown, the second oxide layer material 40b fills the space between the gate electrode 30 and the second shielding region 26, and covers the top surface of the epitaxial layer 20.

[0058] Step S8: Remove a portion of the second oxide layer material 40b. (Refer to...) Figure 9The second shielding region 26, the first sub-region 28 and the third shielding region 27 are exposed to the second oxide layer material 40a away from the surface of the substrate 10, and the second oxide layer material 40b remains covering the part of the gate electrode 30 away from the source region 24 and the well region 23 and covering the part of the gate electrode 30 on the top; and a space is formed between the side of the second shielding region 26 facing the gate electrode 30 and the second oxide layer material 40b.

[0059] Step S9: forming a Schottky metal 50. Refer to Fig. 5. Figure 10 The Schottky metal 50 covers the second shielding region 26, the first sub-region 28 and the third shielding region 27 away from the surface of the substrate 10, and extends to the side of the second shielding region 26 facing the gate electrode 30.

[0060] Step S10: forming a third oxide layer material 70a. Refer to Fig. 6. Figure 11 The third oxide layer material 70a covers the Schottky metal 50 away from the surface of the substrate 10 and covers the remaining part of the second oxide layer material 40a.

[0061] Step S11: removing part of the third oxide layer material 70a to obtain a field oxide layer 70. Refer to Fig. 7. Figure 12 The field oxide layer 70 exposes part of the surface of the Schottky metal 50 and exposes part of the surface of the source region 24 and the first shielding region 25.

[0062] Step S12: forming a source metal 60. Refer to Fig. 8. Figure 1 The source metal 60 is connected with the Schottky metal 50, the source region 24 and the first shielding region 25 respectively.

[0063] The above steps are only one specific way to obtain a semiconductor power device of one embodiment of the present application, and the embodiment is not limited thereto.

[0064] The above description is only a preferred embodiment of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiment, it is not intended to limit the present application. Any skilled person in the art can make some changes or modifications to the above disclosed technical content without departing from the technical solution of the present application, and any simple modification, equivalent change and modification of the above embodiment based on the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor power device, characterized by, The application relates to a semiconductor device, which comprises: a substrate (10); an epitaxial layer (20) arranged on the substrate (10), the epitaxial layer (20) being formed with a concave groove (22) on the side away from the top surface of the substrate (10); the epitaxial layer (20) comprises: a well region (23) arranged on one side of the groove (22); a source region (24) arranged on the side of the well region (23) facing the top surface of the epitaxial layer (20); a first shielding region (25) located on the side of the source region (24) and the well region (23) away from the groove (22); a second shielding region (26) located on the side of the groove (22) away from the source region (24) and the well region (23); a third shielding region (27) located on the side of the second shielding region (26) away from the source region (24) and the well region (23); the first shielding region (25), the second shielding region (26) and the third shielding region (27) are arranged at intervals; the epitaxial layer (20) further comprises a first sub-region (28) between the second shielding region (26) and the third shielding region (27); a gate electrode (30) arranged in the groove (22); a gate oxide layer (40) arranged in the groove (22) and isolated between the gate electrode (30) and the epitaxial layer (20); a Schottky metal (50) arranged on the top surface of the epitaxial layer (20) and connected with the second shielding region (26), the first sub-region (28) and the third shielding region (27) respectively; the Schottky metal (50) is arranged in insulation with the gate electrode (30).

2. The semiconductor power device of claim 1, wherein, The Schottky metal (50) comprises a main body (51) and an extension (52), the main body (51) covers the top surface of the epitaxial layer (20) and is connected with the second shielding region (26), the first sub-region (28) and the third shielding region (27) respectively, the extension (52) extends into the groove (22) from the end of the main body (51) close to the groove (22) along the depth direction of the groove (22); the extension (52) is insulated from the gate electrode (30) through the gate oxide layer (40), the side of the extension (52) away from the gate electrode (30) is connected with the second shielding region (26); the end of the second shielding region (26) close to the substrate (10) further extends to the bottom end of the extension (52) and is connected with the bottom end of the extension (52).

3. The semiconductor power device of claim 2, wherein, The gate oxide layer (40) comprises a first sub-layer (41) between the gate electrode (30) and the source region (24) and the well region (23) and a second sub-layer (42) between the gate electrode (30) and the extension (52), the thickness of the second sub-layer (42) is greater than that of the first sub-layer (41).

4. The semiconductor power device of claim 1, wherein, The distance from the end of the second shielding region (26) close to the substrate (10) to the substrate (10) is less than the distance from the bottom of the groove (22) to the substrate (10).

5. The semiconductor power device of claim 4, wherein, The second shielding area (26) extends to the bottom of the trench (22) on one side of the substrate (10) near one end of the substrate (10); and the minimum distance between the second shielding area (26) and the first shielding area (25) is less than the minimum distance between the side of the gate electrode (30) away from the first shielding area (25) and the first shielding area (25).

6. The semiconductor power device of claim 5, wherein, The minimum distance between the second shielding area (26) and the first shielding area (25) is less than the minimum distance between the trench (22) and the first shielding area (25).

7. The semiconductor power device of claim 1, wherein, The width of the second shielding area (26) on the side of the trench (22) away from the source area (24) and the well area (23) and the width of the third shielding area (27) are a first width, the width of the first sub-area (28) is a second width, and the ratio of the first width to the second width is 0.7-0.

8.

8. The semiconductor power device of claim 1, wherein, An ohmic contact layer (80) is further included, which is arranged between the Schottky metal (50) and the epitaxial layer (20).

9. The semiconductor power device of claim 1, wherein, The Schottky metal (50) is titanium or an alloy of titanium.

10. The semiconductor power device of claim 1, wherein, A source metal (60) is further included, which is arranged on the side of the epitaxial layer (20) away from the substrate (10), and the source metal (60) is connected with the Schottky metal (50), the source area (24) and the first shielding area (25) respectively; the gate electrode (30) is arranged in insulation with the source metal (60).

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