Chip packaging structure and chip

Abstract

The utility model discloses a chip packaging structure and a chip, and belongs to the technical field of chip packaging. The chip packaging structure comprises a function lamination layer which is provided with a circuit unit; the plurality of shielding columns are formed in the functional lamination layer, orthographic projections of the plurality of shielding columns on the first plane are arranged around the orthographic projection of the circuit unit on the first plane, the orthographic projections of the shielding columns on the first plane are arranged at intervals, and a gap between the orthographic projections of every two adjacent shielding columns on the first plane is smaller than a shielding electromagnetic wave wavelength; the first plane is perpendicular to the stacking direction of the functional stacking layers; and the packaging layer is used for packaging the functional lamination layer and surrounding the circuit units and the shielding columns. The electromagnetic shielding structure is packaged in the chip, so that the problems of exposure, oxidation and the like are avoided, the reliability is improved, the position selection freedom degree of the shielding columns in the chip is higher, the controllability is higher, scratches are not easily generated in the manufacturing process, the problem that subsequent manufacturing process identification is influenced by many scratches is avoided, and the strength of the internal overall structure and the heat conductivity are enhanced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip packaging, and particularly relates to a chip packaging structure and a chip. BACKGROUND

[0002] Based on the performance requirements of chips, most of them will increase EMI Shielding (electromagnetic interference shielding) in the product structure to reduce the interference of other electromagnetic waves or reduce the electromagnetic interference on other sensitive products. At present, the conventional measure of electromagnetic interference shielding of chips is to coat a metal layer on the surface of the chip, but the reliability of such structure is not high. CONTENT OF THE INVENTION

[0003] The application aims to at least solve one of the technical problems existing in the prior art. To this end, the application provides a chip packaging structure and a chip, which sets a shielding column in the packaging layer of the chip to form an electromagnetic shielding structure, avoids exposure, and is not prone to oxidation and other problems, thereby improving the reliability.

[0004] In a first aspect, the application provides a chip packaging structure, comprising:

[0005] a functional stack layer, which forms a circuit unit;

[0006] a plurality of shielding columns formed in the functional stack layer, the first plane is perpendicular to the stacking direction of the functional stack layer, and the first plane is perpendicular to the stacking direction of the functional stack layer.

[0007] a packaging layer, which encapsulates the functional stack layer and surrounds the circuit unit and the shielding column.

[0008] According to an embodiment of the application, the shielding column comprises a plurality of sub-columns connected along the stacking direction of the functional stack layer, and the sub-columns are formed in the structure layers in the functional stack layer.

[0009] According to an embodiment of the application, the sub-columns are formed in each structure layer in the functional stack layer.

[0010] According to an embodiment of the application, the gap between the first plane projections of the two adjacent shielding columns is less than one fourth of the wavelength of the electromagnetic wave to be shielded.

[0011] According to an embodiment of the application, the gap between the first plane projections of the two adjacent shielding columns is in the range of 3um to 1000um.

[0012] According to an embodiment of the application, the functional stack layer comprises:

[0013] a wiring layer, which forms a connection line;

[0014] the die and the connection line form a circuit unit;

[0015] the isolation layer is formed on one side of the wiring layer and covers the die.

[0016] According to one embodiment of the present application, the circuit unit comprises a plurality of dies, and the plurality of dies are arranged in multiple layers.

[0017] According to one embodiment of the present application, the material of the shielding column is the same as the material of the connection line.

[0018] According to one embodiment of the present application, the chip packaging structure further comprises:

[0019] the upper shielding layer comprises an upper shielding region, and a projection of the upper shielding region on the first plane covers projections of the shielding columns on the first plane; and / or

[0020] the lower shielding layer comprises a lower shielding region, and a projection of the lower shielding region on the first plane covers projections of the shielding columns on the first plane.

[0021] The upper shielding layer is formed on the upper side of the functional stack, and the upper shielding region is provided with shielding lines; or the upper shielding layer is the top layer of the functional stack, and the upper shielding region comprises the connection lines and / or shielding lines isolated from the connection lines.

[0022] The lower shielding layer is formed on the lower side of the functional stack, and the lower shielding region is provided with shielding lines; or the lower shielding layer is the bottom layer of the functional stack, and the lower shielding region comprises the connection lines and / or shielding lines isolated from the connection lines.

[0023] In a second aspect, the present application provides a chip, which comprises the chip packaging structure according to the foregoing.

[0024] The chip packaging structure and the chip according to the present application set the shielding columns inside the packaging layer of the chip to form an electromagnetic shielding structure, which is not exposed and is not prone to oxidation and other problems, thereby improving the reliability, and the position of the shielding columns inside the chip has higher freedom and stronger controllability, and is not prone to scratches in the process, thereby avoiding the problem that scratches affect the identification of the subsequent process, the overall internal structure is strengthened, and the heat conduction is strengthened.

[0025] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0027] Figure 1 is a top view of a chip packaging structure provided by an embodiment of the present application;

[0028] Figure 2 is another cross-sectional view of the chip packaging structure provided by an embodiment of the present application; Figure 1 is a cross-sectional view of the chip packaging structure shown along the AA line;

[0029] Figure 3 is another cross-sectional view of the chip packaging structure provided by an embodiment of the present application;

[0030] Figure 4 is one of structural diagrams in a chip packaging process provided by an embodiment of the present application;

[0031] Figure 5 is another structural diagram in the chip packaging process provided by an embodiment of the present application;

[0032] Figure 6 is still another structural diagram in the chip packaging process provided by an embodiment of the present application;

[0033] Figure 7 is a fourth structural diagram in the chip packaging process provided by an embodiment of the present application.

[0034] Reference signs:

[0035] functional stack 10, circuit unit 11, wiring layer 12, connection line 121, die 13, isolation layer 14, shielding column 20, packaging layer 30, substrate 40, upper shielding layer 50. DETAILED DESCRIPTION

[0036] Embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings. In the drawings, the size and relative sizes of layers, regions, elements, and the like can be exaggerated for clarity. Identical or similar component elements or component elements having identical or similar functions are denoted by identical or similar reference numerals throughout the specification. The embodiments described below by reference to the drawings are exemplary and are for the purpose of explanation only, and are not to be understood as limiting the present application.

[0037] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0038] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0039] In the related art, the method of electromagnetic interference shielding is to form a metal layer on the surface of the chip by sputtering after the overall packaging of the chip is completed, so as to achieve the purpose of electromagnetic interference shielding. However, because the metal sputtering is performed after the overall packaging is completed, the position of the metal layer is at the outermost layer of the chip, which is in direct contact with the air and is prone to oxidation and falling off, which puts high requirements on the material and reliability of the metal layer.

[0040] The present application provides a chip packaging structure and a chip. A shielding column is arranged inside the packaging layer of the chip to form an electromagnetic shielding structure, which is not exposed and is not prone to oxidation and other problems, thereby improving the reliability. The shielding column has higher freedom degree and stronger controllability in the selection of the position inside the chip, is not prone to scratches in the process, avoids the problem that many scratches affect the identification in the later process, and strengthens the overall internal structure and the heat conduction.

[0041] Reference Figure 1 and Figure 2 , Figure 1 Fig. 1 shows a top view of a chip packaging structure,Figure 2 A cross-sectional view of a chip packaging structure is shown, and one embodiment of the present application provides a chip packaging structure.

[0042] In the present embodiment, the chip packaging structure comprises a functional stack 10, a plurality of shielding pillars 20 and a packaging layer 30. The functional stack 10 is formed with a circuit unit 11. The plurality of shielding pillars 20 are formed in the functional stack 10, and the projections of the plurality of shielding pillars 20 on a first plane surround the projection of the circuit unit 11 on the first plane. The projections of the shielding pillars 20 on the first plane are arranged at intervals, and the gap between the projections of two adjacent shielding pillars 20 on the first plane is less than the wavelength of the electromagnetic wave to be shielded. The first plane is perpendicular to the stacking direction of the functional stack 10. The packaging layer 30 encapsulates the functional stack 10 and surrounds the circuit unit 11 and the shielding pillars 20.

[0043] It should be noted that the functional stack 10 refers to the semiconductor structure inside the chip, which can be composed of multiple layers of films made of different materials, such as insulating layers, conductive layers or semiconductor stacks, etc. Each film layer can also be filled with metal lines or vertical interconnection structures, etc.

[0044] The circuit unit 11 comprises structures such as metal lines and vertical interconnection structures, etc., which can be integrated with structures such as transistors, etc. The circuit unit 11 is the main unit for realizing the functions of the chip, and its specific structure can be determined according to the functions required to be realized by the chip, which is not limited in the present embodiment.

[0045] As shown in the cross-sectional view, Figure 2 the stacking direction of the functional stack 10 can be defined as the up-down direction, and the first plane is a plane perpendicular to the up-down direction, i.e. a plane composed of the left-right direction and the front-back direction (or the first plane is a horizontal plane). In addition, Figure 1 the cross-sectional view of the chip packaging structure along the first plane is shown. From the outside of the chip, the top of the chip is actually also covered with the packaging 30.

[0046] It can be understood that the gap through which the electromagnetic wave can penetrate during propagation must be greater than or equal to one wavelength, so the shielding structure formed by the plurality of shielding pillars 20 can block electromagnetic waves with a wavelength greater than the gap, thereby achieving the effect of electromagnetic shielding. The wavelength of the electromagnetic wave to be shielded can be designed according to requirements, and the specific value is not limited in the present embodiment.

[0047] The encapsulation layer 30 can cover the surfaces of the functional stack 10 in all directions to completely wrap the functional stack 10, thereby providing support for the functional stack 10 while isolating it from the outside, improving reliability. The material of the encapsulation layer 30 can be epoxy resin, ceramic material, or organic ceramic, etc. The shielding pillars 20 are located inside the encapsulation layer 30, and the rest is isolated from the outside, not easy to oxidize, and also not easy to scratch in subsequent processes, with high reliability.

[0048] In some embodiments, the material of the shielding pillars 20 can be metal, such as copper, silver, or aluminum, etc. The shielding pillars 20 can also form an electrical connection with the ground in the circuit unit 11, which can further improve the electromagnetic shielding effect. Of course, it can also be conductive polymer materials, carbon-based materials, or magnetic materials, etc.

[0049] In some embodiments, the gap between the projections of the two adjacent shielding pillars 20 in the first plane is less than one quarter of the wavelength of the electromagnetic wave to be shielded.

[0050] In the present embodiment, the gap between the two adjacent shielding pillars 20 is much smaller than the wavelength of the electromagnetic wave to be shielded, thereby also avoiding the diffraction effect of the electromagnetic wave when it contacts the gap, thereby achieving better electromagnetic shielding effect.

[0051] As an example, the gap between the projections of the two adjacent shielding pillars 20 in the first plane is in the range of 3um-1000um, such as 5um, 100um, or 500um, etc.

[0052] Reference Figure 3 , Figure 3 A cross-sectional view of a chip packaging structure is shown. In some embodiments, the functional stack 10 can include a wiring layer 12, a die 13, and an isolation layer 14, the wiring layer 12 is formed with a connection line 121; the die 13 is connected with the connection line 12, and the die 13 and the connection line 121 form a circuit unit 11; the isolation layer 14 is formed on one side of the wiring layer 12 and covers the die 13.

[0053] The die 13 refers to a chip die, which is a part of semiconductor material inside the chip, usually a silicon wafer, which contains functional components such as circuits and transistors. The wiring layer 12 can also be referred to as an RDL (Redistribution Layer) layer, which is used to redistribute the pins of the die 13, and its preparation process usually includes photolithography, metal deposition, etching, and again photolithography and metal deposition.

[0054] The isolation layer 14 is used to fill around the die 13 and has a protective effect. The isolation layer 14 and the part of the wiring layer 12 other than the connection line 121 can be made of insulating materials such as silicon dioxide, etc.

[0055] In some embodiments, the shielding post 20 comprises a plurality of sub-posts 21 connected along a stacking direction of the functional stack 10, the sub-posts 21 being formed in a structure layer in the functional stack 10.

[0056] In the present embodiment, the structure layers in the functional stack 10 can comprise the wiring layer 12 and the isolation layer 14, and can also comprise other types of material layers based on the functions required to be implemented by the chip. The shielding post 20 is stacked by a plurality of sub-posts 21, each of which can be prepared at the same time as the wiring layer 12, thereby not requiring a separate opening or a new process, but only modifying the existing mask to reserve a copper post pattern at the required position. The position of the copper post is determined by the mask and can be specified at any position, and in combination with the RDL design, the local shielding function of a single die can be achieved, with higher freedom and stronger controllability.

[0057] In some embodiments, the material of the shielding post 20 is the same as that of the connection line 121. Thus, the connection line 121 and the sub-post 21 in the wiring layer 12 can be deposited at the same time in one deposition process, saving the process.

[0058] As an example, each of the structure layers in the functional stack 10 is formed with a sub-post 21. In the present example, the shielding post 20 is arranged through the entire functional stack 10, covering the height of the functional stack 10 to the greatest extent, thereby improving the electromagnetic shielding effect.

[0059] In some embodiments, the circuit unit 11 comprises a plurality of dies 13, and the plurality of dies 13 are arranged in multiple layers.

[0060] As shown in FIG. 1, the circuit unit 11 can comprise six dies 13 arranged in three layers, each layer being provided below with a wiring layer 12 forming a connection line 121 to realize the connection of each die 13. Each die 13 can have different structures and different connection modes (such as flip-chip or face-up). Figure 3 Thus, the integration of the circuit unit 11 is improved, and the plurality of shielding posts 20 surrounding one shielding unit can provide electromagnetic shielding for the plurality of dies 13.

[0061] In other embodiments, the circuit unit 11 can comprise one die 13, and the plurality of shielding posts 20 surrounding one shielding unit can provide electromagnetic shielding for the one die 13. Thus, the electromagnetic shielding effect of the die 13 is improved.

[0062] In some embodiments, the functional stack 10 is formed with a plurality of circuit units 11 and a corresponding plurality of shielding units, the shielding unit comprising a plurality of shielding posts.

[0063] The chip can be provided with multiple shielding units, each of which provides electromagnetic shielding in a corresponding region. The gaps between adjacent shielding columns 20 in each shielding unit can be the same or different, to adapt to the electromagnetic shielding effect of different parts. When the chip is large in size, the electromagnetic shielding effect can be ensured by designing the electromagnetic shielding in different regions, and the gaps between the shielding columns 20 are designed adaptively for each region, which is also conducive to cost control.

[0064] With reference to the foregoing Figure 3 In some embodiments, the chip package structure further comprises an upper shielding layer 50, the upper shielding layer 50 comprises an upper shielding region, a projection of the upper shielding region on the first plane covers the projections of the shielding columns 20 on the first plane, wherein the upper shielding layer 50 is formed on the upper side of the functional stack 10, and the upper shielding region is provided with shielding lines; or the upper shielding layer 50 is the top layer of the functional stack 10, and the upper shielding region comprises connection lines and / or shielding lines isolated from the connection lines.

[0065] In the present embodiment, the upper shielding region is used to form a shielding structure that surrounds the side and top surfaces of the circuit unit 11 in combination with the shielding columns 20, thereby playing an electromagnetic shielding role in more directions of the circuit unit 11 and improving the electromagnetic shielding effect.

[0066] The upper shielding layer 50 can be a structure layer additionally provided on the upper layer of the functional stack 10, and a shielding structure is formed by laying shielding lines. Alternatively, the upper shielding layer 50 can be formed based on the top structure layer of the functional stack 10, and a shielding structure is formed by using the original connection lines 121 and the additionally laid shielding lines. In addition, the upper shielding layer 50 is also surrounded by the package layer 30.

[0067] The shielding lines can be metal traces similar to the connection lines 121 in the functional stack 10. Of course, the shielding lines can also have a wider width, thereby extending into a sheet structure and covering more area.

[0068] In the present embodiment, the shielding lines and the shielding columns 20 can be in contact and are both connected to the ground part of the connection lines 121 in the functional stack 10, to improve the electromagnetic shielding effect. In addition, the gaps between the shielding lines and between the shielding lines and the connection lines 121 are also less than the wavelength of the electromagnetic waves to be shielded. The gap can be described with reference to the foregoing description of the gap between the shielding columns 20, which will not be described here in detail.

[0069] In some other embodiments, the chip packaging structure further comprises a lower shielding layer, the lower shielding layer comprises a lower shielding region, the lower shielding region covers the projection of each shielding column 20 on the first plane in the projection on the first plane; the lower shielding layer is formed on the lower side of the functional stack 10, the lower shielding region is provided with shielding lines; or the lower shielding layer is the bottom layer of the functional stack 10, and the lower shielding region comprises connection lines and / or shielding lines isolated from the connection lines.

[0070] In the present embodiment, the shielding structure can also be formed on the bottom side of the functional stack 10, which surrounds the side and bottom of the circuit unit 11 in combination with each shielding column 20, thereby playing an electromagnetic shielding role in more directions of the circuit unit 11 and improving the electromagnetic shielding effect. The description of the shielding lines can refer to the description of the shielding lines in the upper shielding layer 50, which will not be repeated here.

[0071] In some other embodiments, the chip packaging structure can comprise an upper shielding layer 50 and a lower shielding layer, thereby realizing the all-around electromagnetic shielding of the circuit unit 11 in combination with the shielding columns 20 and further improving the electromagnetic shielding effect.

[0072] Reference Figures 4 to 7 , Figures 4 to 7 A structure in a chip packaging process is shown. As shown in Figure 4 , the wiring layer 12 is formed on the substrate 40, and the connection lines 121 and the sub-columns 21 are formed in the wiring layer 12, wherein each sub-column 21 further comprises a sub-column 21 in the same layer as the die 13; then as shown in Figure 5 , the die 13 is connected on the connection lines 121; then as shown in Figure 6 , the isolation layer 14 is formed; then as shown in Figure 7 , the wiring layer 12 is formed on the isolation layer 14, and the connection lines 121 and the sub-columns 21 are formed in the wiring layer 12. The cycle is repeated in sequence until all the die 13 connections are completed, the substrate 40 is removed, and the chip packaging structure as shown in Figure 3 is formed.

[0073] One embodiment of the present application also provides a chip comprising the chip packaging structure according to the foregoing. The specific structure and principle of the chip packaging structure can refer to the foregoing embodiments, which also has the corresponding technical effects, and will not be repeated here.

[0074] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a functional stack layer, which is formed with a circuit unit; a plurality of shielding columns, which are formed in the functional stack layer, and the projections of the plurality of shielding columns on a first plane surround the projection of the circuit unit on the first plane, the projections of the shielding columns on the first plane are arranged at intervals, and the gap between the projections of two adjacent shielding columns on the first plane is less than the wavelength of electromagnetic waves to be shielded; a packaging layer, which encapsulates the functional stack layer and surrounds the circuit unit and the shielding columns.

2. The chip package structure of claim 1, wherein, The shielding columns comprise a plurality of sub-columns connected along the stacking direction of the functional stack layer, and the sub-columns are formed in a structural layer in the functional stack layer.

3. The chip package structure of claim 2, wherein, The sub-columns are formed in each of the structural layers in the functional stack layer.

4. The chip package structure of any one of claims 1-3, wherein, The gap between the projections of two adjacent shielding columns on the first plane is less than one fourth of the wavelength of electromagnetic waves to be shielded.

5. The chip package structure of claim 4, wherein, The gap between the projections of two adjacent shielding columns on the first plane ranges from 3 um to 1000 um.

6. The chip package structure of any one of claims 1-3, wherein, The functional stack layer comprises: a wiring layer, which is formed with a connection line; a die, which is connected to the connection line, and the die and the connection line form the circuit unit; an isolation layer, which is formed on one side of the wiring layer and covers the die.

7. The chip package structure of claim 6, wherein, The circuit unit comprises a plurality of dies, and the plurality of dies are arranged in multiple layers.

8. The chip package structure of claim 6, wherein, The material of the shielding columns is the same as that of the connection line.

9. The chip package structure of any one of claims 1-3, wherein, The chip package structure further comprises: an upper shielding layer, which comprises an upper shielding region, and the projection of the upper shielding region on the first plane covers the projection of each shielding column on the first plane; and / or a lower shielding layer, which comprises a lower shielding region, and the projection of the lower shielding region on the first plane covers the projection of each shielding column on the first plane; wherein the upper shielding layer is formed on the upper side of the functional stack layer, and the upper shielding region is provided with a shielding line; or the upper shielding layer is the top layer of the functional stack layer, and the upper shielding region comprises a connection line and / or a shielding line that is isolated from the connection line; the lower shielding layer is formed on the lower side of the functional stack layer, and the lower shielding region is provided with a shielding line; or the lower shielding layer is the bottom layer of the functional stack layer, and the lower shielding region comprises a connection line and / or a shielding line that is isolated from the connection line.

10. A chip, characterized by The chip comprises the chip package structure according to any one of claims 1-9.

Images