Chip packaging structure and chip packaging module
By using an adapter board to electrically connect to the printed circuit board in the COWOS chip packaging module, increasing the diameter and spacing of the solder balls, and combining the design of redistribution layers, silicon interposers, and reinforcing ribs, the problem of poor soldering was solved, and the yield and electrical connection reliability of the chip packaging module were improved.
Patent Information
- Application Number
- CN202422923275.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2034-11-28
AI Technical Summary
The low yield rate in COWOS chip packaging modules is mainly due to poor solder ball coplanarity and poor electrical connection caused by warping.
An adapter board is used to electrically connect to the printed circuit board, the diameter and spacing of the solder balls are increased, and the coplanarity and solderability are improved through the design of the redistribution layer and silicon interposer. The packaging substrate is eliminated, the reflow soldering process is reduced, and the structure is optimized by combining reinforcing ribs and passive components.
It improves the soldering yield of chip packaging modules, reduces warpage, enhances electrical connection reliability and anti-interference capability, and improves assembly success rate and integration.
Smart Images
Figure CN223810138U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip packaging module. BACKGROUND
[0002] In a COWOS (Chip on Wafer on Substrate) chip packaging module, a plurality of dies are electrically connected with a silicon interposer, the silicon interposer is electrically connected with a packaging substrate, the packaging substrate is electrically connected with a printed circuit board, and the plurality of dies achieve electrical connection with each other and electrical connection with the packaging substrate through the silicon interposer. In the process of manufacturing the chip packaging module, the electrical connection of the dies with the silicon interposer, the electrical connection of the silicon interposer with the packaging substrate, and the electrical connection of the packaging substrate with the printed circuit board are achieved by melting the solder balls between the dies and the silicon interposer, the solder balls between the silicon interposer and the packaging substrate, and the solder balls between the packaging substrate and the printed circuit board through multiple reflow soldering processes. However, the current COWOS chip packaging module often has a problem of poor welding, resulting in a low yield. CONTENT OF THE UTILITY MODEL
[0003] The present application discloses a chip packaging structure and a chip packaging module to solve the problem of low yield of the chip packaging module caused by poor welding.
[0004] In a first aspect, the present application discloses a chip packaging structure, comprising: a plurality of dies; a conversion board, the plurality of dies being located on one side of the conversion board, and the plurality of dies being electrically connected with the conversion board; the conversion board being used to achieve electrical connection between the plurality of dies and electrical connection between the plurality of dies and a printed circuit board; the side of the conversion board away from the plurality of dies having a plurality of first solder balls; the first solder balls being used to achieve electrical connection between the conversion board and the printed circuit board; and the diameter of the first solder balls being greater than or equal to 200 μm.
[0005] In this way, by making the dies electrically connected with the printed circuit board through the conversion board, the packaging substrate can be cancelled and at least one reflow soldering process can be reduced, thereby reducing the warpage of the chip packaging structure, and further improving the coplanarity of the first solder balls between the conversion board and the printed circuit board, thereby reducing the probability of poor welding of the chip packaging module, and further improving the yield of the chip packaging module. Moreover, by making the diameter of the first solder balls between the conversion board and the printed circuit board greater than or equal to 200 μm, the coplanarity, consistency and weldability of the first solder balls between the conversion board and the printed circuit board can also be improved, thereby further reducing the probability of poor welding of the chip packaging module, and further improving the yield of the chip packaging module.
[0006] In some embodiments of the present application, the pitch of the first solder balls is greater than or equal to 300 μm.
[0007] In this way, not only can the diameter of the first solder balls be increased, but short circuits between the first solder balls can also be avoided, which can reduce the probability of poor soldering of the chip packaging module and improve the yield of the chip packaging module.
[0008] In some embodiments of the present application, the adapter board includes a redistribution layer and a silicon interposer; the plurality of dies are located on one side of the redistribution layer, and the plurality of dies are electrically connected to the redistribution layer; the silicon interposer is located on the side of the redistribution layer away from the plurality of dies; and the redistribution layer is electrically connected to the silicon interposer.
[0009] In this way, not only can the electrical connection between the dies and the printed circuit board be achieved through the adapter board including the redistribution layer and the silicon interposer, but the structure of the redistribution layer and the silicon interposer can also be designed to increase the pitch and diameter of the first solder balls, which can improve the coplanarity, consistency and solderability of the first solder balls, thereby reducing the probability of poor soldering of the chip packaging module and improving the yield of the chip packaging module.
[0010] In some embodiments of the present application, the redistribution layer includes a plurality of conductive layers and a plurality of insulating layers; the insulating layer is between any two conductive layers; and the conductive layers include traces, and the traces of any two conductive layers are electrically connected through a via that penetrates the insulating layer between them.
[0011] In this way, the structure of the redistribution layer can be designed to increase the pitch and diameter of the first solder balls, which can improve the coplanarity, consistency and solderability of the first solder balls, thereby reducing the probability of poor soldering of the chip packaging module and improving the yield of the chip packaging module.
[0012] In some embodiments of the present application, the silicon interposer has a plurality of through-silicon vias, the through-silicon vias penetrate the silicon interposer, the plurality of first solder balls are located on the side of the silicon interposer away from the redistribution layer, and the plurality of through-silicon vias are respectively electrically connected to the plurality of first solder balls.
[0013] In this way, the structure of the silicon interposer can be designed to increase the pitch and diameter of the first solder balls, which can improve the coplanarity, consistency and solderability of the first solder balls, thereby reducing the probability of poor soldering of the chip packaging module and improving the yield of the chip packaging module.
[0014] In a second aspect, the present application discloses a chip packaging module, which includes: the chip packaging structure according to any one of the above; and a printed circuit board, wherein the chip packaging structure is located on one side of the printed circuit board, and the chip packaging structure is electrically connected to the printed circuit board.
[0015] In this way, by making the die pass through the adapter plate to be electrically connected with the printed circuit board and by making the diameter of the first solder ball between the adapter plate and the printed circuit board greater than or equal to 200 μm, the probability of poor soldering of the chip packaging module can be reduced, and the yield of the chip packaging module can be improved.
[0016] In some embodiments of the present application, the chip packaging module further comprises a reinforcing rib; the reinforcing rib and the chip packaging structure are located on the same side of the printed circuit board; and the reinforcing rib at least partially surrounds the chip packaging structure.
[0017] In this way, by reasonably setting the reinforcing rib, the warpage of the chip packaging module can be reduced, the probability of poor soldering of the chip packaging module can be reduced, and the assembly success rate and yield of the chip packaging module can be improved.
[0018] In some embodiments of the present application, the thickness of the reinforcing rib is less than or equal to 3 mm; and / or, the width of the reinforcing rib is greater than or equal to 5 mm.
[0019] In this way, by reasonably designing the thickness and width of the reinforcing rib, the warpage of the chip packaging module can be maximally reduced on the basis of ensuring low cost, the probability of poor soldering of the chip packaging module can be reduced, and the assembly success rate and yield of the chip packaging module can be improved.
[0020] In some embodiments of the present application, the chip packaging module further comprises a passive device; the passive device and the chip packaging structure are located on the same side of the printed circuit board; and the passive device is electrically connected with the printed circuit board.
[0021] In this way, by reasonably setting the passive device, the anti-interference capability of the printed circuit board and the chip packaging module can be improved.
[0022] In some embodiments of the present application, the passive device is located on the side of the reinforcing rib away from the chip packaging structure.
[0023] In this way, by reasonably designing the positions of the passive device and the reinforcing rib, the integration of the chip packaging module can be improved on the basis of ensuring the anti-interference capability and small warpage of the chip packaging module. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments of the present application or the prior art will be described below.
[0025] Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a COWOS chip packaging module disclosed by the present application.
[0026] Figure 2 This is a cross-sectional schematic diagram of a chip packaging structure disclosed in an embodiment of this application.
[0027] Figure 3 This is a cross-sectional structural diagram of a chip packaging module disclosed in an embodiment of this application.
[0028] Figure 4 This is a cross-sectional structural diagram of an adapter plate disclosed in an embodiment of this application.
[0029] Figure 5 This is a cross-sectional structural diagram of another adapter plate disclosed in an embodiment of this application.
[0030] Figure 6 This is a cross-sectional structural diagram of another chip packaging module disclosed in an embodiment of this application.
[0031] Figure 7 This is a top view of another chip packaging module disclosed in an embodiment of this application.
[0032] Figure 8 This is a cross-sectional structural diagram of another chip packaging module disclosed in an embodiment of this application. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0034] like Figure 1 As shown, Figure 1 This is a cross-sectional structural diagram of a COWOS chip packaging module disclosed in this application. The chip packaging module includes multiple dies 10, a silicon interposer 11, a packaging substrate 12, and a printed circuit board 13. The multiple dies 10 are electrically connected to the silicon interposer 11 via second solder balls 100, the silicon interposer 11 is electrically connected to the packaging substrate 12 via third solder balls 111, and the packaging substrate 12 is electrically connected to the printed circuit board 13 via fourth solder balls 120. The silicon interposer 11 is used to realize the electrical connection between the multiple dies 10 and the electrical connection between the multiple dies 10 and the packaging substrate 12, and the packaging substrate 12 is used to realize the electrical connection between the silicon interposer 11 and the printed circuit board 13.
[0035] In the process of manufacturing chip packaging modules, multiple reflow soldering processes are required to melt the second solder ball 100 between the bare die 10 and the silicon interposer 11, the third solder ball 111 between the silicon interposer 11 and the packaging substrate 12, and the fourth solder ball 120 between the packaging substrate 12 and the printed circuit board 13, so as to achieve electrical connection between the bare die 10 and the silicon interposer 11, the silicon interposer 11 and the packaging substrate 12, and the packaging substrate 12 and the printed circuit board 13.
[0036] However, because the thermal expansion coefficients of the bare die 10, silicon interposer 11, packaging substrate 12, and printed circuit board 13 are different, warping of the chip packaging module after reflow soldering can occur. Furthermore, while the COWOS chip packaging module can improve the integration and computing power of the chip packaging module, it also leads to a dramatic increase in the size of the chip packaging module, and larger chip packaging modules experience greater warping. Excessive warping results in poor coplanarity of the fourth solder ball 120 between the packaging substrate 12 and the printed circuit board 13, frequently causing soldering defects in the COWOS chip packaging module and resulting in a low yield rate.
[0037] Based on this, this application discloses a chip packaging structure that improves the coplanarity of the solder balls between the adapter board and the printed circuit board by making the bare die electrically connected to the printed circuit board through an adapter board and by making the diameter of the solder balls between the adapter board and the printed circuit board greater than or equal to 200μm, thereby reducing the probability of soldering defects in the chip packaging module and improving the yield of the chip packaging module.
[0038] As an optional implementation of the disclosure in this application, an embodiment of this application discloses a chip packaging structure, such as... Figure 2 As shown, Figure 2 This is a cross-sectional schematic diagram of a chip packaging structure disclosed in an embodiment of this application. The chip packaging structure includes multiple dies 10 and an adapter board 20. The multiple dies 10 are located on one side of the adapter board 20. Specifically, the multiple dies 10 are located on the same side of the adapter board 20. All the multiple dies 10 are electrically connected to the adapter board 20, which is used to realize the electrical connection between the multiple dies 10.
[0039] And, as Figure 3 As shown, Figure 3 This is a cross-sectional structural diagram of a chip packaging module disclosed in an embodiment of this application. The chip packaging module includes... Figure 2 The chip packaging structure and printed circuit board 13 are shown. The adapter board 20 is electrically connected to the printed circuit board 13, and the adapter board 20 is also used to realize the electrical connection between multiple bare dies 10 and the printed circuit board 13.
[0040] In addition, such as Figure 2and Figure 3 As shown in FIG. 1, the side of the adapter plate 20 away from the plurality of dies 10 has a plurality of first solder balls 200 for realizing the electrical connection between the adapter plate 20 and the printed circuit board 13. The diameter D of the first solder ball 200 is greater than or equal to 200 μm.
[0041] In the embodiments of the present application, by making the die 10 electrically connected to the printed circuit board 13 through the adapter plate 20, the packaging substrate 12 can be cancelled and at least one reflow process can be reduced, so that the warpage of the chip packaging structure can be reduced, and the coplanarity of the solder balls between the adapter plate 20 and the printed circuit board 13 can be improved, and the probability of poor welding of the chip packaging module assembled by the chip packaging structure can be reduced, and the yield of the chip packaging module can be improved.
[0042] In addition, in the embodiments of the present application, by making the diameter D of the first solder ball 200 between the adapter plate 20 and the printed circuit board 13 greater than or equal to 200 μm, the coplanarity, consistency and weldability of the first solder ball 200 between the adapter plate 20 and the printed circuit board 13 can be improved, and the probability of poor welding of the chip packaging module can be further reduced, and the yield of the chip packaging module can be further improved. It should be noted that, as shown in FIG. 1, the diameter of the fourth solder ball 120 between the conventional chip packaging structure and the printed circuit board 13 is about 80 μm. Figure 1
[0043] On this basis, in some embodiments of the present application, the pitch L of the first solder ball 200 is greater than or equal to 300 μm. Based on this, not only the diameter of the first solder ball 200 can be increased, but also the short circuit between the first solder ball 200 can be avoided, which is beneficial to reduce the probability of poor welding of the chip packaging module and improve the yield of the chip packaging module.
[0044] In some embodiments of the present application, the diameter D of the first solder ball 200 can be 0.25 mm, and the pitch L of the first solder ball 200 can be 0.4 mm. Of course, the present application is not limited to this, in other embodiments, the diameter D of the first solder ball 200 can be 0.2 mm, and the pitch L of the first solder ball 200 can be 0.3 mm; or the diameter D of the first solder ball 200 can be 0.15 mm, and the pitch L of the first solder ball 200 can be 0.25 mm.
[0045] In some embodiments of the present application, as shown in FIG. 1, Figure 4 Figure 4 As shown in a cross-sectional structure diagram of a conversion board disclosed by some embodiments of the present application, the conversion board 20 includes a redistribution layer 201 and a silicon interposer 11, wherein a plurality of dies 10 are located on one side of the redistribution layer 201, the plurality of dies 10 are electrically connected with the redistribution layer 201, the silicon interposer 11 is located on the side of the redistribution layer 201 away from the plurality of dies 10, and the redistribution layer 201 is electrically connected with the silicon interposer 11.
[0046] Based on this, not only the electrical connection between the die 10 and the printed circuit board 13 can be realized through the conversion board 20 including the redistribution layer 201 and the silicon interposer 11, but also the structure of the redistribution layer 201 and the silicon interposer 11 can be designed to increase the pitch and diameter of the first solder ball 200, so that the coplanarity, consistency and solderability of the first solder ball 200 can be improved, and then the probability of poor welding of the chip packaging module can be reduced, and then the yield of the chip packaging module can be improved.
[0047] On this basis, as shown in some embodiments of the present application, Figure 5 as shown, Figure 5 As shown in another cross-sectional structure diagram of a conversion board disclosed by some embodiments of the present application, the redistribution layer 201 includes a plurality of conductive layers 2010 and a plurality of insulating layers 2011, and the insulating layer 2011 is arranged between any two conductive layers 2010. The conductive layer 2010 includes a trace, and the traces of any two conductive layers 2010 are electrically connected through a via hole penetrating the insulating layer 2011 between the two conductive layers 2010. The silicon interposer 11 has a plurality of through silicon vias 110, the through silicon via 110 penetrates the silicon interposer 11, a plurality of solder balls 220 are located on the side of the silicon interposer 11 away from the redistribution layer 201, and the plurality of through silicon vias 110 and the plurality of solder balls 220 are respectively electrically connected.
[0048] Based on this, the structure of the redistribution layer 201 and the silicon interposer 11 can be designed to increase the pitch and diameter of the first solder ball 200, so that the coplanarity, consistency and solderability of the first solder ball 200 can be improved, and then the probability of poor welding of the chip packaging module can be reduced, and then the yield of the chip packaging module can be improved.
[0049] As shown in some embodiments of the present application, Figure 5 as shown, the die 10 can be electrically connected with the redistribution layer 201 through the second solder ball 100, and a bottom filler is filled between the die 10 and the redistribution layer 201 to protect the second solder ball 100. The silicon interposer 11 and the printed circuit board 13 can also be filled with a bottom filler to protect the first solder ball 200.
[0050] As an optional implementation of the present application, some embodiments of the present application disclose a chip packaging module, as shown in Figure 3As shown in the figure, the chip packaging module includes the chip packaging structure and the printed circuit board 13 disclosed in any of the above embodiments. The chip packaging structure is located on one side of the printed circuit board 13, and the chip packaging structure is electrically connected to the printed circuit board 13. Specifically, the adapter plate 20 of the chip packaging structure is electrically connected to the printed circuit board 13, and the adapter plate 20 is also used to realize the electrical connection between the plurality of dies 10 and the printed circuit board 13. Based on this, the probability of poor welding of the chip packaging module can be reduced, and the yield of the chip packaging module can be improved.
[0051] As shown in the figure, Figure 6 As shown in the figure, Figure 6 As shown in the figure, the chip packaging module further includes a reinforcing rib 30, and the reinforcing rib 30 is located on the same side of the printed circuit board 13 as the chip packaging structure. As shown in the figure, Figure 7 As shown in the figure, Figure 7 As shown in the figure, the chip packaging module further includes a reinforcing rib 30, and the reinforcing rib 30 is located on the same side of the printed circuit board 13 as the chip packaging structure. As shown in the figure,
[0052] On this basis, in some embodiments of the present application, the thickness of the reinforcing rib 30 is less than or equal to 3mm; and / or the width of the reinforcing rib 30 is greater than or equal to 5mm. Optionally, the thickness of the reinforcing rib 30 is 2mm, and the width of the reinforcing rib 30 is 5mm. The material of the reinforcing rib 30 can be copper or stainless steel, etc. Based on this, by reasonably designing the thickness and width of the reinforcing rib 30, the warping of the chip packaging module can be minimized to the greatest extent on the basis of ensuring low cost, and the probability of poor welding of the chip packaging module can be reduced, and the assembly success rate and yield of the chip packaging module can be improved.
[0053] As shown in the figure, Figure 8 As shown in the figure, Figure 8 As shown in the figure, the chip packaging module further includes a reinforcing rib 30, and the reinforcing rib 30 is located on the same side of the printed circuit board 13 as the chip packaging structure. As shown in the figure,
[0054] As shown in the figure, Figure 8As shown, the passive device 40 is located on the side of the reinforcing rib 30 away from the chip packaging structure, so as to improve the integration of the chip packaging module on the basis of ensuring the anti-interference ability and small warping of the chip packaging module by reasonably designing the positions of the passive device 40 and the reinforcing rib 30. Of course, the present application is not limited to this, and in other embodiments, the passive device 40 can also be located between the reinforcing rib 30 and the chip packaging structure.
[0055] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.
[0056] The above embodiments only express several implementation manners of the present disclosure, and the description is specific and detailed, but it should not be understood as a limitation on the patent scope of the present disclosure. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the patent protection scope of the present disclosure should be subject to the appended claims.
Claims
1. A chip package structure, characterized by, The chip package structure comprises: a plurality of dies; a transition board, the plurality of dies are located on one side of the transition board, and the plurality of dies are all electrically connected with the transition board; the transition board is used to realize electrical connection between the plurality of dies and electrical connection between the plurality of dies and a printed circuit board; a plurality of first solder balls are located on the side of the transition board away from the plurality of dies; the first solder balls are used to directly connect the transition board and the printed circuit board; the diameter of the first solder balls is greater than or equal to 200 μm.
2. The chip package structure of claim 1, wherein, The pitch of the first solder balls is greater than or equal to 300 μm.
3. The chip package structure of claim 1, wherein, The transition board comprises a rewiring layer and a silicon interposer; the plurality of dies are located on one side of the rewiring layer, and the plurality of dies are all electrically connected with the rewiring layer; the silicon interposer is located on the side of the rewiring layer away from the plurality of dies; the rewiring layer is electrically connected with the silicon interposer.
4. The chip package structure of claim 3, wherein, The rewiring layer comprises a plurality of conductive layers and a plurality of insulating layers; the insulating layer is located between any two of the conductive layers; the conductive layer comprises a trace, and the traces of any two of the conductive layers are electrically connected through a via hole penetrating the insulating layer between them.
5. The chip package structure of claim 3, wherein, The silicon interposer has a plurality of through-silicon vias, the through-silicon vias penetrate the silicon interposer, the plurality of first solder balls are located on the side of the silicon interposer away from the rewiring layer, and the plurality of through-silicon vias are respectively electrically connected with the plurality of first solder balls.
6. A chip package module, comprising: The chip package structure comprises: any one of claims 1-5; a printed circuit board, the chip package structure is located on one side of the printed circuit board, and the chip package structure is connected with the printed circuit board through first solder balls.
7. The chip package module of claim 6, wherein, The chip package module further comprises a reinforcing rib; the reinforcing rib and the chip package structure are located on the same side of the printed circuit board; the reinforcing rib at least partially surrounds the chip package structure.
8. The chip package module of claim 7, wherein, The thickness of the reinforcing rib is less than or equal to 3 mm; and / or, the width of the reinforcing rib is greater than or equal to 5 mm.
9. The chip package module of claim 6 or 7, wherein, The chip package module further comprises a passive device; the passive device and the chip package structure are located on the same side of the printed circuit board; the passive device is electrically connected with the printed circuit board.
10. The chip package module of claim 9, wherein, The passive device is located on the side of the reinforcing rib away from the chip package structure.