Planar grid array packaging structure

Abstract

The utility model discloses a planar grid array packaging structure, which comprises a substrate, a first base island, a second base island and a pin bonding pad which are electrically connected are arranged on the front surface of the substrate, a back bonding pad is arranged on the back surface of the substrate, and the pin bonding pad is electrically connected with the back bonding pad; the plurality of first base islands and the plurality of pin bonding pads are arranged on the peripheral side of the second base island; the substrate is plastically packaged in a plastic package body, and a heat dissipation module is further arranged on the back surface of the substrate. Through the planar grid array packaging structure, the technical problem that in a traditional packaging structure, the number of pins, the distance, the heat dissipation performance and the like are gradually difficult to meet the requirements is solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor packaging technical field, concretely relates to a planar grid array packaging structure. BACKGROUND

[0002] With the continuous pursuit of high performance, miniaturization and multi-function of electronic equipment, chip packaging technology continues to evolve. Traditional packaging methods such as dual in-line package (DIP), quad flat package (QFP) and the like gradually fail to meet the requirements of complex chips in terms of pin number, pitch, heat dissipation performance and the like.

[0003] LGA packaging technology emerges as the times require, which realizes the connection of more pin numbers by setting a grid-shaped pin array at the bottom of the chip, and at the same time reduces the packaging size, providing support for the function improvement and integration increase of the chip. UTILITY MODEL CONTENT

[0004] The utility model provides a planar grid array packaging structure, which aims to solve the technical problem that the traditional packaging structure gradually fails to meet the requirements in terms of pin number, pitch, heat dissipation performance and the like.

[0005] The technical solution provided by the utility model is as follows:

[0006] A planar grid array packaging structure includes a substrate, the front surface of the substrate is provided with electrically connected first base islands, second base islands and pin pads, the back surface of the substrate is provided with back pads, and the pin pads are electrically connected with the back pads;

[0007] A plurality of first base islands and a plurality of pin pads are arranged on the periphery of the second base island;

[0008] The substrate is plastic encapsulated in a plastic encapsulation body.

[0009] Further, the second base island is arranged at the middle part of the substrate, and a plurality of first base islands are arrayed on the periphery of the second base island.

[0010] Further, a plurality of pin pads are arranged on the substrate between the second base island and the first base island.

[0011] Further, the pin pads and the second base island are connected by a bonding wire;

[0012] The first base island and the pin pad are connected by a microstrip line.

[0013] Further, a plurality of ink plug holes are uniformly distributed on the edges of the substrate, and the first base island and / or the pin pad is connected with the ink plug hole by a microstrip line;

[0014] The back pad is connected with the ink plug hole.

[0015] Further, the surface of the plastic package is covered with a light-absorbing layer or a light-reflecting layer.

[0016] Further, the first base island surface is provided with an LED chip.

[0017] The second base island surface is provided with an IC chip.

[0018] Compared with the prior art, the utility model has the beneficial effects that:

[0019] 1. The plane grid array packaging structure provided by the utility model is reasonable in layout and high in density of grid array design through the first base island, the pin pad and the like, more connecting points can be realized in limited space, the connecting density between the chip and the substrate is improved, the high-density integration of electronic equipment is helped to realize, meanwhile, the packaging form is also favorable for reducing the size and weight of the whole electronic system, and meets the demand for miniaturization of portable equipment, wearable equipment and the like;

[0020] 2. The plane grid array packaging structure provided by the utility model leaves a certain gap between the IC chip and / or the LED chip and the substrate, better conditions are provided for heat dissipation, the LGA packaging can also conveniently add a heat dissipation back plate or a heat dissipation module, the heat dissipation effect is further enhanced, the temperature stability of the chip in the working process is ensured, and the reliability and service life of the chip are improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a front structure schematic view of the substrate in the plane grid array packaging structure in the utility model embodiment;

[0022] Figure 2 It is a back structure schematic view of the substrate in the plane grid array packaging structure in the utility model embodiment;

[0023] Figure 3 It is a structure schematic view of the substrate and the plastic package in the plane grid array packaging structure in the utility model embodiment.

[0024] The signs are as follows:

[0025] 1-substrate, 2-first base island, 3-second base island, 4-pin pad, 5-microstrip line, 6-back pad, 7-bonding wire, 8-ink plug hole, 100-plastic package, 101-light-absorbing layer. DETAILED DESCRIPTION

[0026] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the embodiments described below are only a part of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0027] Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the accompanying drawings is intended to represent only selected embodiments of the present application and not limit the scope of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application.

[0028] It should be understood that, in the description of the embodiments of the present application, the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like are based on the orientations or positional relationships shown in the drawings, and are merely for the convenience of describing the embodiments of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the embodiments of the present application. In addition, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0029] In the description of the embodiments of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "set", "mount", "connected", "connected" should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0030] Referring to Figures 1-3The utility model provides a plane grid array packaging structure, including substrate 1, substrate 1 front surface is provided with electrically connected first base island 2, second base island 3 and pin pad 4, substrate 1 back surface is provided with back pad 6, pin pad 4 and back pad 6 between electrically connected. This embodiment takes LGA2828 package as an example to make further explanation.

[0031] Multiple first base islands 2 and multiple pin pads 4 are arranged on the periphery of the second base island 3. The substrate 1 is encapsulated in a plastic encapsulation body 100. The plastic encapsulation body 100 can be formed into a desired shape and size by injection molding, die casting or other molding processes, thereby forming a packaging shell.

[0032] In order to better dissipate heat, the substrate 1 can also be provided with a heat dissipation module for heat dissipation.

[0033] Optionally, the second base island 3 is arranged at the middle of the substrate 1, and the multiple first base islands 2 are arrayed on the periphery of the second base island 3.

[0034] Optionally, the multiple pin pads 4 are arranged on the substrate 1 between the second base island 3 and the first base island 2.

[0035] Optionally, the pin pad 4 and the second base island 3 are connected by a bonding wire 7.

[0036] The first base island 2 and the pin pad 4 are connected by a microstrip line 5.

[0037] Optionally, the substrate 1 has multiple ink plug holes 8 evenly distributed on the edges, and the first base island 2 and / or the pin pad 4 are connected to the ink plug holes 8 by the microstrip line 5.

[0038] The back pad 6 is connected to the ink plug hole 8. As shown in Figure 1 、 Figure 2 The number of back pads 6 is equal to the number of ink plug holes 8, and the back pad 6 is connected to the first base island 2 and the pin pad 4 on the front surface through the ink plug hole 8.

[0039] Optionally, the surface of the plastic encapsulation body 100 is covered with a light-absorbing layer 101 or a light-reflecting layer.

[0040] Specifically, in order to prevent the light projection from affecting the chips or circuits inside the LGA2828 package, a material with good light shielding performance can be selected. For example, a light shielding agent can be added to the plastic packaging material, or a material with light shielding properties can be used. At the same time, in the design of the packaging structure, a multi-layer structure, a light shielding cover, etc. can be used to reduce the entry of external light. The surface of the plastic package 100 can also be treated in a special way, such as adding a reflective coating or a light absorbing layer 101, which can also prevent light projection. The reflective coating can reflect the incident light, reducing the entry of light into the package; the light absorbing layer 101 can absorb light, avoiding reflection and scattering of light on the surface of the package.

[0041] Optionally, the first base island 2 is provided with an LED chip on the surface.

[0042] The second base island 3 is provided with an IC chip on the surface.

[0043] The LGA2828 packaging structure provided by the embodiment can realize more connection points in a limited space through the reasonable layout of the first base island 2 and the pin pad 4 and the high-density grid array design, thereby improving the connection density between the chip and the substrate and helping to realize high-density integration of electronic devices. At the same time, this packaging form is also conducive to reducing the size and weight of the entire electronic system, meeting the demand for miniaturization of portable devices, wearable devices, etc.

[0044] The LGA2828 packaging structure provided by the embodiment is very suitable for surface mounting technology, and the regular pin array structure facilitates precise picking, positioning and welding operations by automated equipment, thereby greatly improving production efficiency and welding quality and reducing production cost.

[0045] The LGA2828 packaging structure provided by the embodiment usually leaves a certain gap between the IC chip and / or the LED chip and the substrate, which provides better conditions for heat dissipation. In addition, the LGA package can also conveniently add a heat dissipation backboard or a heat dissipation module to further enhance the heat dissipation effect, ensure the temperature stability of the chip during operation, and improve the reliability and service life of the chip. For example, in some high-performance computing devices, graphics processing chips and other application scenarios with high heat dissipation requirements, the heat dissipation advantage of the LGA package is embodied.

[0046] According to the needs, pin holes (not shown in the figure) can be provided on the plastic package 100, and the positions of the pin holes correspond to the positions of the chip pins, which are used to lead out the pins of the chip. The pins of the chip can be led out through the pin holes: metal leads or other means can be used to lead the pins of the chip from the inside of the package shell to the outside, so as to be connected with the external circuit. The number of pins can be set according to the needs. The pin holes are prior art, which will not be described here.

[0047] The above description is only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1.A planar grid array package structure, comprising: a substrate, a first base island, a second base island and a pin pad being disposed on a front surface of the substrate, a back pad being disposed on a back surface of the substrate, the pin pad being electrically connected with the back pad; a plurality of the first base islands and a plurality of the pin pads being disposed on a periphery of the second base island; the substrate being encapsulated in an encapsulation body, the back surface of the substrate further comprising a heat dissipation module. 2.The planar grid array package structure of claim 1, wherein: the second base island is disposed in a middle portion of the substrate, and a plurality of the first base islands are arrayed on a periphery of the second base island. 3.The planar grid array package structure of claim 2, wherein: a plurality of the pin pads are disposed on the substrate between the second base island and the first base islands. 4.The planar grid array package structure of claim 3, wherein: the pin pad and the second base island are connected by a bonding wire; and the first base island and the pin pad are connected by a microstrip line. 5.The planar grid array package structure of any one of claims 1-4, wherein: a plurality of ink holes are uniformly distributed on an edge of the substrate, the first base island and / or the pin pad are connected to the ink holes by a microstrip line; and the back pad is connected to the ink hole. 6.The planar grid array package structure of claim 5, wherein: a surface of the encapsulation body is covered by a light-absorbing layer or a light-reflecting layer. 7.The planar grid array package structure of claim 5, wherein: an LED chip is disposed on a surface of the first base island; and an IC chip is disposed on a surface of the second base island. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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