Semiconductor structure with through holes

Abstract

The utility model provides a semiconductor structure. The semiconductor structure comprises a substrate, a device layer above the substrate, an interconnection line structure above the device layer, a plurality of first through holes and a plurality of second through holes, wherein the first through holes and the second through holes extend and penetrate through the substrate, the device layer and the interconnection line structure. The device layer includes first and second device regions. From a top view, the first device region has a first side facing and spaced apart from a second side of the second device region. In a plan view, the first plurality of perforations are disposed along a third side of the first device region opposite the first side of the first device region, and the second plurality of perforations are disposed along a fourth side of the second device region opposite the second side of the second device region. Each of the perforations has a racetrack shape as viewed from a top view.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor structure with through hole. BACKGROUND

[0002] The integrated circuit (IC) industry has experienced exponential growth. IC material and design technology advances have yielded a number of generations of ICs, with each successive generation smaller and more complex than the previous. Generally, the shrinkage process can bring benefits by improving production efficiency and reducing associated costs.

[0003] Recent attempts have focused on through vias, such as through-silicon or through-substrate vias (TSVs). TSVs have been used in three-dimensional ICs (3D ICs) to transport power and / or electrical signals from one side of an IC silicon substrate to the other. Typically, a TSV is formed by etching a vertical via opening through a substrate and filling the via opening with a conductive material, such as copper. If the area used by TSVs occupies a significant portion of the entire space available for manufacturing an IC, scaling capability will be limited. On the other hand, smaller TSVs can increase resistance and consume additional power. Thus, while existing TSVs are generally adequate for their intended purpose, they are not perfect in all respects. SUMMARY

[0004] A semiconductor structure is provided. The semiconductor structure includes a substrate and a device layer disposed above the substrate. The device layer includes a first device region and a second device region. The first device region has a first side facing and spaced apart from a second side of the second device region, as viewed from a top view. The semiconductor structure further includes an interconnect structure disposed above the first device region and the second device region, and a first plurality of through holes and a second plurality of through holes extending through the substrate, the device layer, and the interconnect structure. The first plurality of through holes is disposed along a third side of the first device region opposite the first side of the first device region, and the second plurality of through holes is disposed along a fourth side of the second device region opposite the second side of the second device region, as viewed from the top view. Each of the first plurality of through holes and the second plurality of through holes has a racetrack shape, as viewed from the top view.

[0005] A semiconductor structure. The semiconductor structure includes a substrate and a device layer disposed above the substrate. The device layer includes a first device region and a second device region adjacent to the first device region. The semiconductor structure further includes an interconnect line structure disposed above the first device region and the second device region, a first through-silica via and a second through-silica via disposed along a first side of the first device region from a top view, and a third through-silica via and a fourth through-silica via disposed along a second side of the second device region from the top view. The first through-silica via and the second through-silica via are spaced apart from the third through-silica via and the fourth through-silica via via the first device region and the second device region. The first through-silica via, the second through-silica via, the third through-silica via, and the fourth through-silica via all extend through the substrate, the device layer, and the interconnect line structure. There is no through-silica via between the first device region and the second device region. Each of the first through-silica via, the second through-silica via, the third through-silica via, and the fourth through-silica via has an elongated shape from the top view.

[0006] A semiconductor structure. The semiconductor structure includes a device layer including a first device region and a second device region, an interconnect line structure disposed above the first device region and the second device region, a first through-silica via disposed on a first side of the first device region and a second through-silica via disposed on a second side of the second device region opposite the first side of the first device region. The first through-silica via and the second through-silica via both extend through the device layer and the interconnect line structure. Each of the first through-silica via and the second through-silica via has a racetrack shape including a middle portion and two circular end portions sandwiching the middle portion from a top view. The middle portion is parallel to the first side of the first device region.

[0007] So that the foregoing features and advantages of the present application can be understood in more detail, a more particular description will be rendered by reference to example implementations that are illustrated in the appended drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0008] When taken in conjunction with the drawings, the following detailed description of the application will illustrate and explain the principles of the application. Figure 1 The application will be best understood from the following detailed description when read in conjunction with the accompanying drawings. To the extent that the figures illustrate shapes of the various features drawn to size, it should be understood that various sizes of the features shown in the figures can be increased or decreased as is appropriate in discussion of the clearness of the discussion.

[0009] Figure 1 is a schematic top view of a portion of a semiconductor structure according to various aspects of the present application.

[0010] Figure 2 , Figure 3are schematic top views of a semiconductor structure portion according to various aspects of the present invention Figure 1 are schematic cross-sectional views of a semiconductor structure portion along A-A and B-B cross-sectional lines, respectively.

[0011] Figure 4A are schematic top views of a semiconductor structure portion according to various aspects of the present invention Figure 1 are schematic top views of a via.

[0012] Figure 4B , Figure 4C and Figure 4D are schematic top views of a via according to alternative embodiments of the present invention Figure 1 are schematic top views of a via.

[0013] Figure 5 and Figure 6 are schematic top views of a semiconductor structure portion according to alternative embodiments of the present invention Figure 1 are schematic cross-sectional views of a semiconductor structure portion along A-A and B-B cross-sectional lines, respectively.

[0014] Figure 7 , Figure 8 , Figure 9 and Figure 10 are schematic cross-sectional views of a semiconductor structure portion along B-B cross-sectional line when the semiconductor structure is connected with one or more dies in a package according to various aspects of the present invention Figure 1 are schematic cross-sectional views of a semiconductor structure portion along B-B cross-sectional line when the semiconductor structure is connected with one or more dies in a package according to various aspects of the present invention

[0015] Figure 11 , Figure 12 and Figure 13 are schematic top views of alternative semiconductor structure portions according to various aspects of the present invention

[0016] BRIEF DESCRIPTION OF DRAWINGS

[0017] 100, 600, 700, 800: semiconductor structure

[0018] 102, 202, 302, 560: substrate

[0019] 104, 204, 304: device layer

[0020] 105, 205, 305: device region

[0021] 105a: first device region

[0022] 105b: second device region

[0023] 106: dielectric structure

[0024] 108: backside interconnect line structure

[0025] 112, 116: passivation layer

[0026] 115: perforated structure

[0027] 118, 218, 318: interconnect line structure

[0028] 119: fill layer

[0029] 120, 120a, 120b, 160: TSV

[0030] 122, 162: guard ring

[0031] 122a, 122b, 123a, 123b, 123c, 123d, 150, 155: side

[0032] 123: middle portion

[0033] 124, 265, 365: dielectric layer

[0034] 125: first side

[0035] 127: end

[0036] 128a, 228a, 328a, 428a: metal line

[0037] 128b, 228b, 328b: metal via

[0038] 129: circle

[0039] 130: third side

[0040] 132: dummy region

[0041] 135: fourth side

[0042] 140: second side

[0043] 145: power line metal line

[0044] 200, 300, 400: die

[0045] 255, 355, 455, 555: conductive feature

[0046] 450: package

[0047] 550: logic die

[0048] 550PDS: power distribution structure

[0049] 565: bump structure

[0050] 570, 575, 575a, 575b, 575c, 580: memory die

[0051] Areas 615, 615a, 615b, 715, 715a, 715b, 715c, 815, 815a, 815b, 815c, 815d, 815e

[0052] H1: Height

[0053] D1 Distance

[0054] D2: Width

[0055] D3: Length

[0056] D4: Total Length

[0057] P: Central angle

[0058] R: radius

[0059] FS: Front

[0060] BS: Backside

[0061] AA: AA section line

[0062] BB: BB section line

[0063] X, Y, Z: Axes Detailed Implementation

[0064] This invention relates generally to semiconductor structures, and more specifically, to perforations in semiconductor structures.

[0065] This utility model provides numerous different embodiments or examples for implementing various features of the present utility model. Specific examples of components and arrangements are described below to simplify the present utility model. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various embodiments of the present utility model. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0066] Moreover, spatial or directional terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as drawn in the figures. The spatial and directional terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial or directional terms used herein are to be interpreted accordingly.

[0067] Further, when describing the numerical or numerical range with "about", "approximately" and the like, the term is intended to encompass numbers within a reasonable range given the inherent variability of the manufacturing process. For example, the numerical or numerical range encompasses a reasonable range of numbers including the number, such as + / - 10% of the number, based on known manufacturing errors associated with manufacturing features having the relevant properties. For example, a layer of material having a thickness of "about 5 nanometers" can encompass a range of sizes from 4.25 nanometers to 5.75 nanometers, where + / - 15% of the manufacturing tolerance associated with depositing the layer of material is known to one of skill in the art. Still further, the present disclosure can repeat reference numerals and / or letters in each figure for the elements depicted in the figures. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed herein.

[0068] Interconnect line structures electrically couple various components (e.g., transistors, resistors, capacitors, and / or inductors) fabricated on a substrate so that the various components can operate in a manner specified by design requirements. Interconnect line structures include a combination of multiple dielectric layers and multiple conductive layers configured to provide electrical signal routing. The conductive layers include vias and contact features that provide multiple vertical connections and conductive lines that provide multiple horizontal connections. In some embodiments, the interconnect line structures can have multiple metal layers (or metallization layers) that are vertically interconnected by vias or contact features. During operation of an IC device, the interconnect line structures route multiple signals between the multiple components of the IC device and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the multiple components. The interconnect line structures are formed in a back-end-of-the-line (BEOL) process, which typically follows a front-end-of-the-line (FEOL) process to form multiple active devices (e.g., transistors) on a substrate and a middle-end-of-the-line (MEOL) process to form multiple source / drain contact plugs and multiple gate contact plugs.

[0069] In some embodiments, it is desirable to provide vertical interconnections that extend through the interconnect line structures and / or the substrate of multiple IC devices. Such vertical interconnections can be referred to as through vias, through-silicon vias (TSVs), or through-substrate vias (TSVs) because they extend through a semiconductor die. The term TSV in this disclosure broadly encompasses multiple via structures that provide direct routing between a die frontside and a die backside, and vice versa.

[0070] TSVs can provide electrical connections that offer an alternative to other interconnect technologies, such as wire bonds. In some implementations, TSVs allow for the fabrication of 3D packages or integrated circuits that provide for multiple devices on different substrates to be interconnected. TSVs can provide robust interconnects that offer higher device densities and shorter interconnect paths. The introduction of TSVs can improve device performance, such as reducing RC delay. There are a variety of semiconductor devices suitable for TSVs, including semiconductor devices of the present disclosure, and include, but are not limited to, such as complementary metal-oxide-semiconductor image sensors (CIS), three-dimensional packages (3D packages), three-dimensional integrated circuits (3D ICs), integrated-fan-out (InFO) packages, chip-on-wafer-on-substrate (CoWoS) packages, system-on-integrated chip (SoIC) packages, three-dimensional integrated circuits (3DIC) packages, system-on-chip (SoC) packages, microelectromechanical systems (MEMS) devices, radio frequency (RF) devices, wafer-on-wafer (WoW) devices, and the like.

[0071] During the formation of TSVs, moisture can attack the metal material in the areas that house the TSVs. Guard rings have been developed as structural barriers around the TSVs to prevent moisture from attacking the metal material in these areas. In addition, guard rings can also provide an electrical barrier to protect nearby components from electrical interference caused by the current passing through the TSVs.

[0072] TSVs can be located in a TSV region that is close to the device region. If the TSV region takes up a large portion of the entire space available for fabricating an IC, then the scaling capability will be limited. On the other hand, smaller TSVs require a smaller TSV region, which can result in an increase in the resistance of the TSVs and consume additional power.

[0073] A semiconductor structure including a plurality of TSVs is provided. The plurality of TSVs have a plurality of elongated shapes (e.g., racetrack shapes) from a top view. In some embodiments, the semiconductor structure includes a device layer and an interconnect line structure above the device layer. The device layer includes a first device region and a second device region adjacent to the first device region. The plurality of TSVs extend through the device layer and the interconnect line structure. The plurality of TSVs can be arranged along a side of each of the first device region and the second device region. From a top view, the TSVs can increase an area, thus reducing resistance and wasted energy during operation, and can reduce a number of TSVs required in the semiconductor structure. In some embodiments, a space between the first device region and the second device region can be free of TSVs, thus can reduce the space, and can reduce a footprint of the semiconductor structure. In some embodiments, the TSVs also provide flexibility with respect to a TSV height, such that a thickness of the semiconductor structure can be reduced.

[0074] Various aspects of the present application will now be described in more detail, with reference to the drawings. In this regard, Figure 1 is a schematic top view of a portion of a semiconductor structure 100 according to various aspects of the present application. Figure 2 、 Figure 3 is a schematic cross-sectional view of a portion of the semiconductor structure 100 according to various aspects of the present application. Figure 1 are schematic cross-sectional views of a portion of the semiconductor structure 100 along the A-A and B-B cross-sectional lines, respectively, according to alternative embodiments of the present application. Figure 4A to Figure 4C is a schematic top view of a portion of a semiconductor structure 100 according to various aspects of the present application. Figure 1 are schematic top views of a via structure 115. Figure 5 and Figure 6 are schematic cross-sectional views of a portion of the semiconductor structure 100 along the A-A and B-B cross-sectional lines, respectively, according to alternative embodiments of the present application. Figure 1 are schematic cross-sectional views of a portion of the semiconductor structure 100 along the A-A and B-B cross-sectional lines, respectively, according to alternative embodiments of the present application. Figure 7 to Figure 10 is a schematic cross-sectional view of the B-B cross-sectional line of a portion of the semiconductor structure 100 according to various aspects of the present application when the semiconductor structure is connected with one or more dies in a package. Figure 1 is a schematic cross-sectional view of the B-B cross-sectional line of a portion of the semiconductor structure 100 according to various aspects of the present application when the semiconductor structure is connected with one or more dies in a package. Figure 11 、 Figure 12 and Figure 13 are schematic top views of a portion of alternative semiconductor structures 600, 700 and 800 according to various aspects of the present application. For the avoidance of doubt, Figure 1 to Figure 13 the X, Y and Z directions of FIG. 1 are perpendicular to each other. Throughout this document, like reference numerals refer to like features, unless explicitly stated otherwise.

[0075] The semiconductor structure 100 shown in the drawings of the present utility model is simplified, and all the features in the semiconductor structure 100 are not shown or described in detail. The semiconductor structure 100 shown in the drawings can be a part of an IC chip, a system on chip (SoC) or a part thereof, which can include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFET), n-type field effect transistors (NFET), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components or combinations thereof.

[0076] Reference Figure 2 to Figure 3semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Alternatively, the substrate 102 can be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the semiconductor structure 100, the substrate 102 can include various doped regions (not shown). In some embodiments, the substrate 102 includes a plurality of p-type doped regions (e.g., a plurality of p-wells) doped with a plurality of p-type dopants, such as boron (e.g., BF2), indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 102 includes a plurality of n-type doped regions (e.g., a plurality of n-wells) doped with a plurality of n-type dopants, such as phosphorus (P), arsenic (As), other n-type dopants, or a combination thereof. In some embodiments, the substrate 102 includes a plurality of doped regions formed with a combination of a plurality of p-type dopants and a plurality of n-type dopants. The various doped regions can be formed directly on and / or in the substrate 102, for example, to provide p-well structures, n-well structures, dual-well structures, raised structures, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the various doped regions.

[0077] Reference is made to Figure 1 to Figure 3The semiconductor structure 100 includes a device layer 104. The device layer 104 can be disposed above the substrate 102. The device layer 104 includes a plurality of devices (e.g., transistors, resistors, capacitors, diodes, and / or inductors) and / or a plurality of device components (e.g., gate structures and / or source / drain features). In some embodiments, the device layer 104 includes a plurality of doped regions (e.g., source / drain features) disposed above the substrate 102. The transistors include p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffusion MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The transistors can be planar transistors or multi-gate transistors, such as fin-like FETs (FinFETs) or gate-all-around (GAA) transistors. Gate-all-around transistors can include channel regions of various shapes, including nanowires, nanobars, or nanosheets, all of which are collectively referred to as nanosheets. In some embodiments, the transistors include a suspended nanostructure (channel layer) disposed between source / drain features and a gate structure, where the gate structure wraps around and / or surrounds the suspended nanostructure. Each gate structure has a metal gate structure that is formed from a gate disposed above a gate dielectric and from a plurality of gate spacers disposed along a plurality of sidewalls of the gate structure.

[0078] In some embodiments, the device layer 104 includes isolation of multiple features (not shown) to isolate various regions of the semiconductor structure 100, such as various device regions. In some embodiments, the device layer 104 includes multiple dielectric layers (not shown), such as multiple interlayer dielectric (ILD) layers and multiple etch stop layers (ESLs) above multiple devices and / or multiple device components. The interlayer dielectric layers can include a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) formed silicon glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low dielectric materials include fluorosilicate glass (FSG), carbon doped silicon oxide, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, benzocyclobutene (BCB), polyimide, other low dielectric material, or combinations thereof. The etch stop layers can include silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon elements, other suitable material, or combinations thereof.

[0079] Referring still to Figure 1 and Figure 3The device layer 104 includes a first device region 105a and a second device region 105b adjacent to the first device region 105a. The first device region 105a and the second device region 105b can be referred to individually or collectively as device regions 105, depending on the context. In some embodiments, the first device region 105a and the second device region 105b each include a memory macro, which is a type of memory circuit including at least an array of memory cells configured to store data, and one or more circuits configured to control data input, output, and storage operations (details not shown). In some embodiments, the plurality of memory cells of the memory macro includes static random-access memory (SRAM) cells. In various embodiments, the static random-access memory cells include five-transistor (5T) SRAM cells, six-transistor (6T) SRAM cells, eight-transistor (8T) SRAM cells, nine-transistor (9T) SRAM cells, or SRAM cells having other transistor counts. In various embodiments, the plurality of memory cells of the memory macro includes dynamic random-access memory (DRAM) cells, read-only memory (ROM) cells, non-volatile memory (NVM) cells, or other types of memory cells capable of storing data.

[0080] In some embodiments, referring to Figure 1From a top view, the semiconductor structure 100 includes a first plurality of via structures 115 arranged along a first side 125 of the first device region 105a and a second plurality of via structures 115 arranged along a second side 140 of the second device region 105b. For simplicity, the via structures 115 are also referred to as through-silicon via (TSV) structures 115 or through-substrate via (TSV) structures 115, regardless of whether the semiconductor structure 100 includes silicon or a substrate. The plurality of TSV structures 115 is isolated from a plurality of circuits (e.g., a plurality of memory macros) of the first device region 105a and the second device region 105b. The first plurality of TSV structures 115 is spaced apart from each other. The second plurality of TSV structures 115 is spaced apart from each other. The first device region 105a also includes a third side 130 opposite the first side 125. The second device region 105b also includes a fourth side 135 opposite the second side 140. In the depicted embodiment, the first side 125, the second side 140, the third side 130, and the fourth side 135 extend along the X-direction. The third side 130 is adjacent to the fourth side 135, and there is a distance Dl between the third side 130 and the fourth side 135. Dl can be greater than 0 micrometers to about 20 micrometers. This range is not randomly decided. If Dl is too small (e.g., 0 micrometers), the first device region 105a and the second device region 105b can not be sufficiently isolated from each other. If Dl is too large, the footprint of the IC chip and the cost associated therewith can be unnecessarily increased. In embodiments, by having the plurality of TSV structures 115 described herein, the first and second pluralities of TSV structures 115 enable power and / or signal transmission, and thus the space between the first device region 105a and the second device region 105b is free of TSV structures. Details of the TSV structures 115 will be described below.

[0081] In some embodiments, the device layer 104 also includes a plurality of dummy regions 132 disposed between and / or around the plurality of TSV structures 115 and the plurality of adjacent device regions 105 (e.g., the first device region 105a and the second device region 105b). The plurality of dummy regions 132 can include a plurality of dielectric materials that isolate one device region 105 (e.g., the first device region 105a) from another device region 105 (e.g., the second device 105b). The plurality of dummy regions 132 can include a plurality of dielectric layers, such as similar to the interlayer dielectric layers and etch stop layers described above. The dummy regions 132 can include dummy conductive features and / or dummy devices or dummy device components.

[0082] In some embodiments, please refer to Figure 2 and Figure 3semiconductor structure 100 includes an interconnect line structure 118 (also referred to as a front-side interconnect line structure 118) over the device layer 104. The interconnect line structure 118 electrically couples various devices and / or components of the device layer 104 so that the various devices and / or components can function in a manner specified by design requirements. In some embodiments, the interconnect line structure 118 includes a contact layer (contact level), a via layer 0 (via 0 level), a metal layer 0 (metal 0 level), a via layer 1 (via 1 level), a metal layer 1 (metal 1 level),..., a via layer x (via x level), and a metal layer x (metal x level). The present disclosure contemplates that the interconnect line structure 118 has more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the interconnect line structure 118 is x, where x is an integer ranging from 2 to 10. Each level of the interconnect line structure 118 includes a plurality of conductive features (e.g., a plurality of metal lines 128a, a plurality of metal vias 128b, and / or a plurality of metal contacts) disposed in a plurality of dielectric layers 124 (e.g., including interlayer dielectric layers and etch stop layers similar to those described above). In some embodiments, the plurality of conductive features of the interconnect line structure 118 at the same level (e.g., metal 0 level) are formed simultaneously. In some embodiments, the plurality of conductive features of the interconnect line structure 118 at the same level have a plurality of top surfaces that are substantially planar with each other and / or a plurality of bottom surfaces that are substantially planar with each other. The contact level includes a plurality of source / drain contacts disposed in the plurality of dielectric layers 124; the via 0 level includes a plurality of gate vias, a plurality of source / drain contact vias, and a plurality of landing contacts disposed in the plurality of dielectric layers 124; the metal 0 level includes a plurality of metal lines (metal 0) disposed in the plurality of dielectric layers 124, where the plurality of gate vias connect the plurality of gate structures to the plurality of metal lines (metal 0), the plurality of source / drain vias connect the plurality of source / drain features to the plurality of metal lines (metal 0), and the plurality of landing contacts connect the plurality of gate structures and the plurality of source / drain together and to the plurality of metal lines (metal 0); the via 1 level includes a plurality of vias (via 1) disposed in the plurality of dielectric layers 124, where the plurality of vias (via 1) connect the plurality of metal lines (metal 0) to the plurality of metal lines (metal 1); the metal 1 level includes a plurality of metal lines (metal 1) disposed in the plurality of dielectric layers 124;... ; the via x level includes a plurality of vias (via x) disposed in the plurality of dielectric layers 124, where the plurality of vias (via x) connect the plurality of metal lines (metal (x-1)) to the plurality of metal lines (metal x). For clarity, Figure 2 and Figure 3 have been simplified to better understand the inventive concept of the present disclosure. Additional features can be added in various layers of the semiconductor structure 100, and some of the features described can be replaced, modified, or eliminated in other embodiments of the semiconductor structure 100.

[0083] Please refer to Figure 1and Figure 2 In an embodiment, the plurality of conductive features of the interconnect line structure 118 includes a plurality of metal lines 145. The plurality of metal lines 145 can be a plurality of power lines that transmit power to the semiconductor structure 100, and are referred to as the plurality of power lines 145. In some embodiments, at least one metal line 145 is grounded. In some embodiments, the plurality of metal lines 145 extends over the first device region 105a and the second device region 105b along the Y direction. In the described embodiment, each metal line 145 is disposed between a plurality of adjacent TSV structures 115 of the first plurality of TSV structures 115 and between a plurality of adjacent TSV structures 115 of the second plurality of TSV structures 115.

[0084] Reference is made to Figure 1 to Figure 3 In an embodiment, the plurality of TSV structures 115 each includes a via 120 and a guard ring 122 surrounding the via 120. For simplicity, the via 120 is also referred to as a TSV 120, regardless of whether the semiconductor structure 100 includes silicon or a substrate. In an embodiment, the plurality of TSVs 120 includes a plurality of TSVs 120a and a plurality of TSVs 120b, which can be referred to individually or collectively as TSV(s) 120, depending on the context. The plurality of TSVs 120 can provide an electrical path from the front side FS of the semiconductor structure 100 to the backside BS of the semiconductor structure 100. For example, an electrical path is provided from the top surface TS of the semiconductor structure 100 to and / or through the substrate 102. In some embodiments, the plurality of TSVs 120 is used for transmission of power and / or input / output of electrical signals. In an example, the plurality of TSVs 120a is used for transmission of power and / or input of electrical signals, and the plurality of TSVs 120b is used for transmission of power and / or output of electrical signals. Reference is made to Figure 2 and Figure 3 As shown, the plurality of TSVs 120 extends through the interconnect line structure 118, the device layer 104, and the substrate 102.

[0085] In some embodiments, the plurality of TSVs 120 each include a fill layer 119 (to be described below) and a passivation layer 116 that horizontally contacts and surrounds the fill layer 119. In the depicted embodiment, in the same TSV structure 115, the passivation layer 116 is surrounded by the plurality of dielectric layers 124 and the plurality of dummy regions 132, and is spaced apart from the guard ring 122. In some other embodiments, the passivation layer 116 is surrounded by and directly contacts the guard ring 122. The passivation layer 116 can isolate the guard ring 122 and the fill layer 119. The passivation layer 116 can include an oxide, such as silicon oxide; a nitride, such as silicon nitride; an oxynitride, such as silicon oxynitride; a combination thereof; and / or other suitable materials. The passivation layer 116 can have a different composition than the plurality of dielectric materials of the plurality of dielectric layers 124 and the plurality of dummy regions 132. The passivation layer 116 can be deposited by a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, reduced pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, other suitable methods, or a combination thereof.

[0086] The plurality of guard rings 122 can extend through the interconnect line structure 118. In the depicted embodiment, the plurality of guard rings 122 extend through the device layer 104. In some embodiments, the plurality of guard rings 122 extend into at least a portion of the device layer 104. In some embodiments, the guard ring 122 includes a continuous structure that extends from a bottom of the plurality of dummy regions 132 of the device layer 104 to a top surface of the plurality of dielectric layers 124 of the interconnect line structure 118. In some embodiments, the interconnect line structure 118 includes via x layers (e.g., via 0, via 1, via 2, etc.) and metal x layers (e.g., metal 0, metal 1, metal 2, etc.). In embodiments, the guard ring 122 includes a plurality of portions / layers formed on each via x layer and each metal x layer in the interconnect line structure 118, and a plurality of portions / layers formed in the plurality of dummy regions 132. In the same TSV structure, the guard ring 122 can be electrically isolated from the TSV 120, but still provides a multi-layer structure and a power barrier that surrounds the TSV 120.

[0087] As the word “ring” as used in the guard ring 122 does require a structure that has a circular inner edge and outer edge and is composed of a plurality of curves. More specifically, the guard ring 122 can be various shapes that surround the TSV 120 from a top view. Figure 4A to 4D Various embodiments of the TSV structure 115 are depicted from a top view. The TSV 120 can have an elongated shape, such as a rectangular shape and a racetrack shape. In Figure 4AIn the illustrated embodiment, the TSVs 120 and the guard ring 122 each have a rectangular shape. Two sides 123a and 123b of each TSV 120 can extend along the X direction. The TSVs 120 can have a width D2 along the Y direction of about 1 micrometer to about 10 micrometers and a length D3 along the X direction of about 1 micrometer to about 55 micrometers. The ranges of D2 and D3 are not randomly determined. If D2 and / or D3 is less than the lower end of the range, the resistance of the TSVs 120 can be too great, resulting in too much wasted energy. If D2 and / or D3 is greater than the upper end of the range, the footprint of the semiconductor structure 100 and the cost associated therewith can be unnecessarily increased. In Figure 4B In the illustrated embodiment, the TSVs 120 and the guard ring 122 each have a rectangular shape. Two sides 123a and 123b of each TSV 120 can extend along the X direction. The TSVs 120 can have a width D2 along the Y direction of about 1 micrometer to about 10 micrometers and a length D3 along the X direction of about 1 micrometer to about 55 micrometers. The ranges of D2 and D3 are not randomly determined. If D2 and / or D3 is less than the lower end of the range, the resistance of the TSVs 120 can be too great, resulting in too much wasted energy. If D2 and / or D3 is greater than the upper end of the range, the footprint of the semiconductor structure 100 and the cost associated therewith can be unnecessarily increased. In Figure 4A In the illustrated embodiment, the TSVs 120 and the guard ring 122 each have a rectangular shape. Two sides 123a and 123b of each TSV 120 can extend along the X direction. The TSVs 120 can have a width D2 along the Y direction of about 1 micrometer to about 10 micrometers and a length D3 along the X direction of about 1 micrometer to about 55 micrometers. The ranges of D2 and D3 are not randomly determined. If D2 and / or D3 is less than the lower end of the range, the resistance of the TSVs 120 can be too great, resulting in too much wasted energy. If D2 and / or D3 is greater than the upper end of the range, the footprint of the semiconductor structure 100 and the cost associated therewith can be unnecessarily increased. In Figure 4C In the illustrated embodiment, the TSVs 120 and the guard ring 122 each have a rectangular shape. Two sides 123a and 123b of each TSV 120 can extend along the X direction. The TSVs 120 can have a width D2 along the Y direction of about 1 micrometer to about 10 micrometers and a length D3 along the X direction of about 1 micrometer to about 55 micrometers. The ranges of D2 and D3 are not randomly determined. If D2 and / or D3 is less than the lower end of the range, the resistance of the TSVs 120 can be too great, resulting in too much wasted energy. If D2 and / or D3 is greater than the upper end of the range, the footprint of the semiconductor structure 100 and the cost associated therewith can be unnecessarily increased. In Figure 4BDifferences of the TSV structure 115 include that the guard ring 122 has a polygonal shape (e.g., an octagonal shape as shown). Two parallel sides 122a and 122b of the guard ring 122 can be parallel to two sides 123c and 123d of the middle portion 123 of the TSV 120 and extend along the X direction. Note that while the TSV 120 is formed, the TSV 120 does not have to be centered with (e.g., share a center axis with) the guard ring 122 of the same TSV structure 115. The TSV 120 can be offset to one side of the guard ring 122. In the embodiment as shown, the TSV 120 is offset to the left side of the guard ring 122. In other embodiments, the TSV 120 can be offset to the right side of the guard ring 122. Figure 4D In the embodiment as described, the TSV structure 115 includes the guard ring 122 and two TSVs 120 surrounded by the guard ring 122. The two TSVs 120 can be arranged side by side along the X direction. In some other embodiments, the TSV structure 115 includes the guard ring 122 and more than two TSVs 120 surrounded by the guard ring 122. The more than two TSVs can be arranged along the X direction. The multiple TSVs 120 can be similar as described above. The guard ring 122 can have a rectangular shape as shown. In other embodiments, the guard ring 122 has other shapes, such as a polygonal shape as shown. Figure 4D In the embodiment as described, the TSV structure 115 includes the guard ring 122 and two TSVs 120 surrounded by the guard ring 122. The two TSVs 120 can be arranged side by side along the X direction. In some other embodiments, the TSV structure 115 includes the guard ring 122 and more than two TSVs 120 surrounded by the guard ring 122. The more than two TSVs can be arranged along the X direction. The multiple TSVs 120 can be similar as described above. The guard ring 122 can have a rectangular shape as shown. In other embodiments, the guard ring 122 has other shapes, such as a polygonal shape as shown. Figure 4C By having the shapes and / or dimensions described above, the area of the TSV 120 is increased from a top view, and thus, to maintain the designed TSV volume, the height of the TSV 120 along the Z direction can be reduced, which can reduce the overall height of the semiconductor structure 100. The TSV 120 described herein can be more flexible in its height and can have a height H1 of about 2 microns to about 200 microns.

[0088] In embodiments, the formation of the TSVs 120 includes patterning, etching the TSV openings, and filling the TSV openings with the conductive material(s). In some embodiments, the TSVs 120 are formed after the formation of the guard rings 122. The patterning process can include a photolithography process and / or an etching process. For example, forming the plurality of TSV openings includes performing a photolithography process to form a patterned photoresist layer over the plurality of dielectric layers 124, and performing an etching process to transfer the pattern defined by the patterned photoresist layer to the plurality of dielectric layers 124 and the underlying multilayers (e.g., the plurality of dummy regions 132 and / or the substrate 102). The photolithography process can include forming a photoresist layer over the plurality of dielectric layers 124 (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using a photomask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiant energy (e.g., ultraviolet light, deep ultraviolet light, or extreme ultraviolet light), where the photomask blocks, transmits, and / or reflects the radiation to the photoresist layer, depending on the photomask and / or the type of photomask (e.g., a binary mask, a phase shift mask, or an extreme ultraviolet mask), such that an image is projected onto the photoresist layer corresponding to the photomask pattern. As the photoresist layer is sensitive to the radiant energy, depending on the characteristics of the photoresist layer and the characteristics of the developer used in the development process, the exposed portions of the photoresist layer undergo a chemical change, and the unexposed (or non-exposed) portions of the photoresist layer are dissolved during the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the photomask. The etching process uses the patterned photoresist layer as an etch mask when removing portions of the plurality of dielectric layers 124 and the underlying multilayers. The etching process can include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. After the etching process, the patterned photoresist layer is removed from the plurality of dielectric layers 124, e.g., by a photoresist stripping process.

[0089] The TSV openings are then filled with various layers including a passivation layer (e.g., passivation layer 116) and a fill layer 119 (e.g., a plurality of barrier layers and a conductive fill material(s)). In some embodiments, the plurality of barrier layers (not depicted) can include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), aluminum nitride (AIN), or a combination thereof. The conductive fill material(s) can include copper (Cu), aluminum (Al), cobalt (Co), copper alloys, tantalum (Ta), titanium (Ti), or tungsten (W). In one embodiment, the plurality of barrier layers includes titanium nitride (TiN) and the conductive fill material includes copper (Cu). The plurality of barrier layers can be deposited using physical vapor deposition, chemical vapor deposition, metal organic chemical vapor deposition, atomic layer deposition, or a combination thereof. The conductive fill material(s) can then be deposited using electroplating, physical vapor deposition, chemical vapor deposition, electroless plating, or a suitable method. In one embodiment, the conductive fill material(s) is formed using electroplating. In this embodiment, a seed layer can be deposited over the semiconductor structure 100 (including over the plurality of surfaces of the plurality of barrier layers) using physical vapor deposition or a suitable process after the barrier layers are formed. The conductive fill material(s) can then be deposited over the seed layer using electroplating. In embodiments where electroplating is used, the seed layer can include copper (Cu), titanium (Ti), or a combination thereof, and the metal fill can include copper (Cu). The seed layer can be considered part of the conductive fill material(s). After the TSV openings are filled with the conductive fill material(s), a planarization process can remove excess material.

[0090] In some embodiments, the substrate 102 is then thinned from the backside to expose the end of the TSV 120. The thinning can include polishing and grinding the substrate 102 to expose the bottom surface of the TSV 120. Once the TSV 120 is exposed, the TSV 120 extends completely through the interconnect line structure 118, the device layer 104, and the substrate 102.

[0091] In some other embodiments, please refer to Figure 5 and Figure 6 The semiconductor structure 100 includes a backside interconnect line structure 108 below the device layer 104. In some embodiments, the semiconductor structure 100 also includes a passivation layer 112 below the backside interconnect line structure 108. In embodiments, the substrate 102 can be removed prior to forming the backside interconnect line structure 108. Please refer to Figure 1 and Figure 5 In embodiments, the plurality of conductive features of the backside interconnect line structure 108 includes a plurality of power lines 145. The plurality of power lines 145 differs from the plurality of power lines 145 of Figure 2 in that, Figure 5 the plurality of power lines 145 of extends along the Y direction below the first device region 105a and the second device region 105b. Another difference includesFigure 5 and Figure 6 A plurality of TSVs 120 extend through the interconnect line structure 118, the device layer 104, the backside interconnect line structure 108, and the passivation layer 112. A plurality of guard rings 122 can extend through the interconnect line structure 118, the device layer 104, and the backside interconnect line structure 108.

[0092] The backside interconnect line structure 108 can include a backside via 0 interconnect layer (backside via 0 level), a backside metal 0 layer (backside metal 0 level), a backside via 1 interconnect layer (backside via 1 level), and a backside metal 1 interconnect layer (backside metal 1 level). Each of the backside via 0 level, the backside metal 0 level, the backside via 1 level, and the backside metal 1 level can be referred to as a metal level. A plurality of metal lines formed at the backside metal 0 level can be referred to as a plurality of metal lines (backside metal 0). Similarly, a plurality of vias or a plurality of metal lines formed at the backside via 0 level, the backside via 1 level, and the backside metal 1 level can be referred to as a plurality of vias (backside via 0), a plurality of vias (backside via 1), and a plurality of metal lines (backside metal 1), respectively. The present disclosure contemplates that the backside interconnect line structure 108 has more or fewer interconnect layers and / or levels, for example, a total number of interconnect layers (levels) of the backside interconnect line structure 108 is M, where M is an integer ranging from 1 to 10. Each level of the backside interconnect line structure 108 includes a plurality of conductive features (e.g., metal lines, metal vias, and / or metal contacts, not shown) disposed in one or more dielectric layers (e.g., including interlayer dielectric layers and etch stop layers). The plurality of dielectric layers of the backside interconnect line structure 108 are collectively referred to as a dielectric structure 106. In some embodiments, the plurality of conductive features of the backside interconnect line structure 108 are formed at the same level (e.g., the backside metal 0 level) at the same time. In some embodiments, the plurality of conductive features of the backside interconnect line structure 108 at the same level have a plurality of top surfaces that are substantially planar to each other and / or a plurality of bottom surfaces that are substantially planar to each other.

[0093] In Figure 5 and Figure 6In the illustrated embodiment, the backside via 0 level includes a plurality of vias (backside via 0) formed below the device layer 104. For example, the plurality of vias (backside via 0) can include one or more backside source / drain vias formed directly below a plurality of source / drain features of the device layer 104 and coupled to those source / drain features through a silicide layer. The plurality of vias (backside via 0) can include one or more backside gate vias formed directly below a gate structure(s) of the device layer 104 and in direct contact with the gate structure(s) of the device layer 104. The backside metal 0 level includes a plurality of metal lines (backside metal 0) formed below the backside via 0 level. The plurality of backside gate vias connect the plurality of gate structures to the plurality of metal lines (backside metal 0), and the plurality of backside source / drain vias connect the plurality of source / drain features to the plurality of metal lines (backside metal 0). The backside metal 1 level includes a plurality of vias (backside via 1) disposed in the dielectric structure 106, where the plurality of vias (backside via 1) connect the plurality of metal lines (backside metal 0) to a plurality of metal lines (backside metal 1). The backside metal 1 level includes the plurality of metal lines (backside metal 1) formed below the backside via 1 level.

[0094] In some embodiments, the passivation layer 112 is formed by a suitable deposition process, such as a chemical vapor deposition process. The passivation layer 112 can be used to protect the device layer 104 and / or the backside interconnect line structure 108, for example, from exposure to contaminant particles, moisture, oxygen, etc. In some embodiments, the passivation layer 112 can include a dielectric layer. For example, the passivation layer 112 can include silicon oxide.

[0095] Interconnect lines to other conductive features, such as other metal lines, bond pads, conductive bumps, other input / output features, and / or other suitable interconnect lines, can be formed at the top and / or bottom of the plurality of TSVs 120. Figure 7 to Figure 10 Figures 1-3 illustrate cross-sectional views along the B-B line of the semiconductor structure when connected with one or more dies in a package, according to various aspects of the present disclosure. Figure 1 Figures 1-3 illustrate cross-sectional views along the B-B line of the semiconductor structure when connected with one or more dies in a package, according to various aspects of the present disclosure. Figure 7 to Figure 10 Some features, such as the passivation layer 116, are omitted for simplicity of illustration.

[0096] Reference is made to Figure 7In some embodiments, package 250 includes semiconductor structure 100 and die 200 disposed under semiconductor structure 100. Die 200 can include substrate 202, device layer 204 including a plurality of device regions 205, and interconnect line structure 218 including a plurality of metal lines 228a and a plurality of vias 228b, similar to that described above with respect to semiconductor structure 100. In some embodiments, die 200 is a logic die and the plurality of device regions 205 include a plurality of logic circuits. Logic dies are primarily responsible for processing data, executing instructions, and making decisions. The plurality of metal lines 228a and the plurality of vias 228b are electrically coupled to a plurality of devices and / or a plurality of device components of the plurality of device regions 205. In embodiments, TSVs 120 are electrically coupled to a plurality of topmost metal layers 228a of die 200. Package 250 can include a plurality of conductive features 255 connecting the plurality of TSVs 120 with the plurality of topmost metal layers 228a. The plurality of conductive features 255 can include a plurality of bond pads, a plurality of conductive bumps, and / or other suitable conductive features. Package 250 can also include a dielectric layer 265 surrounding the plurality of conductive features 255. Dielectric layer 265 can fill the space between semiconductor structure 100, the plurality of conductive features 255, and die 200. Dielectric layer 265 can be used for protection and insulation purposes. Dielectric layer 265 supports semiconductor structure 100 and prevents cracking of the plurality of joints between semiconductor structure 100, the plurality of conductive features 255, and die 200. In some embodiments, dielectric layer 265 is composed of epoxy (amine type, phenol type, anhydrite type, etc.), silicon filler, curing agent, additive, and / or hardener material.

[0097] See Figure 8 In some embodiments, package 350 includes semiconductor structure 100 and die 300 disposed above semiconductor structure 100. Die 300 can have a similar structure as die 200, except that die 300 is upside down compared to die 200. In embodiments, die 300 includes substrate 302, device layer 304 including a plurality of device regions 305, and interconnect line structure 318 including a plurality of metal lines 328a and a plurality of vias 328b similar to those described above. In some embodiments, die 300 is a logic die and the plurality of device regions 305 include a plurality of logic circuits. The plurality of metal lines 328a and the plurality of vias 328b are electrically coupled to a plurality of devices and / or a plurality of device components of the plurality of device regions 305. In embodiments, the plurality of TSVs 120 are electrically coupled to a plurality of bottommost metal layers 328a of die 300. Package 350 can include a plurality of conductive features 355 connecting the plurality of TSVs 120 with the plurality of bottommost metal layers 328a. The plurality of conductive features 355 can be similar to the plurality of conductive features 255 and embedded in a dielectric layer 365 similar to dielectric layer 265.

[0098] Referring to Figure 9 In some embodiments, package 450 includes two instances of semiconductor structure 100 side-by-side and die 400 disposed below the two instances of semiconductor structure 100. Some features, such as the plurality of guard rings 122, interconnect line structures 118 are omitted from Figure 9 the illustration for simplicity. The two semiconductor structures 100 can be adjacent. In embodiments, die 400 includes metal line 428a. Metal line 428a can be the topmost metal line of die 400. In some embodiments, TSVs 120 of each of the two semiconductor structures 100 are connected and electrically coupled to metal line 428a by conductive features 455. Thus, TSVs 120 of each of the two semiconductor structures 100 are electrically coupled together. In some other embodiments not depicted, die 400 can be disposed upside down above the two semiconductor structures 100, and TSVs 120 of each of the two semiconductor structures 100 are connected and electrically coupled together by the bottommost metal line of die 400. Die 400 can include a plurality of logic circuits or other types of circuits.

[0099] Referring to Figure 10 In some embodiments, package 550 is a non-limiting example of an IC package that includes at least one instance of semiconductor structure 100 as discussed above with respect to Figure 1 to Figure 6 the illustration for simplicity. Some features, such as the plurality of guard rings 122, interconnect line structures 118 are omitted from Figure 10 the illustration.

[0100] In some embodiments, package 550 includes logic die 500, substrate 560, a plurality of memory dies 570, 575A-C, and 580 disposed between logic die 500 and substrate 560, a plurality of conductive features 555, and a plurality of bump structures 565. Memory dies are primarily responsible for storing and retrieving data. Each of the plurality of memory dies 570, 575A-C, and 580 includes one or more instances of semiconductor structure 100 (e.g., in the dashed rectangle with rounded corners) that includes a plurality of TSVs 120 extending through the one or more instances of semiconductor structure 100, each of which is discussed above with respect to Figure 1 to Figure 6 In the depicted embodiment, two adjacent semiconductor structures 100 of memory dies 570 and 580 share the same TSVs 120, which can reduce the footprint of package 550. In some other embodiments, two adjacent semiconductor structures 100 of memory dies 570 and 580 each have their own and do not share with each other the plurality of TSVs 120.

[0101] In some embodiments, the memory die 570 is adjacent to the logic die 500; the plurality of memory dies 575A-575C are aligned along the Y direction, and each of the plurality of memory dies 575A-575C is adjacent to the memory die 570; and the memory die 580 is adjacent to each of the plurality of memory dies 575A-575C and the substrate 560. The TSVs 120 are disposed between the plurality of memory dies 575B and 575C and between the plurality of memory dies 570 and 580 and connect the plurality of memory dies 570 and 580.

[0102] The logic die 500, the plurality of memory dies 570, 575A, and 580, and the substrate 560 are aligned along the Z direction; the logic die 500, the plurality of memory dies 570, 575B, and 580, and the substrate 560 are aligned along the Z direction; and the logic die 500, the plurality of memory dies 570, 575C, and 580, and the substrate 560 are aligned along the Z direction.

[0103] The logic die 500 is an IC chip containing one or more IC devices, such as a logic circuit, a signal circuit, or an application processor, a system-on-a-chip (SoIC), a transmitter and / or a receiver, one or a combination thereof. A special application IC (ASIC), a large-scale integration (LSI) circuit, or a very large-scale integration (VLSI) circuit, a voltage or current regulator, and the like.

[0104] The substrate 560 is an IC chip or a printed circuit board that includes a plurality of conductive segments supported by and electrically separated by a plurality of insulating layers, and is configured to receive one or more supply voltages and a reference voltage, such as a ground voltage, and distribute the one or more supply voltages and the reference voltage to the one or more bump structures 565.

[0105] The conductive segments include conductive lines, vias, contact pads, and / or under-bump metallization (UBM) structures that include one or more conductive materials, such as a metal, such as copper, aluminum, tungsten, or titanium, polysilicon, or another material capable of providing a low-resistance path. The insulating layers include one or more dielectric materials, such as silicon dioxide, silicon nitride, or one or more high-dielectric materials, a molding compound, or other materials capable of electrically insulating a plurality of adjacent conductive segments from one another.

[0106] Power distribution structure 550PDS, also referred to as power distribution network 550PDS in some embodiments, includes a plurality of insulating layers supporting and electrically isolating and arranged according to power transmission requirements of, for example, logic die 500. In various embodiments, power distribution structure 550PDS includes TSVs (e.g., TSVs 120), through-dielectric vias (TDVs), power supply rails, super power supply rails, buried power supply rails, contact pads, a plurality of electrically conductive segments arranged in a grid or mesh structure, or a combination of another arrangement suitable for distributing power to one or more IC devices. In some embodiments, power distribution structure 550PDS includes a plurality of electrically conductive features 555, a plurality of bump structures 565, and a plurality of TSVs 120, and is thereby configured to electrically couple logic die 500 to substrate 560.

[0107] In some embodiments, the plurality of electrically conductive segments are arranged to contact some or all instances of TSVs 120 included in some or all of memory dies 570-580 and logic die 500, such that power distribution structure 550PDS is configured to electrically couple logic die 500 to substrate 560 through some or all instances of TSVs 120, plurality of electrically conductive features 555, and plurality of bump structures 565.

[0108] Plurality of bump structures 565 are a plurality of electrically conductive structures covering and contacting a plurality of portions of substrate 560, and are thereby configured to provide electrical connections between substrate 560 and some or all instances of TSVs 120 in memory die 580. In some embodiments, plurality of bump structures 565 include lead. In some embodiments, plurality of bump structures 565 include a plurality of lead-free materials, such as tin, nickel, gold, silver, copper, or other materials suitable for providing electrical connections to a plurality of external electrically conductive components. In some embodiments, plurality of bump structures 565 have a substantially spherical shape. In some embodiments, plurality of bump structures 565 are controlled collapse chip connection (C4) bumps, ball grid array bumps, microbumps, or the like.

[0109] In Figure 10In the illustrated, non-limiting example, the package 550 includes five memory dies 570-580 that include 15 instances of the semiconductor structure 100 arranged in three rows disposed between the logic die 500 and the substrate 560 to electrically couple the logic die 500 to the substrate 560. In various embodiments, the package 550 includes more or fewer than five memory dies 570-580 and / or includes instances of the semiconductor structure 100 arranged in other ways to electrically couple the logic die 500 to the substrate 560. In some embodiments, the package 550 includes a single instance of the semiconductor structure 100 disposed between the logic die 500 and the substrate 560 to electrically couple the logic die 500 to the substrate 560.

[0110] In Figure 10 In the illustrated, non-limiting example, the package 550 includes the plurality of memory dies 570-580 each oriented with the front side FS more along the Z direction than the back side BS (representative instance labeled memory die 575B). In various embodiments, one or more of the plurality of memory dies 570-580 has an opposite orientation with the back side BS more along the Z direction than the front side FS.

[0111] In Figure 10 In the illustrated, non-limiting example, the package 550 includes a single instance of each of the logic die 500 and the substrate 560. In various embodiments, the package 550 includes two or more instances of one or both of the logic die 500 or the substrate 560, and two or more instances of one or both of the logic die 500 or the substrate 560, and the plurality of memory dies 570-580 are arranged to electrically couple each instance of the logic die 500 to each instance of the substrate 560.

[0112] In Figure 10 In the illustrated, non-limiting example, the plurality of memory dies 570-580 includes a range from one to six instances of the semiconductor structure 100. In various embodiments, one or more of the plurality of memory dies 570-580 does not include an instance of the semiconductor structure 100 or includes a number of instances of the semiconductor structure 100 other than six.

[0113] In Figure 10 In the illustrated, non-limiting example, the plurality of memory dies 570-580 includes a range from two to seven instances of the plurality of TSVs 120. In various embodiments, the plurality of memory dies 570-580 includes a number of instances of the plurality of TSVs 120 other than two and seven (e.g., greater than seven).

[0114] With the above configuration, the package 550 includes at least one instance of the plurality of memory dies 570-580 with one or more instances of the TSVs 120 extending through one or more instances of the semiconductor structure 100 such that the package 550 is able to realize the benefits discussed above with respect to the semiconductor structure 100.

[0115] Figure 11 is a top view of a semiconductor structure 600, which is an alternative to the semiconductor structure 100. The difference from the semiconductor structure 100 is that in the device layer 104, the semiconductor structure 600 also contains regions 615a and 615b located on the device region 105a side 150 and the device region 105b side 155, respectively. The regions 615a and 615b each include input / output (I / O) circuitry or control circuitry for controlling the plurality of circuits (e.g., SRAM cells or SRAM macros) of the plurality of device regions 105. The regions 615a and 615b can be referred to individually or collectively as region(s) 615 or logic region(s) 615, depending on the context.

[0116] In some embodiments depicted, the plurality of regions 615 includes a circular TSV 160. The circular TSV 160 locations and quantities shown herein are by way of example only and do not limit the scope of the present disclosure. For example, the circular TSV 160 can be inside the region 615 or on a side of the region 615. From a top view, the circular TSV 160 can be surrounded by a guard ring 162. The circular TSV 160 and the guard ring 162 can each extend through a plurality of layers (e.g., the interconnect line structure 118, the device layer 104) similar to the TSV 120 and the guard ring 122 as described above. From a top view, the circular TSV 160 can have an area that is less than the area of the TSV 120. As a result, the electrical resistance of the circular TSV 160 can be greater than the electrical resistance of the TSV 120. Because the plurality of circuits (e.g., SRAM cells or SRAM macros) of the plurality of device regions 105 can be more sensitive to voltage drop than the circuits of the plurality of regions 615, using different TSVs (e.g., the plurality of TSVs 120 and the plurality of circular TSVs 160) in the plurality of device regions 105 and the plurality of regions 615 as described above can reduce wasted energy, reduce the total footprint of the plurality of circuits, and reduce the cost associated with the plurality of TSVs while not affecting the performance of the semiconductor structure 600.

[0117] Figure 12is a top-down view of a semiconductor structure 700, which is an alternative to the semiconductor structure 100. The difference from the semiconductor structure 100 is that in the device layer 104, the semiconductor structure 700 also contains a plurality of regions 715a, 715b, and 715c, which are located on the first side 125 of the first device region 105a, between the third side 130 of the first device region 105a and the fourth side 135 of the second device region 105b, and on the second side 140 of the second device region 105b, respectively. The plurality of regions 715a, 715b, and 715c can each include input / output (I / O) circuitry or control circuitry for controlling the plurality of circuits (e.g., SRAM cells or SRAM macros) of the plurality of device regions 105. The plurality of regions 715a, 715b, 715c, depending on the context, can be referred to individually or collectively as region(s) 715 or the plurality of logic regions 715. Although not depicted, the plurality of regions 715 can include TSV(s) 160 and guard ring(s) 162 as described above.

[0118] In some embodiments, the first plurality of TSV structures 115 disposed along the first side 125 of the first device region 105a is located within the region 715a, and the second plurality of TSV structures 115 disposed along the second side 140 of the second device region 105b is located within the region 715c. The plurality of TSV structures 115 is isolated from the plurality of transistors in the regions 715a and 715c. The plurality of power lines 145 can further extend over the plurality of regions 715a, 715b, and 715c.

[0119] Figure 13 is a top-down view of a semiconductor structure 800, which is an alternative to the semiconductor structure 100. The difference from the semiconductor structure 100 is that in the device layer 104, the semiconductor structure 800 also includes a plurality of regions 815a, 815b, 815c, 815d, and 815e, which are comparable to the plurality of regions 715a, 715b, 715c, 615a, and 615b of the semiconductor structure 600. Figure 11 and Figure 12 In some embodiments, the plurality of regions 815a, 815b, and 815c each include control circuitry, and the regions 815d and 815e each include I / O circuitry. Depending on the context, the plurality of regions 815a, 815b, 815c, 815d, and 815d can be referred to individually or collectively as region(s) 815 or logic region(s) 815. Although not depicted, the plurality of regions 815 can include TSV(s) 160 and guard ring(s) 162 as described above.

[0120] Although not intended to be limiting, one or more embodiments of the present application provide a number of benefits for semiconductor structures and packages. The vias of the semiconductor structures described herein reduce resistance by having the shapes and sizes described. As a result, wasted energy during operation can be reduced in the vias. By implementing the vias, space between adjacent device regions can be reduced, thus reducing the footprint of the semiconductor structure. In addition, the height of the vias can also be reduced, which can reduce the height of the semiconductor structure and the size of a package containing the semiconductor structure. In some embodiments, the semiconductor structures described herein are connected to one or more dies through the via(s) to form a package. The power distribution structure formed by the vias and other conductive segments can have the advantages described above.

[0121] In one exemplary aspect, the present application is directed to a semiconductor structure. The semiconductor structure includes a substrate and a device layer disposed above the substrate. The device layer includes a first device region and a second device region. The first device region has a first side facing and spaced apart from a second side of the second device region, as viewed from a top view. The semiconductor structure further includes an interconnect line structure disposed above the first device region and the second device region, and a first plurality of vias and a second plurality of vias extending through the substrate, the device layer, and the interconnect line structure. The first plurality of vias is disposed along a third side of the first device region, as viewed from the top view, opposite the first side of the first device region, and the second plurality of vias is disposed along a fourth side of the second device region, as viewed from the top view, opposite the second side of the second device region. Each via of the first plurality of vias and the second plurality of vias has a racetrack shape, as viewed from the top view.

[0122] In some embodiments, the interconnect line structure includes a plurality of power lines extending along a direction perpendicular to the first side direction of the first device region. In some embodiments, the first device region includes a first memory array and the second device region includes a second memory array, and the first memory array and the second memory array each include a plurality of static random access memory cells. In some embodiments, the semiconductor structure further includes a die disposed below the substrate, wherein the die includes a top metal electrically coupled to the first plurality of vias. In some embodiments, the die is a logic die. In some embodiments, the interconnect line structure is a first interconnect line structure, the semiconductor structure further including a die disposed above the first interconnect line structure, the die including a second interconnect line structure electrically coupled to the first plurality of vias. In some embodiments, the racetrack shape includes two rounded end portions and a rectangular middle portion between the two rounded end portions, a ratio of a width of the racetrack shape to a length of the racetrack shape is about 1:1 to about 1:30. In some embodiments, the racetrack shape has a total length along the first side direction and a width perpendicular to the first side direction, the total length is about 1 micrometer to about 65 micrometers, and the width is about 1 micrometer to about 10 micrometers. In some embodiments, the semiconductor structure further includes a guard ring surrounding one or more vias of the first plurality of vias, the guard ring extending from the device layer to a top surface of the interconnect line structure, and including a stack of a plurality of metal lines and a plurality of vias, from the top-down view. In some embodiments, there is no via between the first device region and the second device region.

[0123] In another exemplary aspect, the utility model relates to a semiconductor structure. The semiconductor structure includes a substrate and a device layer disposed above the substrate. The device layer includes a first device region and a second device region adjacent to the first device region. The semiconductor structure further includes an interconnect line structure disposed above the first device region and the second device region, a first silicon via and a second silicon via disposed along a first side of the first device region from a top-down view, and a third silicon via and a fourth silicon via disposed along a second side of the second device region from the top-down view. The first silicon via and the second silicon via are spaced apart from the third silicon via and the fourth silicon via via the first device region and the second device region. The first silicon via, the second silicon via, the third silicon via, and the fourth silicon via all extend through the substrate, the device layer, and the interconnect line structure. There is no silicon via between the first device region and the second device region. Each of the first silicon via, the second silicon via, the third silicon via, and the fourth silicon via has an elongated shape from the top-down view.

[0124] In some embodiments, the interconnect structure includes a power metal line extending in a direction perpendicular to the first side of the first device region, and the power metal line is disposed between the first silicon via and the second silicon via and between the third silicon via and the fourth silicon via, from the top view. In some embodiments, the first device region and the second device region both include a memory array including a plurality of static random access memory cells. In some embodiments, at least one of the first silicon via, the second silicon via, the third silicon via, and the fourth silicon via is electrically coupled to a top metal of a logic die. In some embodiments, the logic die is disposed above the first silicon via, the second silicon via, the third silicon via, and the fourth silicon via. In some embodiments, the device layer further includes a logic region adjacent to the first device region, and the logic region includes a circular via extending through the logic region, from the top view.

[0125] In another exemplary aspect, the utility model relates to a semiconductor structure. The semiconductor structure includes a device layer including a first device region and a second device region, an interconnect structure disposed above the first device region and the second device region, a first silicon via disposed on a first side of the first device region, and a second silicon via disposed on a second side of the second device region opposite the first side of the first device region. The first silicon via and the second silicon via both extend through the device layer and the interconnect structure. Each of the first silicon via and the second silicon via has a racetrack shape including a middle portion and two circular end portions sandwiching the middle portion, from a top view. Two sides of the middle portion are parallel to the first side of the first device region.

[0126] In some embodiments, the interconnect structure includes a power metal line extending from the first device region to the second device region, from the top view. In some embodiments, the interconnect structure is a first interconnect structure, the device layer further includes a second interconnect structure disposed below the device layer, the first silicon via and the second silicon via further extend through the second interconnect structure, and the second interconnect structure includes a power metal line extending from the first device region to the second device region, from the top view. In some embodiments, there is no silicon via in a space between the first device region and the second device region.

[0127] Finally, it should be noted that: the above embodiments are used to illustrate the technical solutions of the present application, but not limited to them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized by, comprising: a substrate; a device layer disposed over the substrate, wherein the device layer comprises a first device region and a second device region, wherein, from a top view, the first device region has a first side facing and spaced apart from a second side of the second device region; an interconnect line structure disposed over the first device region and the second device region; and a first plurality of vias and a second plurality of vias extending through the substrate, the device layer, and the interconnect line structure, wherein, from the top view, the first plurality of vias is disposed along a third side of the first device region opposite the first side of the first device region, and the second plurality of vias is disposed along a fourth side of the second device region opposite the second side of the second device region, and wherein, from the top view, each via of the first plurality of vias and the second plurality of vias has a racetrack shape.

2. The semiconductor structure of claim 1, wherein, wherein the first device region comprises a first memory array and the second device region comprises a second memory array, wherein the first memory array and the second memory array each comprise a plurality of static random access memory cells.

3. The semiconductor structure of claim 1, wherein, wherein the racetrack shape comprises two circular end portions and a rectangular middle portion between the two circular end portions, wherein a ratio of a width of the racetrack shape to a length of the racetrack shape is about 1: 1 to about 1:

30.

4. The semiconductor structure of claim 1, wherein, wherein the racetrack shape has a total length along the first side direction and a width perpendicular to the first side direction, wherein the total length is about 1 micrometer to about 65 micrometers, wherein the width is about 1 micrometer to about 10 micrometers.

5. The semiconductor structure of claim 1, wherein, further comprising, from the top view, a guard ring surrounding one or more vias of the first plurality of vias, wherein the guard ring extends from the device layer to a top surface of the interconnect line structure and comprises a stack of a plurality of metal lines and a plurality of vias.

6. The semiconductor structure of claim 1, wherein, wherein a space between the first device region and the second device region is free of vias.

7. A semiconductor structure, characterized by comprising: a substrate; a device layer disposed over the substrate, wherein the device layer comprises a first device region and a second device region adjacent to the first device region; an interconnect line structure disposed over the first device region and the second device region; a first silicon via and a second silicon via disposed, from a top view, along a first side of the first device region; and a third silicon via and a fourth silicon via disposed, from the top view, along a second side of the second device region, wherein the first silicon via and the second silicon via are spaced apart from the third silicon via and the fourth silicon via via the first device region and the second device region, wherein the first silicon via, the second silicon via, the third silicon via, and the fourth silicon via all extend through the substrate, the device layer, and the interconnect line structure, wherein a space between the first device region and the second device region is free of silicon vias, and ​ wherein each of the first, second, third, and fourth through-silicon vias has an elongated shape from the top view.

8. The semiconductor structure of claim 7, wherein, wherein the device layer further comprises a logic region adjacent to the first device region from the top view, wherein the logic region comprises a circular through-silicon via extending through the logic region.

9. A semiconductor structure, characterized by Comprising: a device layer comprising a first device region and a second device region; an interconnect line structure disposed above the first device region and the second device region; a first through-silicon via disposed on a first side of the first device region; and a second through-silicon via disposed on a second side of the second device region opposite the first side of the first device region, wherein the first and second through-silicon vias extend through the device layer and the interconnect line structure, wherein each of the first and second through-silicon vias has a racetrack shape comprising a middle portion and two circular end portions flanking the middle portion from a top view, and wherein the middle portion is parallel to the first side of the first device region. wherein the interconnect line structure comprises a power metal line extending from the first device region to the second device region from the top view.

10. The semiconductor structure of claim 9, wherein, ​

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