Semiconductor device, power module, power conversion circuit and vehicle
By introducing a heterojunction structure into semiconductor devices, the problems of forward conduction resistance and leakage current are solved, thereby improving device performance and stability.
Patent Information
- Application Number
- CN202520323606.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2035-02-26
AI Technical Summary
Existing junction barrier Schottky diodes and hybrid PIN-Schottky diodes suffer from large leakage current or high forward voltage drop during forward conduction, which affects device performance.
A heterojunction is formed by using a semiconductor structure layer and a second region. The heterojunction reduces the barrier height at the interface. Combined with the bandgap of the semiconductor structure layer, the contact resistance is reduced when forward biased and the leakage current is reduced when reverse biased.
This approach achieves a reduction in leakage current while lowering the forward conduction resistance of the device, thereby improving the performance and stability of the semiconductor device.
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Figure CN223816359U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the utility model relates to the technical field of semiconductor, especially relates to a semiconductor device, power module, power conversion circuit and vehicle. BACKGROUND
[0002] In the structure of Junction barrier Schottky diode (JBS) and Merged PiN Schottky (MPS), a Schottky contact part is arranged. When the device is forward biased, only the Schottky contact part participates in conduction, and the characteristics of the semiconductor device are similar to those of a Schottky diode. For the Schottky diode, if the Schottky contact part uses a metal with a high contact potential barrier, the leakage current can be reduced, but the forward conduction voltage drop will also increase. If the Schottky contact part uses a metal with a low contact potential barrier, the forward conduction voltage drop can be reduced, but the reverse leakage current will also increase. The above structures will affect the performance of the semiconductor device. SUMMARY
[0003] The utility model provides a kind of semiconductor device, power module, power conversion circuit and vehicle, it is realized in reducing device forward conduction resistance, further reduce device leakage current, improve the performance and stability of semiconductor device.
[0004] In a first aspect, the utility model embodiment provides a kind of semiconductor device, comprising: semiconductor body, the semiconductor body includes oppositely arranged first surface and second surface, the semiconductor body further includes multiple first regions and multiple second regions, the first region and the second region are arranged in the first surface, and extend into the semiconductor body, and the second region is located between adjacent first region;The first region is first conduction type, and the second region is second conduction type;
[0005] Semiconductor structure layer is located in the first surface, and the orthographic projection of the semiconductor structure layer on the first surface at least covers the orthographic projection of the second region on the first surface;The semiconductor structure layer is used to form heterojunction with the second region;Wherein, the semiconductor structure layer is the second conduction type;The first conduction type and the second conduction type are different;
[0006] First metal layer is located in the side of the semiconductor structure layer away from the first surface;
[0007] Second metal layer is located in the second surface.
[0008] Optionally, the first region and the second region are arranged adjacently, and a projection of the semiconductor structure layer on the first surface covers at least a projection of the first region on the first surface and a projection of the second region on the first surface.
[0009] Optionally, the first region and the second region are arranged adjacently, and a projection of the semiconductor structure layer on the first surface covers a projection of the second region on the first surface.
[0010] The semiconductor device further comprises a third metal layer.
[0011] The third metal layer is located on the first surface, and a projection of the third metal layer on the first surface covers a projection of the first region on the first surface.
[0012] Optionally, the semiconductor structure layer comprises polycrystalline silicon of the second conductive type.
[0013] Optionally, the semiconductor device further comprises a metal pad layer, the metal pad layer is located between the first metal layer and the semiconductor structure layer, and a projection of the metal pad layer on the first surface covers at least a projection of the semiconductor structure layer on the first surface.
[0014] Optionally, the semiconductor body further comprises:
[0015] At least one field limiting ring, the at least one field limiting ring is arranged on the first surface and located on a side of the first region that is farthest in a direction parallel to the first surface.
[0016] Optionally, the semiconductor device further comprises:
[0017] An insulating layer, the insulating layer is located on the first surface, and a projection of the insulating layer on the first surface covers a projection of the field limiting ring on the first surface.
[0018] In a second aspect, an embodiment of the utility model provides a power module, comprising a substrate and any semiconductor device described in the utility model embodiment, and the substrate is used for bearing the semiconductor device.
[0019] In a third aspect, an embodiment of the utility model provides a power conversion circuit, and the power conversion circuit is used for one or more of current conversion, voltage conversion and power factor correction.
[0020] The power conversion circuit comprises a circuit board and any semiconductor device described in the utility model embodiment, and the semiconductor device is electrically connected with the circuit board.
[0021] In a fourth aspect, the utility model discloses a kind of vehicles, including load and the power conversion circuit described in the utility model embodiment, the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current or convert direct current into alternating current, input to the load after.
[0022] The semiconductor device provided by the utility model embodiment is characterized in that the semiconductor structure layer is arranged on the first surface of the semiconductor body, and the orthographic projection of the semiconductor structure layer on the first surface covers at least the orthographic projection of the second region on the first surface, that is, a same-type heterojunction is formed by the semiconductor structure layer and the second region, and when forward biasing, the heterojunction can reduce the height of the potential barrier at the interface, thereby reducing the contact resistance, and further reducing the forward conduction resistance of the device, and when reverse biasing, the band gap width of the semiconductor structure layer itself can further reduce the leakage current of the device, so that the forward conduction resistance of the device is reduced while the leakage current of the device is further reduced, and the performance and stability of the semiconductor device are improved. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 A structural schematic diagram of a semiconductor device is provided for the utility model embodiment;
[0024] Figure 2 A structural schematic diagram of another semiconductor device is provided for the utility model embodiment;
[0025] Figure 3 A flowchart of a preparation method of a semiconductor device is provided for the utility model embodiment;
[0026] Figure 4 A flowchart of another preparation method of a semiconductor device is provided for the utility model embodiment;
[0027] Figures 5 to 8 An intermediate structural schematic diagram of a preparation process is provided for the utility model embodiment. DETAILED DESCRIPTION
[0028] To make the purpose, technical scheme and advantages of the utility model embodiments clearer, the technical scheme in the utility model embodiments will be described clearly and completely in combination with the drawings in the utility model embodiments below. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the utility model.
[0029] Figure 1 A structural schematic diagram of a semiconductor device is provided for the utility model embodiment, referring toFigure 1 , comprising:
[0030] a semiconductor body 100 comprising a first surface and a second surface arranged opposite to each other, the semiconductor body 100 further comprising a plurality of first regions 10 and a plurality of second regions 20, the first regions 10 and the second regions 20 being arranged at the first surface and extending into the semiconductor body 100, the second regions 20 being located between adjacent first regions 10; the first regions 10 being of a first conductivity type, the second regions 20 being of a second conductivity type;
[0031] a semiconductor structure layer 110 located at the first surface, a projection of the semiconductor structure layer 110 on the first surface covering at least a projection of the second regions 20 on the first surface; the semiconductor structure layer 110 being configured to form a heterojunction with the second regions 20; the semiconductor structure layer 110 being of the second conductivity type, the first conductivity type and the second conductivity type being different;
[0032] a first metal layer 120 located at a side of the semiconductor structure layer 110 facing away from the first surface;
[0033] a second metal layer 130 located at the second surface.
[0034] In particular, the semiconductor device in the embodiments of the present application can be a JBS or MPS diode. Exemplarily, the semiconductor body 100 can comprise a substrate 30 and an epitaxial layer 40, and the materials of the substrate 30 and the epitaxial layer 40 can be silicon carbide. The epitaxial layer 40 is formed on one side of the substrate 30, wherein the epitaxial layer 40 can be formed on the surface of the substrate 30 by epitaxial growth. The surface of the epitaxial layer 40 facing away from the substrate 30 can be used as the first surface, and the first regions 10 and the second regions 20 are alternately arranged on the first surface, and the first regions 10 are located between adjacent second regions 20. The first regions 10 and the second regions 20 can be formed by epitaxial growth, ion implantation or vapor deposition. Exemplarily, the first regions 10 and the second regions 20 in the embodiments of the present application are formed in the epitaxial layer 40 by ion implantation. The first regions 10 can be of a first conductivity type, and the substrate 30, the epitaxial layer 40 and the second regions 20 can be of a second conductivity type. In the embodiments of the present application, the first conductivity type can be N-type doping, and the second conductivity type can be P-type doping, or the first conductivity type can be P-type doping, and the second conductivity type can be N-type doping. The N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) or B (boron) ions. Exemplarily, the first regions 10 are P-type doped, and the substrate 30, the epitaxial layer 40 and the second regions 20 are N-type doped, in the embodiments of the present application, the first conductivity type is P-type doping, and the second conductivity type is N-type doping.
[0035] A semiconductor structure layer 110 is arranged on the first surface away from the substrate 30, and the semiconductor structure layer 110 can be a polycrystalline silicon material doped with a second conductive type and is formed on the first surface through a deposition process, wherein the semiconductor structure layer 110 at least covers the second region 20 and is in contact with the second region 20. Based on the above embodiment, the semiconductor structure layer 110 can be of the second conductive type and be doped with an N type, wherein the doping concentration of the semiconductor structure layer 110 is greater than the doping concentration of the second region 20. Therefore, the contact area between the second region 20 and the semiconductor structure layer 110 forms a same-type heterojunction. The first metal layer 120 serves as an anode of the semiconductor device, the second metal layer 130 serves as a cathode of the semiconductor device, and the heterojunction structure replaces the Schottky contact in the diode. In the forward bias, the contact area between the second region 20 and the semiconductor structure layer 110 participates in conduction, and the heterojunction can reduce the height of the potential barrier at the interface, thereby reducing the contact resistance and further reducing the forward conduction resistance of the device.
[0036] In the reverse bias, the PN junction formed by the first region 10 and the epitaxial layer 40 on both sides of the second region 20 forms a mutual contact of depletion regions, shields the heterojunction contact, and reduces the electric field strength below the heterojunction, thereby reducing the leakage current.
[0037] The semiconductor device provided in the embodiment of the utility model, through the semiconductor structure layer 110 is arranged in the first surface of the semiconductor body 100, the orthographic projection of the semiconductor structure layer 110 on the first surface at least covers the orthographic projection of the second region 20 on the first surface, that is to say, the same-type heterojunction is formed by the semiconductor structure layer 110 and the second region 20, in the forward bias, the heterojunction can reduce the height of the potential barrier at the interface, thereby reducing the contact resistance and further reducing the forward conduction resistance of the device, in the reverse bias, the semiconductor structure layer 110 itself can further reduce the leakage current of the device by the existence of the forbidden band width, thereby realizing the reduction of the forward conduction resistance of the device while further reducing the leakage current of the device, and improving the performance and stability of the semiconductor device.
[0038] Figure 2 Another structure schematic diagram of the semiconductor device provided in the embodiment of the utility model is provided, referring to Figure 2 , the first region 10 and the second region 20 are arranged adjacent to each other, and the orthographic projection of the semiconductor structure layer 110 on the first surface covers the orthographic projection of the second region 20 on the first surface.
[0039] The semiconductor device further comprises a third metal layer 140.
[0040] The third metal layer 140 is located on the first surface, wherein a projection of the third metal layer 140 on the first surface covers a projection of the first region 10 on the first surface.
[0041] Specifically, the third metal layer 140 and the semiconductor structure layer 110 are alternately arranged on the first surface, wherein the third metal layer 140 only covers the first region 10, and the semiconductor structure layer 110 only covers the second region 20. The third metal layer 140 can be nickel or titanium metal, and the third metal layer 140 forms an ohmic contact with the first region 10, thereby reducing the contact resistance between the first metal layer 120 and the first region 10, and facilitating the formation of a depletion region at the PN junction formed by the first region 10 and the epitaxial layer 40 under reverse bias.
[0042] The contact region between the second region 20 and the semiconductor structure layer 110 forms a same-type heterojunction. The heterojunction can reduce the height of the potential barrier at the interface, thereby reducing the contact resistance. The semiconductor structure layer 110 itself has a band gap, which can further reduce the leakage current of the device, thereby reducing the forward conduction resistance of the device while further reducing the leakage current of the device, and improving the performance and stability of the semiconductor device.
[0043] In other embodiments, continuing to refer to Figure 1 , the first region 10 and the second region 20 are arranged adjacent to each other, and a projection of the semiconductor structure layer 110 on the first surface covers at least a projection of the first region 10 on the first surface and a projection of the second region 20 on the first surface.
[0044] Specifically, the difference between Figure 2 the embodiments is that the semiconductor structure layer 110 covers the first region 10 and covers the second region 20, that is, the semiconductor structure layer 110 is continuously arranged on the first surface, and at this time, the surface of the first region 10 does not need to be provided with the third metal layer 140. Since the first region 10 and the semiconductor structure layer 110 have different conductive types, the PN junction formed by the first region 10 and the epitaxial layer 40 can still form a depletion region under reverse bias, thereby shielding the heterojunction contact. In the preparation process, the semiconductor structure layer 110 can be obtained by deposition, thereby reducing the process difficulty.
[0045] In the semiconductor device structure based on the above embodiments, the semiconductor structure layer 110 can be composed of polycrystalline silicon of the second conductive type. Compared with the traditional metal material, the polycrystalline silicon itself has a band gap, which can further reduce the leakage current of the device.
[0046] Continuing to refer to Figure 1 and Figure 2The semiconductor device further comprises a metal pad layer 150 located between the first metal layer 120 and the semiconductor structure layer 110, and a projection of the metal pad layer 150 on the first surface at least covers a projection of the semiconductor structure layer 110 on the first surface.
[0047] Specifically, the metal pad layer 150 is arranged on a side of the semiconductor structure layer 110 away from the first surface, and the first metal layer 120 is arranged on a side of the metal pad layer 150 away from the first surface. The metal pad layer 150 can be made of titanium or titanium nitride. The metal pad layer 150 can be used as a protective layer to cover the surface of the semiconductor structure layer 110, so as to prevent the semiconductor structure layer 110 from being eroded by the material such as aluminum of the first metal layer 120. In addition, in the process, the first metal layer 120 can be connected with the metal pad layer 150 to form a contact, without forming a Schottky contact with the second region 20, so that the processing procedure of rapid thermal annealing (RTA) of the first metal layer 120 can be reduced, and the process cost can be reduced.
[0048] Continuing to refer to Figure 1 and Figure 2 The semiconductor body 100 further comprises at least one field limiting ring GR arranged on the first surface and located on a side of the first region 10 farthest to the first surface.
[0049] Specifically, the field limiting ring GR is used to improve the withstand voltage performance of the semiconductor device and reduce the concentration effect of the electric field. The field limiting ring GR is formed by layout doping regions, so as to realize the regulation and limitation of the electric field intensity in the semiconductor device. In the embodiment of the utility model, the at least one field limiting ring GR is arranged on a side of the first region 10 farthest to the first surface. When there are a plurality of field limiting rings GR, the field limiting rings GR are arranged at intervals. When a reverse voltage bias is added to the device, the depletion region between the first region 10 and the epitaxial layer 40 will expand to the field limiting ring GR, and the field limiting ring GR can share a part of the withstand voltage, so as to optimize the surface electric field peak value and increase the withstand voltage of the semiconductor device.
[0050] Optionally, the semiconductor device further comprises an insulating layer 160 located on the first surface, and a projection of the insulating layer 160 on the first surface covers a projection of the field limiting ring GR on the first surface.
[0051] Specifically, the insulating layer 160 covers the surface of the field limiting ring GR, can isolate the first metal layer 120, and avoids the field limiting ring GR and the first metal layer 120 from being in contact, thereby affecting the device performance. Further, the insulating layer 160 can also be used to support the packaging material of the subsequent semiconductor device, thereby improving the structural stability of the device.
[0052] The embodiment of the utility model provides a kind of preparation method of semiconductor device based on the above embodiment, Figure 3 It is the flow chart of the preparation method of semiconductor device provided in the embodiment of the utility model, combined with Figure 1 , refer to Figure 3 , preparation method includes:
[0053] S110, provide semiconductor body 100, the semiconductor body 100 includes oppositely arranged first surface and second surface, the semiconductor body 100 also includes multiple first area 10 and multiple second area 20, the first area 10 and the second area 20 are arranged on the first surface and extend into the semiconductor body 100, and the second area 20 is located between adjacent first area 10;
[0054] Specifically, the semiconductor device in the embodiment of the utility model can be JBS or MPS diode, exemplarily, semiconductor body 100 can include substrate 30 and epitaxial layer 40, the material of substrate 30 and epitaxial layer 40 can be silicon carbide, epitaxial layer 40 is formed on one side of substrate 30, wherein epitaxial layer 40 can be formed on the surface of substrate 30 by epitaxial growth.The surface of the side of epitaxial layer 40 away from substrate 30 can be used as the first surface, and the first area 10 and the second area 20 are alternately arranged on the first surface, and the first area 10 is located between adjacent second area 20.The first area 10 and the second area 20 can be formed by epitaxial growth, ion implantation or vapor deposition, exemplarily, the first area 10 and the second area 20 are formed in epitaxial layer 40 by ion implantation in the embodiment of the utility model. The first area 10 can be of a first conductivity type, and the substrate 30, the epitaxial layer 40 and the second area 20 can be of a second conductivity type. The first conductivity type in the embodiment of the utility model can be N-type doping, and the second conductivity type can be P-type doping, or the first conductivity type can be P-type doping, and the second conductivity type can be N-type doping. N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and P-type doping ions can be Al (aluminum) ions or B (boron) ions. Exemplarily, the first area 10 is P-type doped, and the substrate 30, the epitaxial layer 40 and the second area 20 are N-type doped in the embodiment of the utility model, taking the first conductivity type as P-type doping and the second conductivity type as N-type doping as an example.
[0055] S120, forming a semiconductor structure layer 110 on the first surface; a projection of the semiconductor structure layer 110 on the first surface covers at least a projection of the second region 20 on the first surface; the semiconductor structure layer 110 and the second region 20 have the same conductivity type, and a doping concentration of the semiconductor structure layer 110 is greater than a doping concentration of the second region 20;
[0056] Specifically, the semiconductor structure layer 110 is arranged on the side of the first surface away from the substrate 30, and the semiconductor structure layer 110 can be formed on the first surface by a deposition process. The semiconductor structure layer 110 covers at least the second region 20 and is in contact with the second region 20. According to the above embodiment, the semiconductor structure layer 110 can be N-type doped, and the doping concentration of the semiconductor structure layer 110 is greater than the doping concentration of the second region 20. Therefore, the contact area between the second region 20 and the semiconductor structure layer 110 forms a homojunction. The first metal layer 120 serves as an anode of the semiconductor device, the second metal layer 130 serves as a cathode of the semiconductor device, and the heterojunction structure replaces the Schottky contact in the diode. When forward biased, the contact area between the second region 20 and the semiconductor structure layer 110 participates in conduction, and the use of the heterojunction can reduce the barrier height at the interface, thereby reducing the contact resistance, and further reducing the forward conduction resistance of the device.
[0057] When reverse biased, the PN junction formed by the first region 10 and the epitaxial layer 40 on both sides of the second region 20 forms a depletion region that is in contact with each other, shielding the heterojunction contact and reducing the electric field strength below the heterojunction, thereby reducing the leakage current. Further, compared with traditional metal materials, the polysilicon material itself has a band gap, which can further reduce the leakage current of the device.
[0058] S130, forming a first metal layer 120 on the side of the semiconductor structure layer 110 away from the first surface;
[0059] S140, forming a second metal layer 130 on the second surface;
[0060] Specifically, the drain 110 can be formed on the side of the substrate 3050 away from the epitaxial layer 4070 by sputtering or the like. First, the surface of the substrate 3050 away from the epitaxial layer 4070 is thinned, and then the second metal layer 130 is formed by sputtering, deposition, RTA process or the like. The second metal layer 130 can be titanium (Ti), nickel (Ni) or silver (Ag).
[0061] The preparation method of the semiconductor device provided in the embodiment of the utility model, through forming the semiconductor structure layer 110 on the first surface of the semiconductor body 100, the orthographic projection of the semiconductor structure layer 110 on the first surface covers at least the orthographic projection of the second area 20 on the first surface, thereby forming the same type of heterojunction by the semiconductor structure layer 110 and the second area 20, when forward bias, the heterojunction can reduce the barrier height at the interface, thereby reducing the contact resistance, and further can reduce the device forward conduction resistance, when reverse bias, by the band gap width of the semiconductor structure layer 110 itself, the device leakage current can be further reduced, thereby realizing reducing the device forward conduction resistance while further reducing the device leakage current, and improving the performance and stability of the semiconductor device.
[0062] The embodiment of the utility model takes Figure 1 The semiconductor device structure in the example as an example introduces a kind of preparation method of semiconductor device, Figure 4 It is the flow chart of another preparation method of semiconductor device provided in the embodiment of the utility model, Figures 5 to 8 The intermediate structure schematic diagram of preparation process provided in the embodiment of the utility model, preparation method includes:
[0063] S210, epitaxial layer 40 is formed on one side of substrate 30;Its structure is as shown in Figure 5 As shown.
[0064] S220, first area 10, second area 20 and at least one field limiting ring GR are formed on the side of epitaxial layer 40 away from substrate 30, second area 20 is located between adjacent first area 10, and at least one field limiting ring GR is located on the side of the outermost first area 10 in the direction parallel to the first surface.
[0065] Specifically, the side surface of epitaxial layer 40 away from substrate 30 can be used as the first surface, and the first area 10 and the second area 20 are alternately arranged on the first surface, and the first area 10 is located between adjacent second areas 20. At least one field limiting ring GR is arranged on the side of the outermost first area 10, and the first area 10, the second area 20 and the at least one field limiting ring GR are formed in the epitaxial layer 40 by ion implantation, if there are multiple field limiting rings GR, the field limiting rings GR are arranged at intervals. The first area 10 is of a first conductivity type, and the second area 20 is of a second conductivity type. The embodiment of the utility model takes the first conductivity type as P-type doping and the second conductivity type as N-type doping as an example, the first area 10 is P-type doped, and the substrate 30, the epitaxial layer 40 and the second area 20 are N-type doped. Its structure is as shown in Figure 6 As shown.
[0066] S230, forming an insulating layer 160 on the first surface, a projection of the insulating layer 160 on the first surface covers a projection of the field limiting ring GR on the first surface.
[0067] Specifically, the insulating layer 160 covers the surface of the field limiting ring GR, which can isolate the first metal layer 120 and avoid the contact between the field limiting ring GR and the first metal layer 120, thereby affecting the performance of the device. Further, the insulating layer 160 can also be used to support the packaging material of the subsequent semiconductor device, thereby improving the structural stability of the device. The structure is shown in FIG. 8. Figure 7
[0068] S240, forming a semiconductor structure layer 110 on the first surface; a projection of the semiconductor structure layer 110 on the first surface covers at least a projection of the second region 20 on the first surface; the semiconductor structure layer 110 and the second region 20 have the same conductivity type.
[0069] Specifically, the semiconductor structure layer 110 is arranged on the side of the first surface away from the substrate 30, and the semiconductor structure layer 110 can be formed on the first surface by a deposition process. The semiconductor structure layer 110 covers the first region 10 and the second region 20, and the doping concentration of the semiconductor structure layer 110 is greater than the doping concentration of the second region 20. The contact area of the second region 20 and the semiconductor structure layer 110 forms a same-type heterojunction.
[0070] Optionally, a metal pad layer 150 is formed on the side surface of the semiconductor structure layer 110 away from the first surface, and the material of the metal pad layer 150 can be titanium or titanium nitride. The metal pad layer 150 can be used as a protective layer to cover the surface of the semiconductor structure layer 110, thereby avoiding the erosion of the semiconductor structure layer 110 by the aluminum or other materials of the first metal layer 120. In addition, in the process, the first metal layer 120 can form a contact connection with the metal pad layer 150 by arranging the metal pad layer 150 on the surface of the semiconductor structure layer 110, without the need to form a Schottky contact with the second region 20, thereby reducing the processing procedure of the rapid thermal annealing (RTA) of the first metal layer 120 and reducing the process cost. The structure is shown in FIG. 8.
[0071] S250, forming a first metal layer 120 on the side of the semiconductor structure layer 110 away from the first surface; and forming a second metal layer 130 on the second surface. The structure is shown in FIG. 8. Figure 1
[0072] The utility model embodiment provides a kind of power module on the basis of the above embodiment, including substrate and the semiconductor device of any embodiment of the utility model, substrate is used to carry semiconductor device.
[0073] The power module provided by the technical scheme of the embodiment of the utility model has the same beneficial effects as the semiconductor device of any embodiment of the utility model.
[0074] The power conversion circuit provided by the technical scheme of the embodiment of the utility model has the same beneficial effects as the semiconductor device of any embodiment of the utility model.
[0075] The power conversion circuit provided by the technical scheme of the embodiment of the utility model has the same beneficial effects as the semiconductor device of any embodiment of the utility model.
[0076] The vehicle provided by the embodiment of the utility model on the basis of the above embodiment comprises a load and the power conversion circuit of any embodiment of the utility model, and the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current or converting direct current into alternating current, and then inputting to the load.
[0077] Finally, it should be noted that: the above embodiments are only used to illustrate the technical scheme of the utility model, and not to limit it; although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical scheme recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the spirit and scope of the technical scheme of each embodiment of the utility model.
Claims
1. A semiconductor device, characterized by, Comprising: a semiconductor body comprising a first surface and a second surface disposed oppositely, the semiconductor body further comprising a plurality of first regions and a plurality of second regions, the first regions and the second regions disposed on the first surface and extending into the semiconductor body, the second regions located between adjacent first regions; the first regions being of a first conductivity type, the second regions being of a second conductivity type; a semiconductor structure layer located on the first surface, a projection of the semiconductor structure layer on the first surface covering at least a projection of the second regions on the first surface; the semiconductor structure layer configured to form a heterojunction with the second regions; wherein the semiconductor structure layer is of the second conductivity type; the first conductivity type and the second conductivity type being different; a first metal layer located on a side of the semiconductor structure layer away from the first surface; a second metal layer located on the second surface.
2. The semiconductor device according to claim 1, wherein the first regions and the second regions are disposed adjacently, a projection of the semiconductor structure layer on the first surface covering at least a projection of the first regions on the first surface and a projection of the second regions on the first surface.
3. The semiconductor device of claim 1, wherein the first regions and the second regions are disposed adjacently, a projection of the semiconductor structure layer on the first surface covering a projection of the second regions on the first surface; the semiconductor device further comprising: a third metal layer; the third metal layer located on the first surface, wherein a projection of the third metal layer on the first surface covers a projection of the first regions on the first surface.
4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor structure layer comprises polysilicon of the second conductivity type.
5. The semiconductor device according to any one of claims 1 to 3, wherein further comprising a metal pad layer located between the first metal layer and the semiconductor structure layer, a projection of the metal pad layer on the first surface covering at least a projection of the semiconductor structure layer on the first surface.
6. The semiconductor device of claim 4, wherein the semiconductor body further comprising: at least one field limiting ring disposed on the first surface, located on a side of the first regions that is most outward in a direction parallel to the first surface.
7. The semiconductor device of claim 6, wherein, the semiconductor device further comprising: an insulating layer located on the first surface, a projection of the insulating layer on the first surface covering a projection of the field limiting ring on the first surface.
8. A power module, characterized by comprising a substrate and at least one semiconductor device as claimed in any one of claims 1-7, the substrate configured to carry the semiconductor device.
9. A power conversion circuit, characterized by, the power conversion circuit configured to perform one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit comprising a circuit board and at least one semiconductor device as claimed in any one of claims 1-7, the semiconductor device electrically connected to the circuit board.
10. A vehicle characterized by comprising: comprising a load and a power conversion circuit as claimed in claim 9, the power conversion circuit configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current before inputting to the load.