Highly accelerated stress testing device

Abstract

The utility model discloses a high acceleration stress testing device. The high acceleration stress testing device comprises a box body; the power supply control unit is arranged outside the box body, the power supply control unit comprises a plurality of switch assemblies, and one end of each switch assembly is connected with a power supply; the test unit is arranged in the box body; the test unit comprises a plurality of test seats, and each test seat is configured to test a to-be-tested chip when the to-be-tested chip is placed on the test seat; the test unit is connected with the power supply through the power control unit. Wherein the plurality of test bases are divided into at least two groups, each group of test bases is connected with the other end of one switch assembly, and the power supply control unit can utilize the plurality of switch assemblies to independently supply power to each group of test bases. According to the scheme, when the power supply outputs abnormal current, troubleshooting of each group of test bases can be realized without opening the box body, and the troubleshooting efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a high-accelerated stress testing device. BACKGROUND

[0002] Chip reliability testing is to test the reliability of the chip before it is shipped out by using corresponding testing devices and testing methods, which plays a crucial role in ensuring the quality of the chip. The reliability testing of plastic packaged chips includes wafer reliability testing and package reliability testing, and high-accelerated stress testing is a kind of package reliability testing, which is a kind of accelerated life testing to test the resistance of packaged chips to moisture immersion, chemical reaction and electrochemical reaction under high temperature, high humidity, high pressure and bias conditions. Since high-accelerated stress testing needs to be carried out under high temperature, high humidity and high pressure stress conditions in the powered-on state, a specific high-accelerated stress testing device is needed to carry out the testing.

[0003] The testing board in the high-accelerated stress testing device can support the placement of multiple chips and the connection of a power supply. During the high-accelerated stress testing process, the current value output by the power supply needs to be ensured within a small preset range. If there is a problem with the testing board, the test seat on the testing board or the chip itself, resulting in the current output by the power supply being greater than the preset range, it will take a long time to stop the high-accelerated stress testing, restore the environment in the box from high temperature, high humidity, high pressure and bias conditions to normal temperature, normal humidity and normal pressure environment, then open the box, and perform troubleshooting operations on the testing board and the chip placed in the box. After the troubleshooting is completed, the test seat with the abnormality is isolated, and then the box is closed, and the environment in the box is adjusted to the test environment again. In this way, the chip testing process is greatly prolonged. CONTENT OF THE INVENTION

[0004] The present application provides a high-accelerated stress testing device.

[0005] One of the technical solutions adopted by the present application is to provide a high-accelerated stress testing device, which comprises:

[0006] a box;

[0007] a power supply control unit arranged outside the box, the power supply control unit comprising a plurality of switch assemblies, one end of each switch assembly being connected to the power supply;

[0008] a testing unit arranged in the box; the testing unit comprising a plurality of test seats, each test seat being configured to test the chip under test when the chip under test is placed; the testing unit being connected to the power supply through the power supply control unit;

[0009] The plurality of test seats are divided into at least two groups, and one end of each group of test seats is connected to one end of one switch assembly.

[0010] Optionally, each group of test seats contains only one test seat.

[0011] Optionally, at least one group of test seats contains at least two test seats.

[0012] Optionally, the switch assembly comprises a first switch and a plurality of second switches, one end of the first switch is connected to the power supply;

[0013] One end of each second switch is connected to the other end of the first switch, and each test seat in each group of test seats is connected to the other end of the same second switch.

[0014] Optionally, the test seat is provided with a test interface, and the test interface is coupled to the chip to be tested.

[0015] Optionally, the test interface of at least one test seat is of a type different from that of the test interface of the other test seats.

[0016] Optionally, the power supply control unit comprises a plurality of ammeters, one end of each ammeter is connected to one end of each group of test seats, the other end of each ammeter is connected to the other end of one switch assembly, and the ammeter is configured to obtain the input current of each group of test seats.

[0017] Optionally, the test unit comprises a test board, and the test seat is detachably arranged and / or welded on the test board.

[0018] Optionally, the surface of the test board is provided with a protective layer.

[0019] Optionally, the power supply control unit is provided with a first power supply interface, one end of the first power supply interface is connected to the other end of the switch assembly.

[0020] The test board is provided with a second power supply interface, one end of the second power supply interface is connected to the test seat.

[0021] The box is provided with an electrical connector, one end of the electrical connector is in the box, and the other end of the electrical connector is outside the box.

[0022] One end of the electrical connector is connected to the other end of the first power supply interface through a first connecting line, and the other end of the electrical connector is connected to the other end of the second power supply interface through a second connecting line.

[0023] Optionally, the high acceleration stress test device further comprises:

[0024] A temperature adjusting module configured to adjust the temperature in the box.

[0025] a humidity adjusting module configured to adjust humidity in the box;

[0026] a gas pressure adjusting module configured to adjust gas pressure in the box.

[0027] The application has the beneficial effect that the test unit arranged in the box comprises a plurality of test seats, each test seat being configured to test the to-be-tested chip when the to-be-tested chip is placed; the test unit is connected with the power supply through the power supply control unit arranged outside the box; the power supply control unit comprises a plurality of switch assemblies, one end of each switch assembly being connected with the power supply; the plurality of test seats are divided into at least two groups, each group of test seats being connected with the other end of one switch assembly, and the power supply control unit can supply power to each group of test seats by using the plurality of switch assemblies; since the power supply control unit is arranged outside the box, when the current output by the power supply is higher than the preset range in the high-acceleration stress test, each group of test seats causing the abnormal current output of the power supply can be directly checked out by sequentially turning on or turning off each switch assembly to control whether each group of test seats in the box is supplied with power, so that the time required for troubleshooting is effectively shortened. The high-acceleration stress test device provided by the application can more quickly check out each group of test seats causing the abnormal current output of the power supply when the current output by the power supply is greater than the preset range, and turn off the switch assembly corresponding to each group of test seats with an abnormality, so as to isolate the abnormal test seat without stopping the high-acceleration stress test. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0029] Figure 1 is a structural schematic diagram of an embodiment of the high-acceleration stress test device provided by the application;

[0030] Figure 2 is a structural schematic diagram of another embodiment of the high-acceleration stress test device provided by the application. DETAILED DESCRIPTION

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0032] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, or apparatuses.

[0033] HAST (Highly Accelerated Stress Test) is an accelerated life test that examines the resistance of packaged chips to moisture intrusion, chemical reactions, and electrochemical reactions under high temperature, high humidity, high pressure, and bias conditions. It is a test used to check the reliability of chip packages. Due to the requirements of the testing environment, a corresponding HAST test board (or simply test board) needs to be designed. A HAST test board typically has multiple test sockets to support multiple chips. The test board is also connected to a power supply to power the chips on the test sockets.

[0034] Generally, high-accelerated stress testing is conducted only after the testing environment meets the requirements (i.e., the environment inside the chamber is adjusted to a high-temperature, high-humidity, and high-pressure environment). Before conducting high-accelerated stress testing, it is necessary to ensure that all chips are in low-power mode (i.e., the power supply output current is within a reasonable range). Due to potential problems with the test board, test socket, and the chips themselves, under high-temperature, high-humidity, high-pressure, and bias conditions, the power supply output current exceeds the reasonable range and does not meet the low-power requirements when initially placed in the high-accelerated stress testing device. This necessitates restoring the high-accelerated stress testing device to normal temperature, humidity, and pressure, removing the test board for troubleshooting (such as replacing the base or chips), and then re-placing the test board in the chamber for heating, humidification, and pressurization checks, repeating this process multiple times. Changing the temperature, humidity, and pressure of the high-accelerated stress testing device takes a very long time, making the entire inspection and debugging process extremely lengthy.

[0035] During high-accelerated stress testing, issues with the test socket or chip may cause an increase in the power supply's output current. This can lead to two problems:

[0036] (1) If timely investigation and isolation cannot be carried out, the test of all chips on the entire test board will be affected due to the uncertainty of high current (high power consumption), which may cause all chips to fail the high accelerated stress test.

[0037] (2) If investigation and isolation are to be carried out, according to the test requirements of high accelerated stress testing, the tested chips need to be kept in a special environment to prevent moisture loss from the package. Under the premise of meeting this test requirement, investigation will become very difficult.

[0038] Please refer to details. Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the high-acceleration stress testing device provided in this application.

[0039] like Figure 1 As shown, the high accelerated stress testing device 10 provided in this application embodiment includes a housing 11, a power control unit 12, and a testing unit 13.

[0040] The power control unit 12 is located outside the housing 11. The power control unit 12 includes multiple switch components 121, one end of which is connected to the power supply 2.

[0041] In some embodiments, power supply 2 is a DC regulated power supply. Optionally, power supply 2 is equipped with an ammeter, so that by obtaining the ammeter reading, it can be determined whether power supply 2 is outputting a large current.

[0042] The test unit 13 is housed within the enclosure 11. The test unit 13 includes multiple test sockets 131, each of which is configured to perform a test on the chip under test 3 when placed thereon. The test unit 13 is connected to the power supply 2 via the power control unit 12.

[0043] Optionally, a single test socket 131 may support placing only a single chip under test 3, or it may support placing multiple chips under test 3.

[0044] The test sockets 131 are divided into at least two groups, and each group of test sockets is connected to the other end of a switch assembly 121. The power control unit 12 can use multiple switch assemblies to supply power to each group of test sockets individually.

[0045] Alternatively, test unit 13 can be presented in the form of a test board.

[0046] Optionally, the power control unit 12 can be presented in the form of a test board or a test box.

[0047] In some possible embodiments, the housing 11 may contain one or more test units 13. Furthermore, a single power control unit 12 may supply power to each set of test sockets in the multiple test units 13. In some possible embodiments, if a single power control unit 12 can supply power to each set of test sockets in the multiple test units 13, the power control unit 12 may be too large. Therefore, a single power control unit 12 may also supply power to each set of test sockets in one test unit 13. This configuration effectively reduces the size of the power control unit 12.

[0048] In some embodiments, each group of test sockets contains only one test socket 131, that is, each test socket 131 corresponds to one switching component 121. For example, the test unit 13 includes 20 test sockets 131. Since each group of test sockets is connected to the other end of a switching component 121, in short, there can be at least 20 switching components 121 on the power control unit. With this configuration, in scenarios where the power supply 2 outputs a large current, the abnormal target test socket and / or the target chip under test located on the target test socket can be identified by turning each switching component 121 on or off. Furthermore, after identifying the abnormal target test socket and / or the target chip under test located on the target test socket, other chips under test can still undergo high-acceleration stress testing by turning off the switching component 121 corresponding to the abnormal target test socket.

[0049] In some possible embodiments, the target chip under test may be a chip under test 3 that is malfunctioning.

[0050] In some embodiments, at least one set of test sockets includes at least two test sockets 131, that is, at least one switching component 121 corresponds to multiple test sockets 131. For example, the test unit 13 includes 20 test sockets 131, with each switching component 121 corresponding to two test sockets 131. In this way, the number of switching components 121 on the power control unit 12 can be reduced to at least 10. This arrangement effectively reduces the number of switching components 121 on the power control unit 12, further reducing the size of the power control unit 12.

[0051] In some embodiments, the switch assembly 121 includes a first switch and a plurality of second switches, one end of the first switch is connected to the power supply 2, one end of each second switch is connected to the other end of the first switch, and each set of test sockets is connected to the other end of the same second switch.

[0052] For example, a single power control unit 12 includes four switching assemblies 121, each of which includes one first switch (not shown) and four second switches (not shown). Further, in this example, the test unit 13 includes 16 test sockets 131, meaning each second switch corresponds to one test socket 131. With this setup, in scenarios where the power supply 2 outputs a large current, the target test socket and / or the target chip under test corresponding to the abnormality can be identified by sequentially turning the four first switches on or off. Further, the second switches under the target first switches are then sequentially turned on or off to determine the abnormal target test socket and / or the target chip under test located on the target test socket. Compared to turning all the second switches on or off one by one, this setup improves the efficiency of the investigation. Furthermore, after identifying the abnormal target test socket and / or the target chip under test located on the target test socket, other chips under test can still undergo high-acceleration stress testing by turning off the second switch corresponding to the abnormal target test socket.

[0053] This example is further described below. If the switching components 121 on the power control unit 12 correspond one-to-one with the test sockets 131, that is, if the power control unit 12 has 16 switching components, for example, if only one target test socket and / or the target chip under test set on the target test socket has an anomaly, a maximum of 16 switching components 121 need to be turned on or off to troubleshoot. If the power control unit 12 includes 4 switching components 121, and each switching component 121 includes 1 first switch and 4 second switches, then in this scenario, a maximum of 8 switching components need to be turned on or off to troubleshoot.

[0054] Optionally, a test interface (not shown) is provided on the test socket 131, and the test interface is coupled to the chip under test 3.

[0055] In some embodiments, at least one test socket 131 has a different test interface type than the other test sockets 131. This configuration allows the test unit to be compatible with chips under test 3 of different test interface types.

[0056] In some possible embodiments, all test sockets 131 have the same test interface type. Understandably, test socket 131 can perform high-accelerated stress testing on different models of the chip under test (DUT) with the same test interface type.

[0057] In some embodiments, the power control unit 12 includes multiple ammeters (not shown), one end of each ammeter connected to one end of each test socket, and the other end of each ammeter connected to the other end of a switching assembly 121. The ammeters are configured to acquire the input current of each test socket 131. This configuration allows for a more intuitive acquisition of the current reading of each test socket, and faster identification of the target test socket with an anomaly and / or the target chip under test located on the target test socket.

[0058] Understandably, placing multiple ammeters on the power control unit 12 would make the power control unit 12 very large. In some possible application scenarios, a current sampling circuit can be used to replace the ammeters. When it is necessary to obtain the current reading of each test socket, the current reading of the current sampling circuit can be directly obtained. In this way, the input current of each test socket 131 can be obtained without significantly increasing the size of the power control unit 12.

[0059] In some embodiments, the test unit 13 includes a test board 133. Optionally, the test socket 131 can be detachably mounted on the test board 133. This configuration allows the number of test sockets 131 in the test unit 13 to be increased or decreased depending on the number of chips 3 under test. Alternatively, the test socket 131 can be replaced with one corresponding to the test interface type of the chip 3 under test. These configurations improve the testing flexibility and compatibility of the test unit 13.

[0060] Understandably, the detachable mounting of the test socket 131 onto the test board 133 would significantly increase the cost of the test unit 13. In some applications, to reduce costs and / or increase the number of uses of the test board 133, the test socket 131 is soldered onto the test board 133.

[0061] Optionally, a protective layer is provided on the surface of the test board 133 to improve its resistance to high temperature, high humidity, and high pressure environments during high accelerated stress testing. For example, the protective layer is formed by coating the surface of the test board 133 with conformal coating or a solid adhesive resistant to high temperature, high humidity, and high pressure.

[0062] In some embodiments, the power control unit 12 is provided with a first power supply interface 125, one end of which is connected to the other end of the switch assembly 121, and the test board 133 is provided with a second power supply interface 134, one end of which is connected to the test socket 131.

[0063] Optionally, an electrical connector 14 is provided on the housing 11, with one end 141 inside the housing 11 and the other end 142 outside the housing 11.

[0064] In some possible embodiments, the electrical connector 14 extends through the housing 11.

[0065] It should be noted that during the high accelerated stress test, the enclosure 11 needs to remain sealed, and the power control unit 12 cannot be directly electrically connected to the test unit 13. By providing an electrical connector 14 on the enclosure 11, the power control unit 12 and the test unit 13 can be electrically connected through the electrical connector 14.

[0066] Furthermore, one end 141 of the electrical connector 14 is connected to the other end of the first power supply interface 125 via a first connecting line 15, and the other end 142 of the electrical connector 14 is connected to the other end of the second power supply interface 134 via a second connecting line 16.

[0067] In some possible embodiments, electrical connector 14 is an aviation electrical connector (aviation plug).

[0068] In some embodiments, the high accelerated stress testing device 10 further includes a temperature regulation module, a humidity regulation module, and an air pressure regulation module.

[0069] The temperature control module is configured to regulate the temperature inside the chamber 11. The humidity control module is configured to regulate the humidity inside the chamber 11. The air pressure control module is configured to regulate the air pressure inside the chamber 11.

[0070] For example, the high accelerated stress testing device 10 can provide a test unit 13 with the chip under test 3 installed with HAST test under the conditions of 130°C, 85% RH humidity, 230 kPa atmospheric pressure, 96 hours, 5.5V voltage or 110°C, 85% RH humidity, 122 kPa atmospheric pressure, 264 hours, 5.5V voltage.

[0071] The above solution involves a test unit housed within the enclosure, comprising multiple test sockets. Each test socket is configured to test the chip under test (DUT) when placed inside. The test unit is connected to a power supply via a power control unit located outside the enclosure. The power control unit includes multiple switching components, one end of which is connected to the power supply. The test sockets are divided into at least two groups, with each group connected to the other end of a switching component. The power control unit can individually power each group of test sockets using these switching components. Because the power control unit is located outside the enclosure, during high-acceleration stress testing, if the power supply output current exceeds a preset range, it can directly control the power supply status of each group of test sockets inside the enclosure by sequentially turning each switching component on or off. This allows for the identification of each group of test sockets causing abnormal power supply output current. This eliminates the need to first stop testing all chips under test, spend significant time changing the testing environment inside the enclosure, and then open the enclosure to troubleshoot each test socket individually, effectively shortening the time required for troubleshooting. The high accelerated stress testing device provided in this application can more quickly identify each group of test sockets that cause abnormal power output current when the current output by the power supply exceeds a preset range, and shut down the switching components corresponding to each abnormal group of test sockets, thereby isolating the abnormal test sockets without stopping the high accelerated stress test.

[0072] like Figure 2 As shown, Figure 2 This is a schematic diagram of another embodiment of the high-acceleration stress testing device provided in this application.

[0073] The high-accelerated stress testing device 20 in this embodiment includes a housing 21, a power control board 22, and a HAST test board 23. The HAST test board 23 is disposed inside the housing 21, and the power control board 22 is disposed outside the housing 21.

[0074] Among them, the HAST test board 23 corresponds to the test unit 13 mentioned above, and the power control board 22 corresponds to the power control unit 12 mentioned above.

[0075] Specifically, the power control board 22 includes multiple switches 221, power connectors 222, and a first power connection socket 223. For example, the power control board 22 includes four switches 221. It should be noted that this application does not limit the number of switches 221 on the power control board 22.

[0076] Furthermore, one end of switch 221 is electrically connected to power connector 222, and the other end of switch 221 is electrically connected to first power connector 223.

[0077] The power connector 222 is used for electrical connection with the power supply 6.

[0078] In some embodiments, power supply 6 is a DC regulated power supply. Optionally, power supply 6 is equipped with an ammeter to obtain the current output current of power supply 6.

[0079] Specifically, the HAST test board 23 includes multiple test sockets 231. Each test socket 231 is configured to perform high-stress accelerated testing on at least one chip under test 7.

[0080] For example, the HAST test board 23 includes four test sockets 231. It should be noted that this application does not limit the number of test sockets 231 on the HAST test board 23.

[0081] In some possible embodiments, in order to increase the compatibility of the test socket 231 with the chip under test 7 of different interface types, the chip under test 7 of different interfaces can be coupled to the adapter, and the adapter is then coupled to the test socket.

[0082] Furthermore, the HAST test board 23 also includes a second power connector 232. In some embodiments, each test connector 231 is electrically connected to the second power connector 232.

[0083] Among them, the second power connector 232 corresponds to the second power supply interface 134 mentioned above, and the first power connector 223 corresponds to the first power supply interface 125 mentioned above.

[0084] Furthermore, an electrical connector 24 is provided on the housing 21, with one end 241 of the electrical connector 24 located inside the housing 21 and the other end 242 located outside the housing.

[0085] Furthermore, the second power connector 232 is electrically connected to one end 241 of the electrical connector 24 via the first connecting line 25, and the first power connector 223 is electrically connected to the other end 242 of the electrical connector 24 via the second connecting line 26.

[0086] In some possible embodiments, the first power connector 223 and the second power connector 232 can be power connectors. Exemplarily, the first power connector 223 and the second power connector 232 can be any of an industrial power connector or an aviation power connector.

[0087] In this embodiment, each switch 221 supplies power to each test socket 231 individually. Understandably, when a switch 221 is turned off, the power supply to the test socket 231 corresponding to that switch 221 is turned off, that is, the chip under test 7 on the test socket 231 stops the high-acceleration stress test.

[0088] During actual testing, the HAST test board 23 is placed inside the housing 21, while the power control board 22 is outside the housing 21. The HAST test board 23 and the power control board 22 are electrically connected via a first connecting line 25, an electrical connector 24, and a second connecting line 26. In scenarios where anomalies occur during high-accelerated stress testing, requiring troubleshooting and isolation, the faulty test socket 231 and / or the faulty chip under test 7 can be identified by turning the switch 221 on the power control board 22 on or off. Furthermore, once the faulty test socket 231 and / or the faulty chip under test 7 are identified, the electrical connection between the test socket 231, the chip under test 7, and the power supply 6 is isolated by turning off the corresponding switch.

[0089] The above solution involves a test unit housed within the enclosure, comprising multiple test sockets. Each test socket is configured to test the chip under test (DUT) when placed inside. The test unit is connected to a power supply via a power control unit located outside the enclosure. The power control unit includes multiple switching components, one end of which is connected to the power supply. The test sockets are divided into at least two groups, with each group connected to the other end of a switching component. The power control unit can individually power each group of test sockets using these switching components. Because the power control unit is located outside the enclosure, during high-acceleration stress testing, if the power supply output current exceeds a preset range, it can directly control the power supply status of each group of test sockets inside the enclosure by sequentially turning each switching component on or off. This allows for the identification of each group of test sockets causing abnormal power supply output current. This eliminates the need to first stop testing all chips under test, spend significant time changing the testing environment inside the enclosure, and then open the enclosure to troubleshoot each test socket individually, effectively shortening the time required for troubleshooting. The high accelerated stress testing device provided in this application can more quickly identify each group of test sockets that cause abnormal power output current when the current output by the power supply exceeds a preset range, and shut down the switching components corresponding to each abnormal group of test sockets, thereby isolating the abnormal test sockets without stopping the high accelerated stress test.

[0090] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A high-acceleration stress testing device, characterized in that, The high-acceleration stress testing device includes: Box; A power control unit is located outside the enclosure. The power control unit includes multiple switching assemblies, one end of which is connected to a power source. A test unit is disposed within the enclosure; the test unit includes multiple test sockets, each of which is configured to test the chip under test when the chip under test is placed thereon; the test unit is connected to a power supply via the power control unit. The plurality of test sockets are divided into at least two groups, each group of test sockets is connected to the other end of a switching assembly, and the power control unit can use the plurality of switching assemblies to individually power each group of test sockets.

2. The high-acceleration stress testing device according to claim 1, characterized in that, Each set of test sockets contains only one of the aforementioned test sockets.

3. The high-acceleration stress testing device according to claim 1, characterized in that, At least one set of test sockets contains at least two of the test sockets.

4. The high-acceleration stress testing device according to claim 1, characterized in that, The switching assembly includes a first switch and a plurality of second switches, one end of the first switch being connected to the power supply; One end of each second switch is connected to the other end of the first switch, and each test socket in each group of test sockets is connected to the other end of the same second switch.

5. The high-acceleration stress testing device according to claim 1, characterized in that, The test socket is provided with a test interface, which is coupled to the chip under test; Among them, at least one test socket has a test interface type that is different from the test interface types of other test sockets.

6. The high-acceleration stress testing device according to any one of claims 1-5, characterized in that, The power control unit includes multiple ammeters, one end of each ammeter is connected to one end of each set of test sockets, and the other end of each ammeter is connected to the other end of a switching assembly. The ammeters are configured to acquire the input current of each set of test sockets.

7. The high-acceleration stress testing device according to claim 1, characterized in that, The test unit includes a test board, and the test socket is detachably mounted and / or welded onto the test board.

8. The high-acceleration stress testing device according to claim 7, characterized in that, The surface of the test board is provided with a protective layer.

9. The high-acceleration stress testing device according to claim 7, characterized in that, The power control unit is provided with a first power supply interface, one end of which is connected to the other end of the switch assembly. The test board is provided with a second power supply interface, one end of which is connected to the test socket; An electrical connector is provided on the housing, with one end of the electrical connector inside the housing and the other end outside the housing; One end of the electrical connector is connected to the other end of the first power supply interface via a first connecting line, and the other end of the electrical connector is connected to the other end of the second power supply interface via a second connecting line.

10. The high-acceleration stress testing device according to claim 1, characterized in that, The high-acceleration stress testing device also includes: The temperature control module is configured to regulate the temperature inside the enclosure; A humidity control module is configured to regulate the humidity inside the enclosure; The air pressure regulating module is configured to regulate the air pressure inside the box.

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