High and low temperature test board of stamp hole core board
By designing a high and low temperature test board for the stamp perforation core board and adopting a half-hole test probe and communication method, the problems of low efficiency and high cost of batch testing of the core board in high and low temperature environments were solved, realizing efficient and low-cost testing and troubleshooting.
Patent Information
- Application Number
- CN202520569683.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-03-28
AI Technical Summary
In existing technologies, the batch aging test of industrial-grade core boards in high and low temperature environments is inefficient, costly, difficult to locate problems, and requires a large amount of maintenance work.
A high and low temperature test board for a stamp perforation core board was designed. It adopts half-hole test probes and communication methods such as RS485, USB, and UART. Combined with the core board slots and test circuits, it realizes efficient program burning, functional interface testing and status monitoring of the core board, and supports multi-layer stacking.
It enables efficient batch testing of core boards in high and low temperature environments, reduces testing costs, simplifies troubleshooting and repair processes, and improves testing efficiency.
Smart Images
Figure CN223827776U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip testing technology, and in particular relates to a high and low temperature test board for a stamp hole core board. Background Technology
[0002] Industrial-grade core boards typically operate at temperatures ranging from -40℃ to 70℃, requiring batch aging tests in corresponding high and low temperature environments. The conventional testing method involves soldering the core board into the complete product, programming it, and then placing the entire product in a high and low temperature alternating humidity test chamber for aging testing. When problems arise, it's necessary to investigate whether the issue lies with the core board's peripheral circuitry. Furthermore, repairs often require complete disassembly and replacement of the entire core board, making problem localization difficult and resulting in a large workload. In batch testing, the overall volume occupied by the test chamber is excessive, and the amount of equipment that can be placed within a single high and low temperature alternating humidity test chamber is limited, leading to low testing efficiency and high testing costs. Utility Model Content
[0003] Purpose of the utility model: The technical problem to be solved by this utility model is to provide a high and low temperature test plate for a stamp perforation core plate, which addresses the shortcomings of the existing technology.
[0004] To address the aforementioned technical problems, this utility model discloses a high and low temperature test board for a stamp perforation core board, comprising at least one core board slot and a core board test circuit corresponding to the core board slot. Half-hole test pins are arranged around the core board slot. The stamp perforation core board to be tested is placed in the core board slot, and the stamp holes of the core board are adapted and connected to the half-hole test pins. The core board test circuit is used to test the programming function and functional interfaces of the stamp perforation core board to be tested. The functional interfaces include USB, I2C, SPI, ADC, GPIO, RS485, and UART interfaces.
[0005] Furthermore, the core board test circuit includes a UART to USB circuit and a USB-HUB circuit. The UART to USB circuit is used to convert the UART0 signal of the stamp hole core board under test into a USB signal. The USB-HUB circuit is used to connect the USB signal to the HUB chip and bring it out through the USB interface for program debugging.
[0006] The USB0 pin of the stamp hole core board to be tested is connected to a USB vertical interface for programming the stamp hole core board to be tested.
[0007] Furthermore, the core board test circuit also includes an RS485 circuit and an SPI circuit. The RS485 circuit is used to convert the UART7 signal of the stamp hole core board under test into an RS485 signal, which is brought out through a unified interface for operation monitoring and data transmission of various functional interfaces of the stamp hole core board under test.
[0008] The SPI circuit is used to connect to the SPI pin of the stamp hole core board under test, and to communicate with the ESAM chip. The ESAM chip encrypts the communication data, thereby verifying the SPI function of the core board.
[0009] Furthermore, the core board test circuit also includes an ADC circuit, which is connected to the ADC pin of the stamp hole core board under test to detect the ADC function of the core board.
[0010] Furthermore, the core board test circuit also includes an RTC circuit, which is connected to the I2C pin of the stamp hole core board under test to detect the I2C communication function of the core board.
[0011] Furthermore, the core board test circuit also includes an EEPROM circuit, which is connected to the I2C pin of the stamp hole core board under test, and is used to detect the I2C communication function of the core board and store data.
[0012] Furthermore, it also includes a PC host computer, which is connected to the core board testing circuit. The PC host computer periodically checks each operating core board via an RS485 circuit, and the core board sequentially feeds back its current operating status to the PC host computer. When a core board malfunctions or changes its operating status, the host computer uses a UART0 to USB circuit to debug and monitor the tested core board. The RS485 circuit is mainly used for large-scale, long-term monitoring of high and low temperature chambers, and the types of information transmitted are limited. The UART0 to USB circuit is mainly used for debugging small-batch equipment at room temperature.
[0013] Furthermore, it includes multiple layers, each layer containing 8 core board slots; the layers are connected via RS485 signals. With multiple slots and stacked configurations, the test board occupies a small space.
[0014] Furthermore, it also includes a first 12V power adapter, and the core board test circuit includes a first 12V to 5V circuit. The first 12V power adapter is used to power the first 12V to 5V circuit, and the first 12V to 5V circuit is used to provide power to the stamp hole core board to be tested and the corresponding core board test circuit.
[0015] Furthermore, it also includes a second 12V power adapter and a second 12V to 5V circuit, wherein the second 12V power adapter is used to power the second 12V to 5V circuit, and the second 12V to 5V circuit is used to provide power to the RS485 circuit.
[0016] Beneficial effects: The test board provided in this application can hold multiple core boards and can communicate with the core boards in real time via RS485, USB, UART and other communication methods to record the operating status of the core boards. The core boards are connected to the test board through half-hole test pins. This connection method is simple in structure and low in cost. The core board under test can be disassembled at any time, which is convenient for troubleshooting and maintenance. Attached Figure Description
[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.
[0018] Figure 1 This is a schematic diagram of the structure of a high and low temperature test plate for a stamp perforation core plate provided in an embodiment of this application.
[0019] Figure 2 This is another structural schematic diagram of a high and low temperature test plate for a stamp perforation core plate provided in an embodiment of this application.
[0020] Figure 3 This is a schematic diagram of the interface of a stamp perforation core plate provided in an embodiment of this application.
[0021] Figure 4 This is a schematic diagram of the structure of a stamp perforation core plate provided in an embodiment of this application.
[0022] Figure 5 This is a schematic diagram showing the connection between the core board test circuit and the core board under test in a high and low temperature test board for a stamp perforation core board provided in an embodiment of this application.
[0023] Figure 6 This is a schematic diagram of the SPI circuit of the core board test circuit in a high and low temperature test board of a stamp hole core board provided in an embodiment of this application.
[0024] Figure 7 This is a schematic diagram of the EEPROM circuit of the core board test circuit in a high and low temperature test board of a stamp hole core board provided in an embodiment of this application.
[0025] Figure 8 This is a schematic diagram of the ADC circuit of the core board test circuit in a high and low temperature test board of a stamp hole core board provided in an embodiment of this application.
[0026] Figure 9This is a schematic diagram of the RTC circuit of the core board test circuit in a high and low temperature test board for a stamp hole core board provided in an embodiment of this application.
[0027] Figure 10 This is a schematic diagram of a USB-HUB circuit for a core board test circuit in a high and low temperature test board of a stamp hole core board provided in an embodiment of this application.
[0028] Figure 11 This is a schematic diagram of the UART to USB circuit of the core board test circuit in a high and low temperature test board of a stamp hole core board provided in an embodiment of this application.
[0029] Figure 12 This is a schematic diagram of the RS485 circuit of the core board test circuit in a high and low temperature test board for a stamp hole core board provided in an embodiment of this application.
[0030] Figure 13 A physical image of a high and low temperature test plate for a stamp perforation core plate provided in an embodiment of this application.
[0031] Figure 14 Another physical image of a high and low temperature test plate for a stamp perforation core plate provided in this application embodiment.
[0032] Figure 15 A physical image of a high and low temperature test plate for a stamp perforation core plate provided in this application embodiment, showing the core plate installed in the core plate slot. Detailed Implementation
[0033] The embodiments of this utility model will now be described with reference to the accompanying drawings.
[0034] Existing testing fixtures for stamp perforated core boards primarily rely on jigs, requiring multiple structural components. These components are bulky, have high manufacturing requirements, and cannot be placed in high and low temperature chambers for testing. Furthermore, high and low temperature testing is often performed on the entire machine, resulting in low testing efficiency, difficult maintenance, and an inability to meet the needs of batch testing and screening of core boards. This invention replaces the complex structural components with a half-hole test probe and, supplemented by communication methods such as RS485, USB, and UART, enables efficient testing of the high and low temperature performance of stamp perforated core boards.
[0035] This utility model is mainly used for batch screening and troubleshooting of core boards in high and low temperature environments, in order to determine the high and low temperature performance of individual core boards, screen out defective core boards, and provide a low-cost, simple, and efficient high and low temperature test board for core boards.
[0036] This application discloses a high and low temperature test plate for a stamp perforation core plate, such as... Figure 1 As shown, it includes at least one core board slot and a core board test circuit corresponding to the core board slot, such as... Figure 13As shown, a half-hole test probe is provided around the core board slot, such as... Figure 15 As shown, the stamp hole core plate to be tested is placed in the core plate slot, and the stamp hole of the core plate is adapted and connected to the half-hole test probe; in the specific implementation process, the stamp hole of the core plate is as follows: Figure 4 As shown, the interface distribution of the core board can be as follows: Figure 3 As shown. The core board test circuit is used to test the programming function and functional interfaces of the stamp hole core board under test. The functional interfaces include USB, I2C, SPI, ADC, GPIO, RS485 and UART interfaces.
[0037] like Figure 2 and Figure 5 As shown, the core board test circuit includes a UART-to-USB circuit and a USB-HUB circuit. The UART-to-USB circuit converts the UART0 signal of the stamp hole core board under test into a USB signal. The USB-HUB circuit connects the USB signal to a HUB chip (e.g., connecting the USB signals in groups of three to the HUB chip), and outputs the signal through a USB interface for program debugging. In specific implementation, the following can be used: Figure 11 The UART to USB circuit shown and such Figure 10 The USB-HUB circuit shown. Figure 11 In the core board, UART0 (PIN61, 62) is connected to the serial-to-USB chip U4 via the isolation chip U5. After conversion by U4, the serial port signal is converted into a USB signal and output to the USB-HUB circuit. Figure 10 Middle, three routes Figure 11 The USB signal is connected to the USB-HUB chip U6, and the U6 integrates the signal into a single USB output through the USB interface J1.
[0038] The USB0 pin of the stamp hole core board under test is connected to a USB vertical interface for programming the stamp hole core board. During programming, the UBOOT pin of the core board needs to be shorted to ground through the reserved pins on the test board, and the core board will then enter programming mode.
[0039] The core board test circuit also includes an RS485 circuit and an SPI circuit. The RS485 circuit is used to convert the UART7 signal of the stamp hole core board under test into an RS485 signal, which is brought out through a unified interface for operation monitoring and data transmission of various functional interfaces of the stamp hole core board under test.
[0040] The SPI circuit is connected to the SPI pin of the stamp hole core board under test and is used to communicate with the ESAM chip. The ESAM chip encrypts the communication data to verify the SPI communication function of the core board.
[0041] In the specific implementation process, the following can be adopted: Figure 12 The RS485 circuit shown is as follows: Figure 6 The SPI circuit shown. Figure 12 In the process, the UART1 (PIN109~111) of the core board is connected to the serial port to RS485 chip U8 through the isolation chip U7. After conversion by U8, the serial port signal is converted into an RS485 signal, which is then connected in parallel with the RS485 signals of the other core boards under test and output through the terminal block. Figure 6 In the core board, SPI4 (PIN 129~132) is connected to the SPI pins (PIN1, 2, 5, 6) of the ESAM chip U9. The encryption key is obtained through SPI communication to verify the SPI communication function.
[0042] The core board test circuit also includes an ADC circuit, which is connected to the ADC pins of the stamp perforation core board under test to detect the ADC function of the core board. In specific implementation, methods such as... Figure 8 The ADC circuit shown. Figure 8 In the process, the battery voltage VBAT is connected to the ADC0 pin (PIN105) of the core board through two voltage divider resistors. The accuracy of the voltage read by ADC0 is used to verify the ADC function.
[0043] The core board test circuit also includes an RTC circuit, which is connected to the I2C pin of the stamp hole core board under test to detect the I2C communication function of the core board. In specific implementation, methods such as... Figure 9 The RTC circuit shown. Figure 9 In the process, the I2C2 (PIN117,118) of the core board is connected to the RTC chip U3. The core board obtains time information from the RTC chip through I2C communication, and at the same time verifies the I2C communication function.
[0044] The core board test circuit also includes an EEPROM circuit, which is connected to the I2C pin of the stamp hole core board under test to detect the I2C communication function of the core board and store data. Figure 7 In the process, the I2C3 (PIN121,122) of the core board is connected to the EEPROM chip U11. Through I2C communication, the core board writes some program running information and time information into the EEPROM, waiting for the PC host computer to read the information, and at the same time verifying the I2C communication function.
[0045] This also includes PC host computers, such as Figure 1 As shown, the PC host computer is connected to the core board test circuit. The PC host computer periodically checks each running core board via an RS485 circuit, and the core board sequentially reports its current operating status to the PC host computer. The PC host computer collects and processes the data transmitted via the RS485 circuit. When a core board malfunctions or changes its operating state, the host computer uses a UART0-to-USB circuit to debug and monitor the core board under test.
[0046] like Figure 14 As shown, the high and low temperature test plate of the stamp hole core plate includes multiple layers, each layer including 8 core plate slots; the layers are connected by RS485 signal. Figure 14 The green 3-pin threaded terminal block is an RS485 signal line. RS485 signal lines can be connected in parallel in large numbers, and layers are connected through it; the light yellow pillar is used for core board stacking.
[0047] like Figure 2 As shown, it also includes a first 12V power adapter. The core board test circuit includes a first 12V to 5V circuit. The first 12V power adapter is used to power the first 12V to 5V circuit. The first 12V to 5V circuit is used to provide power to the stamp hole core board to be tested and the corresponding core board test circuit.
[0048] It also includes a second 12V power adapter and a second 12V to 5V circuit, the second 12V power adapter being used to power the second 12V to 5V circuit, and the second 12V to 5V circuit being used to provide power to the RS485 circuit.
[0049] This utility model provides a high and low temperature testing plate for a stamp perforation core plate. There are many methods and approaches to implement this technical solution; the above description is only a preferred embodiment of this utility model. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model. All components not explicitly stated in this embodiment can be implemented using existing technology.
Claims
1. A high and low temperature test plate for a stamp perforation core plate, characterized in that, The device includes at least one core board slot and a core board test circuit corresponding to the core board slot. Half-hole test probes are arranged around the core board slot. The stamp hole core board to be tested is placed in the core board slot, and the stamp hole of the core board is adapted to be connected with the half-hole test probes. The core board test circuit is used to test the programming function and functional interfaces of the stamp hole core board to be tested. The functional interfaces include USB, I2C, SPI, ADC, GPIO, RS485 and UART interfaces.
2. A high-low temperature test board for a postage stamp aperture core board according to claim 1, wherein, The core board test circuit includes a UART to USB circuit and a USB-HUB circuit. The UART to USB circuit is used to convert the UART0 signal of the stamp hole core board under test into a USB signal. The USB-HUB circuit is used to connect the USB signal to the HUB chip and bring it out through the USB interface for program debugging. The USB0 pin of the stamp hole core board to be tested is connected to a USB vertical interface for programming the stamp hole core board to be tested.
3. A high and low temperature test board for a stamp hole core board according to claim 2, characterized in that, The core board test circuit also includes an RS485 circuit and an SPI circuit. The RS485 circuit is used to convert the UART7 signal of the stamp hole core board under test into an RS485 signal, which is brought out through a unified interface for operation monitoring and data transmission of various functional interfaces of the stamp hole core board under test. The SPI circuit is connected to the SPI pin of the core board of the stamp hole to be tested, and is used to communicate with the ESAM chip. The ESAM chip encrypts the communication data, thereby verifying the SPI function of the core board.
4. The high and low temperature test plate for a stamp perforation core plate according to claim 3, characterized in that, The core board test circuit also includes an ADC circuit, which is connected to the ADC pin of the stamp hole core board under test to detect the ADC function of the core board.
5. The high and low temperature test plate for a stamp perforation core plate according to claim 4, characterized in that, The core board test circuit also includes an RTC circuit, which is connected to the I2C pin of the stamp hole core board under test to test the I2C communication function of the core board.
6. The high and low temperature test plate for a stamp perforation core plate according to claim 5, characterized in that, The core board test circuit also includes an EEPROM circuit, which is connected to the I2C pin of the stamp hole core board under test to detect the I2C communication function of the core board and store data.
7. The high and low temperature test plate for a stamp perforation core plate according to claim 6, characterized in that, It also includes a PC host computer, which is connected to the core board test circuit. The PC host computer uses an RS485 circuit to periodically check each running core board, and the core board sequentially feeds back its current running status to the PC host computer. When a core board malfunctions or switches its running status, the host computer uses a UART0 to USB circuit to debug and monitor the core board under test.
8. The high and low temperature test plate for a stamp perforation core plate according to claim 7, characterized in that, It includes multiple layers, each layer containing 8 core board slots; the layers are connected via RS485 signals.
9. A high and low temperature test plate for a stamp perforation core plate according to claim 8, characterized in that, It also includes a first 12V power adapter, and the core board test circuit includes a first 12V to 5V circuit. The first 12V power adapter is used to power the first 12V to 5V circuit, and the first 12V to 5V circuit is used to provide power to the stamp hole core board to be tested and the corresponding core board test circuit.
10. A high and low temperature testing plate for a stamp perforation core plate according to claim 9, characterized in that, It also includes a second 12V power adapter and a second 12V to 5V circuit, the second 12V power adapter being used to power the second 12V to 5V circuit, and the second 12V to 5V circuit being used to provide power to the RS485 circuit.