Display panel and display device
By designing a display panel structure in an electronic paper display device with the gate and grid lines in the same direction, the pixel electrode area is increased, which solves the problem of limited display performance in the prior art, achieves better display effect and control of charged particles, and avoids image retention.
Patent Information
- Application Number
- CN202520195627.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-07
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-02-07
AI Technical Summary
In existing electronic paper display devices, the pixel electrode area is relatively small, which limits display performance, makes it difficult to display images accurately in a short time, and easily leads to problems such as image retention.
Design a display panel in which the length direction of the gate is the same as the length direction of the connected gate line, and the overlap area between the gate's orthogonal projection on the substrate and the pixel area is small, avoiding the top gate effect between the pixel electrode and the transistor. At the same time, increase the overlap area between the pixel electrode's orthogonal projection on the substrate and the pixel area, reduce leakage current through hollow parts, and increase the area of the pixel electrode by setting protrusions.
It effectively avoids the top grid effect, increases the overlap area between the ink layer and the pixel electrode, improves the control of charged particles, avoids image ghosting, and enhances the display effect.
Smart Images
Figure CN223827941U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND
[0002] Electronic paper display device has the advantages of convenient reading, convenient carrying, resource saving, low energy consumption, fast transmission speed, etc., and therefore has broad development prospects.
[0003] The area ratio of the pixel electrode of the existing electronic paper display device in the pixel area is small, which affects the display performance of the electronic paper display device. CONTENT OF THE UTILITY MODEL
[0004] The present application provides a display panel and a display device.
[0005] The first aspect of the present application provides a display panel, comprising:
[0006] a substrate;
[0007] a plurality of gate lines arranged on one side of the substrate and extending along a first direction;
[0008] a plurality of data lines arranged on one side of the substrate and extending along a second direction; the first direction intersects the second direction; the gate lines and the data lines enclose a plurality of pixel areas;
[0009] a plurality of pixel electrodes, each of which is located in one of the pixel areas;
[0010] a plurality of transistors, each of which comprises a gate electrode, each of the gate electrodes is connected to one of the gate lines, and the length direction of the gate electrode is the same as the first direction; the orthogonal projection of the gate electrode on the substrate and the orthogonal projection of the gate line on the substrate do not overlap with the orthogonal projection of the pixel electrode on the substrate.
[0011] In one embodiment, the gate electrode of each of the transistors comprises a first gate electrode and a second gate electrode; each of the transistors further comprises a connecting portion, the first gate electrode and the second gate electrode are connected through the connecting portion; the first gate electrode, the connecting portion and the second gate electrode are arranged along the length direction of the gate line connected thereto.
[0012] In one embodiment, the connecting portion is provided with a hollow portion; the transistor further comprises a first electrode and a second electrode, the orthogonal projection of the hollow portion on the substrate overlaps with the orthogonal projection of the first electrode and / or the second electrode on the substrate.
[0013] In one embodiment, the orthogonal projection of the hollow portion on the substrate is entirely within the orthogonal projection of the first electrode and / or the second electrode on the substrate.
[0014] In one embodiment, in the width direction of the connecting portion, the width of the cutout portion is greater than half the width of the connecting portion.
[0015] In one embodiment, the pixel electrode includes a main body and a protrusion extending from at least one side of the main body, wherein the orthographic projection of the protrusion on the substrate is located between the orthographic projection of the main body on the substrate and the orthographic projection of the gate line on the substrate.
[0016] In one embodiment, the width of the gate line is smaller than the width of the gate in a direction perpendicular to the length direction of the gate line; the orthographic projection of the protrusion on the substrate is opposite to the orthographic projection of the adjacent gate line on the substrate.
[0017] In one embodiment, the distance between the orthographic projection of the main body portion on the substrate and the orthographic projection of the adjacent gate on the substrate ranges from 10 μm to 15 μm.
[0018] In one embodiment, the display panel includes a display area and a bonding area surrounding the display area; the pixel area is located in the display area; the bonding area includes a plurality of connection terminals and an insulating layer located on the side of the connection terminals away from the substrate, the insulating layer having a plurality of openings, each opening including a portion of the surface of one of the connection terminals; at least one opening corresponding to at least one of the connection terminals is an elongated opening.
[0019] In one embodiment, the extension direction of the elongated opening is parallel to the length direction of the corresponding connecting terminal.
[0020] In one embodiment, at least one of the connection terminals is opposite only one opening, and the opening is an elongated opening.
[0021] A second aspect of this application provides a display device, which displays the display panel described above.
[0022] When the length direction of the gate and the length direction of the gate line connected to it are the same in the display panel provided in this application embodiment, the overlap area between the orthogonal projection of the gate on the substrate and the orthogonal projection of the pixel area on the substrate is small, and the orthogonal projection of the gate on the substrate does not overlap with the orthogonal projection of the pixel electrode on the substrate. Therefore, while avoiding the top-gate effect between the pixel electrode and the transistor, the overlap area between the orthogonal projection of the pixel electrode on the substrate and the orthogonal projection of the pixel area on the substrate can be increased. This further increases the overlap area between the orthogonal projection of the ink layer on the substrate and the orthogonal projection of the pixel electrode on the substrate, which is more conducive to the control of charged particles in the ink layer, so that the charged particles are arranged in a predetermined position in a short time, avoiding the display screen display image from having afterimages and other defects.
[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0025] Figure 1 A partial structural diagram of a display panel provided for related technologies;
[0026] Figure 2 This is a partial structural schematic diagram of a display panel provided in one embodiment of this application;
[0027] Figure 3 for Figure 2 The illustrated embodiment provides a cross-sectional view of the display panel cut along the BB direction;
[0028] Figure 4 A partial structural schematic diagram of the bonding area of a display panel provided in an embodiment of this application;
[0029] Figure 5 for Figure 4 The illustrated embodiment provides a cross-sectional view of the bonding area of the display panel cut along the CC direction;
[0030] Figure 6 A partial structural schematic diagram of the bonding area of a display panel provided in another embodiment of this application;
[0031] Figure 7 for Figure 6 The illustrated embodiment provides a cross-sectional view of the bonding area of the display panel cut along the DD direction;
[0032] Figure 8 This is a partial structural diagram of the binding area of a display panel provided in another embodiment of this application. Detailed Implementation
[0033] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0034] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0035] The display panel and display device of the present application embodiments will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can complement or combine with each other.
[0036] Electronic paper display devices include a display panel, Figure 1 This is a schematic diagram of the structure of an electronic paper substrate in related technologies. For example... Figure 1 As shown, the display panel includes a substrate 10', a gate line GL', a data line DL', a pixel electrode 20', and a transistor 30'. The gate line GL' and the data line DL' form a pixel area, and the transistor 30' and the pixel electrode 20' are located within the pixel area. Transistor 30' includes gate 31'. To avoid top-gate effect, the orthogonal projection of pixel electrode 20' on substrate 10' and the orthogonal projection of gate 31' on substrate 10' should not overlap. Therefore, when the length direction of gate 31' is perpendicular to the length direction of gate line GL', the area of transistor 30' in the pixel area enclosed by gate line GL' and data line DL' is relatively large, resulting in a smaller area of pixel electrode in the pixel area. Especially when transistor 30' is a dual-gate transistor, the two gates 31' are arranged side by side, and the area of pixel electrode 20' is even larger. This further reduces the area of pixel electrode 20' and increases the spacing between different pixel electrodes 20'. As a result, ink particles in the ink layer of the electronic paper display device located outside the area corresponding to pixel electrode 20' are difficult to be controlled by the electric field. The electronic paper display device is unable to accurately display images in a short time, leading to problems such as image retention and affecting the display performance of the electronic paper display device.
[0037] This application provides a display panel, such as... Figure 2 As shown, the display panel includes a substrate, multiple gate lines, multiple data lines, multiple pixel electrodes, and multiple transistors.
[0038] A gate line GL is disposed on one side of the substrate 10 and extends along a first direction X, and a data line DL is disposed on one side of the substrate 10 and extends along a second direction Y, wherein the first direction X and the second direction Y intersect. The gate line GL and the data line DL form a plurality of pixel regions. Each pixel electrode 20 is located in one pixel region. The transistor 30 includes a gate 31, each gate 31 being connected to one of the gate lines GL, and the length direction of the gate 31 being the same as the first direction X. The orthographic projection of the gate 31 on the substrate 10 and the orthographic projection of the gate line GL on the substrate 10 do not overlap with the orthographic projection of the pixel electrode 20 on the substrate 10.
[0039] In this embodiment of the application, when the length direction of the gate 31 of the display panel is the same as the length direction of the gate line GL connected to it, the overlap area between the orthogonal projection of the gate 31 on the substrate 10 and the orthogonal projection of the pixel area on the substrate 10 is small, and the orthogonal projection of the gate 31 on the substrate 10 does not overlap with the orthogonal projection of the pixel electrode 20 on the substrate 10. Therefore, while avoiding the top-gate effect between the pixel electrode 20 and the transistor 30, the overlap area between the orthogonal projection of the pixel electrode 20 on the substrate 10 and the orthogonal projection of the pixel area on the substrate 10 can be increased. This further increases the overlap area between the orthogonal projection of the ink layer on the substrate 10 and the orthogonal projection of the pixel electrode 20 on the substrate 10, which is more conducive to the control of charged particles in the ink layer, so that the charged particles are arranged in a predetermined position in a short time, avoiding the display screen display image from having afterimages or other defects.
[0040] In one embodiment, the display panel may be electronic paper, and the display panel may also include an ink layer located on the side of the pixel electrode away from the substrate. The ink layer includes a plurality of electrophoretic capsules. Each electrophoretic capsule may include a capsule body, an electrophoretic solution and charged particles located within the capsule body, wherein the charged particles may include black particles, white particles or colored particles, etc.
[0041] In one embodiment, a transparent electrode layer is further provided on the side of the ink layer away from the substrate. When an electric field is applied between the pixel electrode and the transparent electrode layer, charged particles move under the influence of the electric field. For example, when a negative charge is applied to the transparent electrode layer and a positive charge is applied to the pixel electrode, white particles accumulate on the side of the transparent electrode layer, while black particles accumulate on the side of the pixel electrode. In this case, under the reflection of natural light, the display panel displays a white image. Conversely, when a positive charge is applied to the transparent electrode layer and a negative charge is applied to the pixel electrode, white particles accumulate on the side of the pixel electrode, while black particles accumulate on the side of the transparent electrode layer. In this case, under the reflection of natural light, the display panel displays a black image.
[0042] In one embodiment, such as Figure 2As shown, the first direction X is perpendicular to the second direction Y, and the pixel area enclosed by the gate line GL and the data line DL is rectangular.
[0043] In one embodiment, such as Figure 2 and Figure 3 As shown, the gate 31 of the transistor 30 includes a first gate 311 and a second gate 312. Each transistor 30 also includes a connection portion 313. The first gate 311 and the second gate 312 are connected through the connection portion 313. The first gate 311, the connection portion 313, and the second gate 312 are arranged along the length direction of the gate line GL connected to them. Figure 2 As shown, transistor 30 is a dual-gate transistor. The length directions of the first gate 311 and the second gate 312 are both parallel to the first direction X, and the two gates are arranged along their length directions, that is, along the first direction X. Compared with the arrangement of the first gate 311 and the second gate 312 along their width direction, the above arrangement can effectively reduce the total area of the dual-gate transistor, thereby reducing the area ratio of gate 31 in the pixel area and increasing the area ratio of pixel electrode 20 in the pixel area, which is beneficial to improving the display effect of the display panel.
[0044] In one embodiment, such as Figure 2 and Figure 3 As shown, the connection portion 313 has a cutout portion 314. The transistor 30 also includes a first electrode 321, a second electrode 322, and an active layer 33 located between the first electrode 321, the second electrode 322, and the gate 31. The orthogonal projection of the second electrode 322 on the substrate 10 overlaps with the orthogonal projections of the first gate 311 and the second gate 312 on the substrate 10. The orthogonal projection of the cutout portion 314 on the substrate 10 overlaps with the orthogonal projection of the first electrode 321 on the substrate 10, or overlaps with the orthogonal projection of the second electrode 322 on the substrate 10.
[0045] When the gate-source voltage of the transistor is greater than the threshold voltage, a conductive channel is formed in the active layer 33, allowing current to flow between the first electrode 321 and the second electrode 322, and the transistor is in the on state. When the gate voltage applied at the gate 31 is less than the threshold voltage, the conductive channel disappears, and the thin-film transistor is in the off state. When the voltage applied at the gate 31 continues to decrease, holes in the active layer 33 of the transistor move away from the gate 31 under the influence of the voltage, continuously accumulating to form a conductive path, resulting in leakage current.
[0046] The cutout portion 314 can reduce the area of the overlap between the orthogonal projection of the first electrode 321 and / or the second electrode 322 on the substrate 10 and the orthogonal projection of the gate 31 on the substrate 10. Since there is an electric field between the first electrode 321 and the second electrode 322 and the gate 31 in the vertical direction, when the gate voltage applied at the gate 31 is lower than the threshold voltage, the accumulation of holes in the active layer 33 can be reduced by reducing the area of this overlap region, thereby reducing the leakage current caused by the participation of holes in conduction.
[0047] In one embodiment, one of the first electrode 321 and the second electrode 322 is the source electrode and the other is the drain electrode.
[0048] In one embodiment, such as Figure 3 As shown, the gate 31 and the gate line GL are located on the same layer, and the first electrode 321, the second electrode 322 and the data line DL are located on the same layer.
[0049] In one embodiment, the length of the first gate 311 and the second gate 312 of the transistor ranges from 45 μm to 90 μm, and the width ranges from 3 μm to 6 μm. The length of the first gate 311 and the second gate 312 can be, for example, 50 μm, 60 μm, 70 μm, 80 μm, etc., and the width can be, for example, 3.5 μm, 4.5 μm, 5 μm, 5.5 μm, etc.
[0050] In one embodiment, such as Figure 2 As shown, the orthographic projection of the cutout portion 314 onto the substrate 10 falls entirely within the orthographic projection of the first electrode 321 and / or the second electrode 322 onto the substrate 10. This arrangement minimizes the overlap area between the first electrode 321 or the second electrode 322 and the gate 31 in the vertical direction, which helps reduce leakage current.
[0051] In one embodiment, in the width direction of the connection portion 313, the width of the cutout portion 314 is greater than half the width of the connection portion 313. This arrangement reduces the overlap area between the first electrode 321 or the second electrode 322 and the gate 31 in the vertical direction, which helps to reduce leakage current. Figure 2 In the illustrated embodiment, the width of the cutout portion 314 is three-fifths of the width of the connecting portion 313, and the cutout portion 314 is square. In other embodiments, the width and shape of the cutout portion 314 can be specifically set according to requirements.
[0052] In one embodiment, such as Figure 2As shown, the pixel electrode 20 includes a main body 21 and a protrusion 22 extending from at least one side of the main body. The orthographic projection of the protrusion 22 on the substrate 10 is located between the orthographic projection of the main body 21 on the substrate 10 and the orthographic projection of the gate line GL on the substrate 10. The width of the gate 31 is greater than the width of the gate line GL. By providing the protrusion 22, the space between the main body 21 and the gate line GL can be fully utilized, avoiding overlap between the orthographic projection of the pixel electrode 20 on the substrate 10 and the orthographic projection of the gate 31 on the substrate 10, while maximizing the area of the pixel electrode 20.
[0053] exist Figure 2 In the embodiment shown, the pixel electrode 20 includes a main body 21 and two protrusions 22 located on the upper and lower sides of the main body 21. The lower protrusion 22 is located between the main body 21 and the gate line GL, and the upper protrusion 22 is located between the main body 21 and the gate line adjacent to the pixel electrode 20.
[0054] In one embodiment, such as Figure 2 As shown, the distance 'a' between the orthographic projection of the main body 21 on the substrate 10 and the orthographic projection of the adjacent gate electrode 31 on the substrate 10 is in the range of 10μm to 15μm. For example, the distance range 'a' can be 11μm, 12.5μm, 13.5μm, etc. This arrangement avoids the main body 21 from covering the gate electrode 31 or affecting the gate electrode 31, thus avoiding problems such as top-gate effect or crosstalk between the pixel electrode 20 and the transistor 30. Figure 2 In the embodiment shown, the distance range a is 14 μm and the width of the protrusion 22 is 3 μm.
[0055] In one embodiment, such as Figure 3 As shown, a first insulating layer 41 is provided between the gate 31 and the active layer 33, and a second insulating layer 42 is provided between the pixel electrode 20 and the first electrode 321 and the second electrode 322.
[0056] In one embodiment, such as Figure 3 As shown, the display panel further includes a first auxiliary electrode 51 and a second auxiliary electrode 52. The first auxiliary electrode 51 is located between the substrate 10 and the first insulating layer 41, and the second auxiliary electrode 52 is located between the first insulating layer 41 and the second insulating layer 42. The first auxiliary electrode 51, the second auxiliary electrode 52, and the pixel electrode 20 have overlapping orthographic projections on the substrate 10.
[0057] The pixel electrode 20 is connected to the first auxiliary electrode 51 through a first via 61 passing through the first insulating layer 41 and the second insulating layer 42. The pixel electrode 20 is also connected to the first electrode 321 or the second electrode 322 through a second via 62 passing through the second insulating layer 42.
[0058] The first auxiliary electrode 51 and the second auxiliary electrode 52 can form a storage capacitor to maintain the stability of the voltage applied to the pixel electrode 20. The larger the capacitance value of the storage capacitor, the better the effect of maintaining the stability of the voltage applied to the pixel electrode 20.
[0059] In one embodiment, such as Figure 3 As shown, the second auxiliary electrode 52 can be reused as a common electrode in the pixel. In this way, the film thickness of the display panel can be reduced, which helps to achieve a thinner and lighter display panel.
[0060] In one embodiment, such as Figure 3 As shown, the first auxiliary electrode 51 is located on the same layer as the first gate electrode 311 and the second gate electrode 312, and the second auxiliary electrode 52 is located on the same layer as the first electrode 321 and the second electrode 322. This simplifies the manufacturing process of the display panel and reduces production costs.
[0061] In one embodiment, such as Figure 3 , Figure 4 and Figure 5 As shown, the display panel includes a display area AA and a bonding area BA surrounding the display area AA, with the pixel area located within the display area AA. The bonding area BA includes a plurality of connection terminals 70 and an insulating layer 40 located on the side of the connection terminals 70 away from the substrate 10. The insulating layer 40 has a plurality of openings 80, each opening 80 including a portion of the surface of one of the connection terminals 70, and at least one opening 80 corresponding to one of the connection terminals 70 is an elongated opening.
[0062] The connecting terminals 70 can be bonded using ACF (Anisotropic Conductive Film). ACF contains conductive particles. When pressure is applied to these particles, they aggregate within the opening 80. When the opening 80 is small, the force applied directly to the conductive particles is small, thus affecting the rupture state of the insulating film on the surface of the conductive particles. When the opening 80 is elongated, the force on the conductive particles can be increased, improving the rupture state of the insulating film and enhancing the electrical connection performance of the bonding area BA.
[0063] In one embodiment, such as Figure 4 and Figure 5As shown, the bonding area BA also includes a conductive layer 90, which is located on the side of the insulating layer 40 away from the substrate 10. Part of the conductive layer 90 is located inside the opening 80 and is in contact with the connection terminal 70.
[0064] In one embodiment, such as Figure 4 and Figure 5 As shown, the connection terminal 70 includes a gate connection terminal 71, which is located between the first insulating layer 41 and the substrate 10. An opening 80 passes through both the first insulating layer 41 and the second insulating layer 42, exposing a portion of the upper surface of the gate connection terminal 71. In another embodiment, as... Figure 6 and Figure 7 As shown, the connection terminal 70 includes a source-drain connection terminal 72, which is located between the first insulating layer 41 and the second insulating layer 42. After the opening 80 passes through the second insulating layer 42, it exposes part of the upper surface of the source-drain connection terminal 72.
[0065] In one embodiment, such as Figure 4 and Figure 6 As shown, the extension direction of the elongated opening 80 is parallel to the length direction of the corresponding connecting terminal 70. The connecting terminal 70 is relatively long, and this arrangement provides sufficient extension space for the opening 80, increasing its area.
[0066] In one embodiment, such as Figure 6 As shown, a connecting terminal 70 is opposite to three elongated openings 80. When the bonding connection of one of the openings 80 fails, the remaining openings 80 can still function as a connector. In another embodiment, as... Figure 8 As shown, at least one of the connection terminals 70 is opposite only one opening 80, and the opening 80 is an elongated opening. This maximizes the area of the elongated opening 80, allowing the insulating film of the conductive particles to have a better breakage state.
[0067] This application also provides a display device, which includes the display panel described above.
[0068] In one embodiment, the display device further includes a housing, and the display panel is disposed within the housing.
[0069] This application does not impose specific limitations on the application of display devices, which can be any product or component with display function, such as televisions, laptops, tablets, wearable display devices, mobile phones, in-vehicle displays, navigation systems, e-books, electronic price tags, digital photo frames, and advertising light boxes.
[0070] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A display panel, characterized in that, The display panel includes: Substrate; Multiple gate lines are disposed on one side of the substrate and extend along a first direction; Multiple data lines are disposed on one side of the substrate and extend along a second direction; the first direction intersects the second direction; the gate lines and the data lines form multiple pixel areas; Multiple pixel electrodes, each of the pixel electrodes being located in one of the pixel regions; Multiple transistors, including gates, each gate being connected to a gate line, and the length direction of the gate being the same as the first direction; the orthographic projection of the gate on the substrate and the orthographic projection of the gate line on the substrate do not overlap with the orthographic projection of the pixel electrode on the substrate.
2. The display panel according to claim 1, characterized in that, Each transistor has a gate including a first gate and a second gate; each transistor also includes a connection portion, through which the first gate and the second gate are connected; the first gate, the connection portion and the second gate are arranged along the length direction of the gate line to which they are connected.
3. The display panel according to claim 2, characterized in that, The connecting portion has a hollow portion; the transistor also includes a first electrode and a second electrode, and the orthographic projection of the hollow portion on the substrate overlaps with the orthographic projection of the first electrode and / or the second electrode on the substrate.
4. The display panel according to claim 3, characterized in that, The orthographic projection of the hollow portion on the substrate falls entirely within the orthographic projection of the first electrode and / or the second electrode on the substrate.
5. The display panel according to claim 3, characterized in that, In the width direction of the connecting portion, the width of the hollow portion is greater than half the width of the connecting portion.
6. The display panel according to claim 1, characterized in that, The pixel electrode includes a main body portion and a protrusion extending from at least one side of the main body portion, wherein the orthographic projection of the protrusion on the substrate is located between the orthographic projection of the main body portion on the substrate and the orthographic projection of the gate line on the substrate.
7. The display panel according to claim 6, characterized in that, In a direction perpendicular to the length direction of the gate line, the width of the gate line is smaller than the width of the gate; the orthographic projection of the protrusion on the substrate is opposite to the orthographic projection of the adjacent gate line on the substrate.
8. The display panel according to claim 6, characterized in that, The distance between the orthographic projection of the main body on the substrate and the orthographic projection of the adjacent gate on the substrate is in the range of 10 μm to 15 μm.
9. The display panel according to claim 1, characterized in that, The display panel includes a display area and a bonding area surrounding the display area; the pixel area is located in the display area; the bonding area includes a plurality of connection terminals and an insulating layer located on the side of the connection terminals away from the substrate, the insulating layer having a plurality of openings, each opening including a portion of the surface of one of the connection terminals; at least one opening corresponding to at least one of the connection terminals is an elongated opening.
10. The display panel according to claim 9, characterized in that, The elongated opening extends in a direction parallel to the length direction of the corresponding connecting terminal.
11. The display panel according to claim 10, characterized in that, At least one of the connection terminals is opposite only one opening, and the opening is an elongated opening.
12. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.