Band-gap reference voltage circuit without operational amplifier

Abstract

The utility model discloses a band-gap reference voltage circuit without an operational amplifier, which solves the problems that the structure and operation of the band-gap reference voltage circuit without the operational amplifier in the prior art are complicated, and the PSRR performance of output voltage in a high-frequency band is poor, and comprises a band-gap reference core circuit and a cascode current mirror circuit which are connected with each other, the band-gap reference core circuit and the cascode current mirror circuit are jointly connected with a starting circuit, and the band-gap reference core circuit is further connected with a driving circuit. According to the utility model, the circuit structure and the operation complexity are simplified, the parameters of each component do not need to be repeatedly adjusted, and the excellent PSRR performance of the output voltage in a high frequency band is realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit technical field, specifically provide a kind of without operational amplifier band gap reference voltage circuit. BACKGROUND

[0002] Reference voltage is one of basic analog unit circuits in integrated circuit design, which can provide voltage that does not change with temperature and power supply voltage for other modules of the system. The voltage clamping of the traditional band gap reference circuit is realized through the operational amplifier loop, and the offset voltage of the operational amplifier will affect the accuracy of the reference voltage. In addition, the operational amplifier will introduce certain power consumption, which is not conducive to low-power design.

[0003] The existing operational amplifier-free band gap reference voltage circuit, for example, a "high-low voltage conversion circuit with low temperature coefficient and high power supply rejection ratio" disclosed in Chinese patent documents, with publication number CN113934250A, includes an operational amplifier-free band gap reference circuit and a high-to-low voltage conversion circuit connected together. Under the condition that the parameters of the components are properly selected, the temperature drift effect of the circuit can be significantly reduced, and the working stability of the integrated circuit in high-temperature and low-temperature environments can be improved. However, the output voltage of the circuit has poor PSRR performance in the high-frequency band, and the circuit needs to be set with multiple bias current sources to realize high-to-low voltage conversion. The circuit structure is complex, and the parameters of each component need to be adjusted again under different working conditions, which increases the operation complexity. UTILITY MODEL CONTENT

[0004] To solve the problems of complex structure and operation of the operational amplifier-free band gap reference voltage circuit in the prior art, and poor PSRR performance of the output voltage in the high-frequency band, the utility model provides an operational amplifier-free band gap reference voltage circuit, which simplifies the circuit structure and operation complexity and realizes excellent PSRR performance of the output voltage in the high-frequency band.

[0005] The specific scheme of the utility model is as follows.

[0006] An operational amplifier-free band gap reference voltage circuit includes a band gap reference core circuit and a common-source common-gate current mirror circuit connected together, and the band gap reference core circuit and the common-source common-gate current mirror circuit are commonly connected with a start-up circuit. The band gap reference core circuit is also connected with a driving circuit.

[0007] The band gap reference core circuit has two degenerate points. When the power supply is powered on, there may be a situation where the internal current of the circuit is zero, which causes the band gap reference core circuit to fail to work normally. The start-up circuit can ensure that the band gap reference core circuit escapes from the degenerate point when the power supply is powered on and establishes a normal reference voltage.

[0008] Furthermore, the bandgap reference core circuit includes a first NMOS transistor M1 and a second NMOS transistor M2, as well as a first NPN transistor Q1 and a second NPN transistor Q2; the gate and drain of the first NMOS transistor M1 are electrically connected to the gate of the second NMOS transistor M2, and the source is electrically connected to the collector of the second NPN transistor Q2; the source of the second NMOS transistor M2 is electrically connected to the collector of the first NPN transistor Q1; the base of the first NPN transistor Q1 is connected to the first end of a fifth resistor R5, and the second end of the fifth resistor R5 is electrically connected to the base of the second NPN transistor Q2.

[0009] Furthermore, the reference voltage output terminal of the bandgap reference core circuit is also connected to an RC low-pass filter, which includes a capacitor C and a sixth resistor R6. The first terminal of the capacitor C is electrically connected to the first terminal of the sixth resistor R6, and is also electrically connected to the base of the second NPN transistor Q2 and the second terminal of the fifth resistor R5, respectively. The second terminal of the capacitor C is electrically connected to the second terminal of the sixth resistor R6, and both are grounded. Adding an RC low-pass filter to the reference voltage output terminal can ensure the PSRR performance of the output voltage at high frequencies. The zero introduced by the RC low-pass filter can effectively achieve excellent PSRR performance in the high-frequency band.

[0010] Furthermore, the bandgap reference core circuit also includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is electrically connected to the emitter of the first NPN transistor Q1, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0011] The first NPN transistor Q1 and the first resistor R1 generate a PTAT current, which is then converted into a PTAT voltage through the second resistor R2. The PTAT voltage and the voltage between the base and emitter of the first NPN transistor Q1 and the second NPN transistor Q2 are weighted and superimposed to obtain a reference voltage at the base of the first NPN transistor Q1 and the second NPN transistor Q2.

[0012] Furthermore, the first NPN transistor Q1 and the second NPN transistor Q2 have different areas. By using first NPN transistor Q1 and second NPN transistor Q2 with different areas, it is possible to ensure that first NPN transistor Q1 and second NPN transistor Q2 operate at different current densities, thereby obtaining a voltage difference with a positive temperature coefficient, where the temperature coefficient is a function related to temperature.

[0013] Furthermore, the common-source common-gate current mirror circuit includes a first PMOS transistor M3, a second PMOS transistor M4, a third PMOS transistor M5, and a fourth PMOS transistor M6. The gates of the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 are electrically connected one by one. The source of the first PMOS transistor M3 is electrically connected to the drain of the third PMOS transistor M5; the source of the second PMOS transistor M4 is electrically connected to the drain of the fourth PMOS transistor M6; and the source of the third PMOS transistor M5 is electrically connected to the source of the fourth PMOS transistor M6, and they are all connected to a common power supply.

[0014] Furthermore, the drain of the first PMOS transistor M3 is electrically connected to the drain of the second NMOS transistor M2 and the gate of the first PMOS transistor M3, respectively; the drain of the second PMOS transistor M4 is electrically connected to the drain of the first NMOS transistor M1. That is, the drain of the first PMOS transistor M3 is also electrically connected to the gates of the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6, respectively.

[0015] The common-source cascode current mirror circuit is a self-biased current mirror circuit, ensuring that the two current mirrors of the core bandgap reference circuit are equal. By employing the common-source cascode current mirror circuit, the PSRR characteristics of the bandgap reference output voltage are improved at low and medium frequencies while ensuring that the circuit noise performance does not deteriorate. This achieves a high power supply rejection ratio while realizing an op-amp-free bandgap reference voltage circuit.

[0016] Furthermore, the startup circuit includes a third NPN transistor Q3 and a fourth NPN transistor Q4, as well as a sixth PMOS transistor M8 and a seventh PMOS transistor M9; the base of the third NPN transistor Q3 is electrically connected to the collector of the third NPN transistor Q3 and the base of the fourth NPN transistor Q4, respectively; the emitter of the fourth NPN transistor Q4 is electrically connected between the emitter of the first NPN transistor Q1 and the first terminal of the first resistor R1; the gate of the sixth PMOS transistor M8 is electrically connected to the drain of the sixth PMOS transistor M8, the gate of the seventh PMOS transistor M9, and the collector of the fourth NPN transistor Q4, respectively; the source of the sixth PMOS transistor M8 is electrically connected to the source of the seventh PMOS transistor M9, and they are all connected to a power supply.

[0017] Furthermore, the startup circuit also includes a third resistor R3 and a fourth resistor R4. The first end of the third resistor R3 is electrically connected to the emitter of the third NPN transistor Q3, and the second end is grounded. The first end of the fourth resistor R4 is electrically connected to the collector and base of the third NPN transistor Q3 and the base of the fourth NPN transistor Q4, respectively, and the second end is electrically connected to the source of the fourth PMOS transistor M6 and the source of the third PMOS transistor M5, respectively. The drain of the seventh PMOS transistor M9 is electrically connected to the gate of the first NMOS transistor M1.

[0018] When the circuit is at the zero-state junction point, the third NPN transistor Q3 and the third resistor R3 generate current, which is injected into the emitter of the first NPN transistor Q1 in the bandgap reference core circuit through the fourth NPN transistor Q4. The sixth PMOS transistor M8 and the seventh PMOS transistor M9 in the startup circuit inject startup current into the drain of the first NMOS transistor M1. When the reference voltage is established normally, the fourth NPN transistor Q4 is turned off, and the startup circuit is turned off.

[0019] In the startup circuit, the sixth PMOS transistor M8 and the seventh PMOS transistor M9 inject startup current into the drain of the first NMOS transistor M1, ensuring that the circuit can get away from the zero-parallel point and that the self-bias circuit is established normally, so that the current flowing through the first NPN transistor Q1 and the second NPN transistor Q2 in the bandgap reference core circuit is equal.

[0020] Furthermore, the driving circuit includes a third NMOS transistor M7, the gate of which is electrically connected to the drain of the first NMOS transistor M1, the source of which is the reference voltage output terminal and electrically connected to the base of the second NPN transistor Q2, and the drain of which is electrically connected to the source of the fourth PMOS transistor M6.

[0021] The third NMOS transistor M7, the first NMOS transistor M1, and the second NPN transistor Q2 together form a negative feedback loop, enabling the op-amp-free bandgap reference voltage circuit to have driving capability. The third NMOS transistor M7 serves as the driving transistor, and its size depends on the current required by the subsequent circuit.

[0022] Therefore, this utility model has the following beneficial effects:

[0023] (1) Combining the bandgap reference core circuit and the common source cascode current mirror circuit reduces power consumption and simplifies the circuit structure and operation complexity, eliminating the need to repeatedly adjust the parameters of each component.

[0024] (2) The driving capability of the op-amp-free bandgap reference voltage circuit is improved by the driving circuit;

[0025] (3) The start-up circuit ensures that the core bandgap reference circuit gets rid of the degeneracy point and establishes the reference voltage normally when the power supply is turned on; (4) An RC low-pass filter is added to the output terminal of the reference voltage, and the zero point introduced by it can effectively realize the excellent PSRR performance of the output voltage in the high frequency band. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0027] Figure 1 This is a circuit diagram of an op-amp-free bandgap reference voltage circuit according to the present invention.

[0028] Figure 2 This is a structural block diagram of an op-amp-free bandgap reference voltage circuit according to the present invention. Detailed Implementation

[0029] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0030] Reference voltage is one of the fundamental analog unit circuits in integrated circuit design. It provides a voltage to other modules of the system that remains constant regardless of temperature or power supply voltage. Because the manufacturing process of a chip can vary due to factors like process technology, power supply, and temperature, the final chip will differ, affecting product specifications. A chip that is as close to ideal as possible is better; therefore, a reference voltage source capable of withstanding these undesirable environments is essential. This is especially true for analog circuit design, where a stable reference potential generated by the chip itself is necessary when an external voltage source is unavailable. Therefore, most modern analog chips incorporate a bandgap reference circuit, typically composed of NPN or PNP transistors, operational amplifiers, and resistors.

[0031] like Figure 1 The diagram shown is a circuit schematic of an op-amp-free bandgap reference voltage circuit according to this invention. Figure 2The diagram shown is a structural block diagram of an op-amp-free bandgap reference voltage circuit according to this invention. The high PSRR op-amp-free bandgap reference voltage circuit consists of a startup circuit, a common-source cascode current mirror circuit, a bandgap reference core circuit, and a drive circuit. The startup circuit is connected to both the common-source cascode current mirror circuit and the bandgap reference core circuit. The common-source cascode current mirror circuit and the bandgap reference core circuit are electrically connected. The bandgap reference core circuit is connected to the drive circuit.

[0032] The core circuit of the bandgap reference includes two NMOS transistors, namely a first NMOS transistor M1 and a second NMOS transistor M2. The gate of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2, and the drain of the first NMOS transistor M1 is connected to its gate. The core circuit also includes two NPN bipolar transistors, namely a first NPN transistor Q1 and a second NPN transistor Q2. The source of the first NMOS transistor M1 is connected to the collector of the second NPN transistor Q2, and the source of the second NMOS transistor M2 is connected to the collector of the first NPN transistor Q1. The base of the first NPN transistor Q1 is electrically connected to the first terminal of a fifth resistor R5, and the base of the second NPN transistor Q2 is electrically connected to the second terminal of the fifth resistor R5. The emitter of the first NPN transistor Q1 is connected to the first resistor R1 and the second resistor R2 in sequence and then grounded. The emitter of the second NPN transistor Q2 is connected to the second resistor R2 and then grounded; that is, the emitter of the second NPN transistor Q2 is connected between the first resistor R1 and the second resistor R2.

[0033] Whether it's a bandgap reference circuit primarily composed of PNP or NPN transistors, its temperature-independent characteristics are achieved through the transistor's V... BE The negative temperature characteristic of the bandgap reference circuit, combined with the positive temperature coefficient of the voltage difference between the base and emitter, allows for the creation of a reference potential with a zero-temperature curve by combining two sets of transistors. Typically, voltage clamping in a bandgap reference circuit is achieved through an operational amplifier loop, but the offset voltage of the operational amplifier can affect the accuracy of the reference voltage. Furthermore, operational amplifiers introduce power consumption, which is detrimental to low-power designs.

[0034] In this embodiment, the PTAT current is realized through the first NPN transistor Q1 and the first resistor R1, and converted into the PTAT voltage through the second resistor R2. The PTAT voltage is related to the NPN bipolar transistor V. BE Weighted superposition is performed to obtain a reference voltage at the base of the bipolar transistor, where is the voltage between the base and emitter of the NPN bipolar transistor. By using a first NPN transistor Q1 and a second NPN transistor Q2 with different areas, it is ensured that the first NPN transistor Q1 and the second NPN transistor Q2 operate at different current densities, thereby obtaining the positive temperature coefficient ΔV. BEThe area of ​​the NPN transistor refers to its effective cross-sectional area. Circuit performance can be optimized by adjusting the areas of the first NPN transistor Q1 and the second NPN transistor Q2. The bandgap reference output voltage formula in this embodiment is: V BG =V BE2 +2V T lnn(R2 / R1).

[0035] V BE The temperature coefficient is a function related to temperature; at room temperature, V BE ≈750mV. Considering layout matching and post-circuit simulation performance optimization, taking n=8, the theoretical value of R2 / R1 is approximately 8, V. BG The expected value is approximately 1.2V.

[0036] The reference voltage output terminal of the bandgap reference core circuit is also connected to an RC low-pass filter. The RC low-pass filter includes a parallel capacitor C and a sixth resistor R6. One end of the RC low-pass filter is grounded, and the other end is connected to the base of the second NPN transistor Q2. The zero introduced by the RC low-pass filter can effectively achieve excellent PSRR performance of the op-amp-free bandgap reference voltage circuit in the high-frequency band.

[0037] The core circuit of the bandgap reference generates a reference voltage that is largely independent of temperature and power supply voltage changes. By utilizing the positive temperature coefficient of the voltage between the base and emitter of the bipolar transistor and the difference under different current densities, combined with a resistor network, a reference voltage output with zero temperature coefficient is achieved, providing a stable reference voltage for the entire circuit.

[0038] The common-source cascode current mirror circuit is a self-biased current mirror circuit, which includes four PMOS transistors: the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6. The drain of the first PMOS transistor M3 is connected to the drain of the second NMOS transistor M2, and the drain of the second PMOS transistor M4 is connected to the drain of the first NMOS transistor M1. That is, the drain of the second PMOS transistor M4 is connected to the gate of the first NMOS transistor M1, and the gates of the first PMOS transistor M3 and the second PMOS transistor M4 are connected. The drain of the third PMOS transistor M5 is connected to the source of the first PMOS transistor M3, and the drain of the fourth PMOS transistor M6 is connected to the source of the second PMOS transistor M4. The gates of the third PMOS transistor M5 and the fourth PMOS transistor M6 are connected, and the sources of the third PMOS transistor M5 and the fourth PMOS transistor M6 are connected. The gate of the third PMOS transistor M5 is also connected to the drain of the first PMOS transistor M3, that is, the gate of the third PMOS transistor M5 is also connected to the drain of the second NMOS transistor M2. Furthermore, the sources of the third PMOS transistor M5 and the fourth PMOS transistor M6 are connected to the same power supply. The gates of the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 are electrically connected one by one. The common-source cascode current mirroring and the mirrored reference current improve the accuracy and stability of current replication, providing a stable bias current for the core bandgap reference circuit.

[0039] By employing a common-source cascode current mirror circuit, the two current mirrors of the core bandgap reference circuit are made equal. At low and medium frequencies, the PSRR characteristics of the bandgap reference output voltage are improved while ensuring that the circuit noise performance is not degraded. This achieves a high power supply rejection ratio and realizes an op-amp-free bandgap reference voltage circuit.

[0040] The core circuit of the bandgap reference has two degeneracy points. When the power is turned on, there may be a situation where the internal current of the circuit is zero, which will cause the core circuit of the bandgap reference to fail to work properly. By setting up a startup circuit, it can be ensured that the core circuit of the bandgap reference gets rid of the degeneracy point when the power is turned on and establishes the reference voltage normally.

[0041] The startup circuit consists of two PMOS transistors, two NPN bipolar transistors, and two resistors. The two PMOS transistors are the sixth PMOS transistor M8 and the seventh PMOS transistor M9. The two NPN bipolar transistors are the third NPN transistor Q3 and the fourth NPN transistor Q4. The two resistors are the third resistor R3 and the fourth resistor R4. The gate of the sixth PMOS transistor M8 is connected to the gate of the seventh PMOS transistor M9, and the gate of the sixth PMOS transistor M8 is also connected to its drain. The source of the sixth PMOS transistor M8 is connected to the source of the seventh PMOS transistor M9, and both sources are connected to the same power supply. The drain of the seventh PMOS transistor M9 is electrically connected to the drain of the first NMOS transistor M1. The node voltage of the drain of the seventh PMOS transistor M9 and the node voltage of the drain of the first NMOS transistor M1 are both VA.

[0042] The drain of the sixth PMOS transistor M8 is connected to the collector of the fourth NPN transistor Q4, meaning the collector of the fourth NPN transistor Q4 is connected to the gates of both the sixth PMOS transistors M8 and M9. The base of the fourth NPN transistor Q4 is connected to the base of the third NPN transistor Q3, and the base of the third NPN transistor Q3 is also connected to its collector. The emitter of the fourth NPN transistor Q4 is connected between the first NPN transistor Q1 and the first resistor R1, meaning the emitter of the fourth NPN transistor Q4 is connected to the emitter of the first NPN transistor Q1. The emitter of the third NPN transistor Q3 is connected to ground via the third resistor R3, and its collector is connected to the power supply via the fourth resistor R4, meaning the collector of the third NPN transistor Q3 is connected to the source of both the third PMOS transistor M5 and the fourth PMOS transistor M6 through the fourth resistor R4. This startup circuit prevents the circuit from falling into a degenerate bias point (where all branch currents are zero) when the power is applied, ensuring the circuit can start normally and recover from this abnormal operating state.

[0043] When the bandgap reference core circuit is at the zero-state junction point, the third NPN transistor Q3 and the third resistor R3 generate current, which is injected into the emitter of the first NPN transistor Q1 in the bandgap reference core circuit through the fourth NPN transistor Q4. In the startup circuit, the sixth PMOS transistor M8 and the seventh PMOS transistor M9 inject startup current into the drain of the first NMOS transistor M1. When the reference voltage is established normally, the fourth NPN transistor Q4 turns off, and the startup circuit is turned off. The startup current injected by the sixth PMOS transistor M8 and the seventh PMOS transistor M9 into the drain of the first NMOS transistor M1 ensures that the circuit can move away from the zero-state junction point and ensures that the self-biasing circuit is established normally, achieving equal current flowing through the first NPN transistor Q1 and the second NPN transistor Q2 in the bandgap reference core circuit.

[0044] The driving circuit includes a third NMOS transistor M7. The gate of the third NMOS transistor M7 is connected to the drain of the first NMOS transistor M1 and the drain of the second PMOS transistor M4. The drain of the third NMOS transistor M7 is connected to the source of the fourth PMOS transistor M6 and the source of the third PMOS transistor M5, as well as a fourth resistor R4. In other words, the drain of the third NMOS transistor M7 is connected to the power supply, and the source of the third NMOS transistor M7 is the reference voltage output terminal, connected to the base of the second NPN transistor Q2. Thus, the source of the third NMOS transistor M7 is connected to an RC low-pass filter. The third NMOS transistor M7, the first NMOS transistor M1, and the second NPN transistor Q2 form a negative feedback loop, enabling the op-amp-less bandgap reference voltage circuit to have driving capability. The size of the third NMOS transistor M7, as the driving transistor, depends on the current required by the subsequent circuit. The driving circuit provides sufficient driving capability for the op-amp-less bandgap reference voltage circuit, ensuring that the signal can be effectively transmitted to the next stage circuit, guaranteeing the normal operation and stable performance of the circuit.

[0045] The operation of an op-amp-free bandgap reference voltage circuit in this embodiment is as follows. First, during the startup phase, the startup circuit operates when the power supply is turned on, generating an initial current or voltage to break the degenerate bias point of the bandgap reference core circuit, allowing the circuit to begin normal operation. The current generated by the startup circuit is replicated and mirrored through a common-source cascode current mirror circuit to generate a stable bias current, which is then supplied to the bandgap reference core circuit. The bandgap reference core circuit utilizes the base-emitter voltage (V0) of a bipolar junction transistor (BJT). BE The negative temperature coefficient characteristic of BJTs, and the V of two BJTs operating at different current densities. BE The difference has a positive temperature coefficient characteristic. A resistor network converts this positive temperature coefficient current into a voltage, and then compares it with V. BE The negative temperature coefficient voltages are added together to achieve temperature compensation, resulting in a zero temperature coefficient reference voltage. The drive circuit ensures that the reference voltage signal can be stably transmitted to the output terminal, providing sufficient drive capability so that the output voltage remains stable regardless of load changes. Through the above process, the op-amp-less bandgap reference voltage circuit can provide a stable and accurate reference voltage under various operating conditions and is widely used in analog and mixed-signal integrated circuits.

[0046] Traditional bandgap reference circuits can largely solve the problem of reference voltage changes due to temperature variations. However, the impact of op-amp offset voltage on the output voltage is also a key concern. Due to the traditional architecture, the clamping op-amp offset voltage is relatively large, which can affect the reference voltage signal and even cause malfunctions in downstream circuits when the system has high requirements for reference voltage accuracy. Considering the above-mentioned undesirable factors, we propose a stable and easily modified op-amp-free bandgap reference circuit. While achieving clamping of the core reference circuit, it eliminates the error introduced by the op-amp offset voltage and solves the problem of unstable reference potential in the chip.

[0047] Existing op-amp-less bandgap reference voltage circuits have poor PSRR performance in the high-frequency band, focusing only on improving the PSRR characteristics of the bandgap reference output voltage at low and medium frequencies. Furthermore, this circuit requires multiple bias current sources to achieve high-voltage to low-voltage conversion, resulting in a complex circuit structure. The parameters of each component need to be readjusted under different operating conditions, which increases the operational complexity.

[0048] This embodiment combines the bandgap reference core circuit and the common-source cascode current mirror circuit, reducing power consumption and simplifying the circuit structure and operation complexity, eliminating the need for repeated adjustments to component parameters; the driving circuit improves the driving capability of the op-amp-less bandgap reference voltage circuit; the startup circuit ensures that the bandgap reference core circuit overcomes the degeneracy point and establishes the reference voltage normally when the power supply is turned on; and an RC low-pass filter is added to the reference voltage output terminal, whose introduced zero point can effectively achieve excellent PSRR performance of the output voltage in the high-frequency band.

[0049] This embodiment of an op-amp-less bandgap reference voltage circuit provides a high-precision reference voltage, is minimally affected by temperature and power supply voltage variations, ensuring circuit stability and reliability. It eliminates the need for an operational amplifier, reducing circuit complexity and power consumption, making it suitable for applications with high power consumption requirements. It exhibits strong power supply voltage suppression capabilities, operating normally over a wide power supply voltage range. It also features fast response characteristics, rapidly adjusting the output voltage to adapt to dynamically changing input signals. Furthermore, it reduces the number of components, lowering circuit cost and chip area, which is beneficial for optimized integrated circuit design. These advantages make this op-amp-less bandgap reference voltage circuit of significant value in applications such as analog integrated circuits, sensor interfaces, and data converters.

[0050] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the present utility model. Any simple modifications, alterations, or equivalent structural transformations made to the above embodiments based on the technical essence of the present utility model shall still fall within the protection scope of the present utility model.

Claims

1. An op-amp-free bandgap reference voltage circuit, characterized in that, It includes a bandgap reference core circuit and a common-source cascode current mirror circuit connected together. The bandgap reference core circuit and the common-source cascode current mirror circuit are jointly connected to a startup circuit. The bandgap reference core circuit is also connected to a drive circuit.

2. The op-amp-free bandgap reference voltage circuit according to claim 1, characterized in that, The bandgap reference core circuit includes a first NMOS transistor M1 and a second NMOS transistor M2, as well as a first NPN transistor Q1 and a second NPN transistor Q2. The gate and drain of the first NMOS transistor M1 are electrically connected to the gate of the second NMOS transistor M2, and the source is electrically connected to the collector of the second NPN transistor Q2. The source of the second NMOS transistor M2 is electrically connected to the collector of the first NPN transistor Q1. The base of the first NPN transistor Q1 is connected to the first terminal of a fifth resistor R5, and the second terminal of the fifth resistor R5 is electrically connected to the base of the second NPN transistor Q2.

3. The op-amp-free bandgap reference voltage circuit according to claim 2, characterized in that, The reference voltage output terminal of the bandgap reference core circuit is also connected to an RC low-pass filter, which includes a capacitor C and a sixth resistor R6. The first terminal of the capacitor C is electrically connected to the first terminal of the sixth resistor R6, and is also electrically connected to the base of the second NPN transistor Q2 and the second terminal of the fifth resistor R5, respectively. The second terminal of the capacitor C is electrically connected to the second terminal of the sixth resistor R6, and they are both grounded.

4. The op-amp-free bandgap reference voltage circuit according to claim 3, characterized in that, The bandgap reference core circuit also includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is electrically connected to the emitter of the first NPN transistor Q1, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

5. A bandgap-free op-amp reference voltage circuit according to claim 2, 3, or 4, characterized in that, The first NPN transistor Q1 and the second NPN transistor Q2 have different areas.

6. The op-amp-free bandgap reference voltage circuit according to claim 4, characterized in that, The common-source common-gate current mirror circuit includes a first PMOS transistor M3, a second PMOS transistor M4, a third PMOS transistor M5, and a fourth PMOS transistor M6. The gates of the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 are electrically connected one by one. The source of the first PMOS transistor M3 is electrically connected to the drain of the third PMOS transistor M5; the source of the second PMOS transistor M4 is electrically connected to the drain of the fourth PMOS transistor M6; and the source of the third PMOS transistor M5 is electrically connected to the source of the fourth PMOS transistor M6, and they are all connected to a common power supply.

7. The op-amp-free bandgap reference voltage circuit according to claim 6, characterized in that, The drain of the first PMOS transistor M3 is electrically connected to the drain of the second NMOS transistor M2 and the gate of the first PMOS transistor M3, respectively; the drain of the second PMOS transistor M4 is electrically connected to the drain of the first NMOS transistor M1.

8. A bandgap-free op-amp reference voltage circuit according to claim 6 or 7, characterized in that, The startup circuit includes a third NPN transistor Q3, a fourth NPN transistor Q4, a sixth PMOS transistor M8, and a seventh PMOS transistor M9. The base of the third NPN transistor Q3 is electrically connected to the collector of the third NPN transistor Q3 and the base of the fourth NPN transistor Q4, respectively. The emitter of the fourth NPN transistor Q4 is electrically connected between the emitter of the first NPN transistor Q1 and the first terminal of the first resistor R1. The gate of the sixth PMOS transistor M8 is electrically connected to the drain of the sixth PMOS transistor M8, the gate of the seventh PMOS transistor M9, and the collector of the fourth NPN transistor Q4, respectively. The source of the sixth PMOS transistor M8 is electrically connected to the source of the seventh PMOS transistor M9 and they are all connected to the power supply.

9. The op-amp-free bandgap reference voltage circuit according to claim 8, characterized in that, The startup circuit further includes a third resistor R3 and a fourth resistor R4. The first end of the third resistor R3 is electrically connected to the emitter of the third NPN transistor Q3, and the second end is grounded. The first end of the fourth resistor R4 is electrically connected to the collector and base of the third NPN transistor Q3 and the base of the fourth NPN transistor Q4, respectively, and the second end is electrically connected to the source of the fourth PMOS transistor M6 and the source of the third PMOS transistor M5, respectively. The drain of the seventh PMOS transistor M9 is electrically connected to the gate of the first NMOS transistor M1.

10. A bandgap-free op-amp reference voltage circuit according to claim 6 or 7, characterized in that, The driving circuit includes a third NMOS transistor M7, whose gate is electrically connected to the drain of the first NMOS transistor M1, whose source is the reference voltage output terminal and electrically connected to the base of the second NPN transistor Q2, and whose drain is electrically connected to the source of the fourth PMOS transistor M6.

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