High-order temperature compensation band-gap reference circuit

Abstract

The utility model discloses a high-order temperature compensation band-gap reference circuit which comprises a biasing circuit, a compensation current generating circuit, a starting circuit and a band-gap reference core circuit. The biasing circuit, the compensation current generating circuit, the starting circuit and the band-gap reference core circuit are sequentially connected. The bias circuit is used for generating bias current with a positive temperature coefficient; the compensation current generation circuit is used for generating current with a high-order temperature coefficient; the starting circuit is used for controlling the starting of the band-gap reference core circuit according to the bias current generated by the bias circuit; and the band-gap reference core circuit is used for compensating reference voltage by the current with the high-order temperature coefficient to generate reference voltage with a low temperature coefficient. The output reference voltage VBG has the advantage of low temperature drift in a wide temperature range, and is suitable for a power supply management chip, a digital-to-analog conversion circuit and the like.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor integrated circuits, and in particular relates to a high-order temperature-compensated bandgap reference circuit. Background Technology

[0002] In power management chips such as switching power supplies and low-dropout linear regulators, the accuracy and temperature coefficient of the reference power supply are crucial factors affecting voltage output accuracy. As power management chips become increasingly digitized, the performance requirements for reference circuits are also rising. Utility Model Content

[0003] This invention designs a high-order temperature-compensated bandgap reference circuit, which can generate a low-temperature drift reference voltage V. BG The bias circuit generates a positive temperature coefficient current; the startup circuit ensures the bandgap reference core circuit escapes degeneracy and starts normally; the compensation current generation circuit outputs a high-order temperature coefficient current to perform high-order compensation on the reference potential. The reference voltage V output by this invention... BG It has the advantage of low temperature drift over a wide temperature range and is suitable for power management chips, digital-to-analog conversion circuits, etc.

[0004] To achieve the above objectives, this utility model provides a bias circuit, a compensation current generating circuit, a startup circuit, and a bandgap reference core circuit connected in sequence.

[0005] The bias circuit is used to generate a bias current with a positive temperature coefficient.

[0006] The compensation current generating circuit is used to generate a current with a high-order temperature coefficient, and obtain the mirror current through a current mirror.

[0007] The startup circuit is used to control the startup of the bandgap reference core circuit according to the bias current generated by the bias circuit.

[0008] The bandgap reference core circuit is used to compensate the reference voltage with the current having a high temperature coefficient, thereby generating a reference voltage with a low temperature coefficient.

[0009] Optionally, the bias circuit includes PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, NMOS transistors N1, N2, NPN BJT transistors Q1, Q2, Q3, and resistors R1, R2, R3.

[0010] In this configuration, the sources of P1, P5, P6, P7, and P8 are all connected to the power supply VDD; the gates of P1, P5, P6, P2, P3, and P4 are connected; the drain of P4 is connected to the first terminal of R1; the drain of P5 is connected to the collector of Q1; the base of Q1 and the base of Q2 are connected; the first terminal of R2, the emitter of Q3, and the drain of P8 are connected; the drain of N1, the drain of P6, the gate of N1, and the gate of N2 are connected; the emitter of N1, the base of Q3, and the collector of Q2 are connected; the gates of P7, P8, and P7, and the drain of N2 are connected; the source of N2 and the collector of Q3 are connected; and the second terminals of R1, R2, and R3 are all connected to the ground GND.

[0011] Optionally, the compensation current generating circuit includes: an operational amplifier OPA1, PMOS transistors P9, P10, P11, P12, and P16, NMOS transistors N3, N4, and N7, resistors R4 and R5, and NPN BJT transistors Q4, Q5, Q6, and Q7.

[0012] In this configuration, the sources of P9, P10, P11, P12, P13, and P16 are all connected to the power supply VDD; the drains of P9, N3, N3, and N4 are connected; the gates of P10, P10, N4, and P11 are connected; the source of N3, the collector of Q4, the base of Q4, and the base of Q5 are connected; the source of N4 and the collector of Q5 are connected; and the emitter of Q4, the collector of Q6, the base of Q6, and the operational amplifier OPA are connected. The negative input node N of P11 is connected; the emitter of Q5 and the first terminal of R4 are connected; the drain of P11, the first terminal of R5, the base of Q7, and the collector of Q7 are connected; the gates of P12 and P16 are connected to the input node of operational amplifier OPA1; the second terminal of R5, the drain of P12, and the positive output node P of OPA1 are connected; the drain of P16, the drain of N7, and the gate of N7 are connected; the emitter of Q6, the second terminal of R4, the emitter of Q7, and the source of N7 are all connected to ground GND.

[0013] Optionally, the operational amplifier OPA1 includes: PMOS transistors P13, P14, and P15, NMOS transistors N5 and N6, resistor R13, and capacitor C1;

[0014] Among them, the source of P13 is connected to the power supply VDD; the drain of P13, the source of P14, and the source of P15 are connected; the drain of P14 and the drain of N5 are connected; the drain of P15, the drain of N6, the gate of N6, and the gate of N5 are connected; the gate of P14, the first terminal of C1, the second terminal of C1, and the first terminal of R13 are connected; the second terminal of R13, the source of N5, and the source of N6 are all connected to the ground GND.

[0015] Optionally, the startup circuit includes: PMOS transistors P17, P18, and P19; NMOS transistors N8 and N9; and NPN BJT transistors Q8, Q9, Q10, Q11, Q12, and Q17.

[0016] In this configuration, the sources of P17, P18, and P19 are all connected to the power supply VDD; the drain of P17, the drain of N8, the gate of N8, and the gate of N9 are connected; the gate of P18, the gate of P19, and the drain of P18 are connected; the drain of P19, the collector of Q8, the base of Q8, and the base of Q17 are connected; the emitter of Q17, the collector of Q10, and the base of Q10 are connected; the emitter of Q8, the collector of Q9, and the base of Q9 are connected; the emitter of Q10, the collector of Q11, and the base of Q11 are connected; the emitter of Q11, the collector of Q12, and the base of Q12 are connected; and the emitters of Q9 and Q12 are both connected to the ground terminal GND.

[0017] Optionally, the bandgap reference core circuit includes: operational amplifier OPA2, NPN BJT transistors Q13 and Q14, PMOS transistors P20 and P21, NMOS transistor N10, and resistors R6, R7, R8, R9, R10, R11, and R12.

[0018] In this configuration, the sources of P20 and P21 are connected to the power supply VDD; the first terminal of R6 is connected to the drain of P20; the first terminal of R9 is connected to the second terminal of R6, the drain of P21, and the drain of N10; the first terminal of R7, the second terminal of R9, and the first terminal of R10 are connected; the second terminal of R7, the first terminal of R8, the base of Q13, and the positive input terminal of operational amplifier OPA2 are connected to node X; the second terminal of R10, the collector of Q14, and the negative input terminal of operational amplifier OPA2 are connected to node Y; the second terminal of R8, the collector of Q13, and the base of Q14 are connected; the first terminal of R11 is connected to the emitter of Q14; the first terminal of R12, the second terminal of R11, and the emitter of Q13 are connected, and the second terminal of R12 is connected to ground GND.

[0019] Optionally, the operational amplifier OPA2 includes: PMOS transistors P22, P23, and P24; NMOS transistors N11 and N12; NPN BJT transistors Q15 and Q16; resistor R14; and capacitor C2.

[0020] Specifically, the gates of P22, P23, and P24 are connected to the drain of N11 and then to the drain of P23; the sources of P22, P23, and P24 are all connected to the power supply VDD; the drain of P24, the drain of N12, the gate of N12, and the gate of N11 are connected; the source of N11 is connected to the collector of Q15; the source of N12 is connected to the collector of Q16; and the emitters of Q15 and Q16 are connected and then to the first terminal of R12.

[0021] The technical effect of this invention is as follows: This invention uses a current with a high-order temperature term to compensate for the reference voltage, eliminating the high-order temperature characteristics of the reference voltage and obtaining a reference voltage V with zero temperature coefficient. BG This reference voltage has a low temperature coefficient of 1.425ppm / ℃ over the range of -55℃ to 125℃, making it suitable for use in low dropout linear regulators, switching power supplies, and digital-to-analog converter circuits. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 This is a high-order temperature-compensated bandgap reference circuit diagram according to an embodiment of the present invention;

[0024] Figure 2 This is a core circuit diagram of the bandgap reference according to an embodiment of the present invention;

[0025] Figure 3 This is a DC simulation result diagram of the output voltage VBG in an embodiment of this utility model;

[0026] Figure 4 The figure shows the Monte Carlo simulation results of the output voltage VBG in this embodiment of the present invention. Detailed Implementation

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] like Figure 1As shown, this embodiment provides a high-order temperature-compensated bandgap reference circuit, including: a bias circuit, a compensation current generation circuit, a startup circuit, and a bandgap reference core circuit connected in sequence.

[0029] Bias circuit, used to generate bias current with a positive temperature coefficient;

[0030] The compensation current generating circuit is used to generate a current with a high-order temperature coefficient, and obtain the mirror current through a current mirror.

[0031] A startup circuit is used to control the startup of the bandgap reference core circuit based on the bias current generated by the bias circuit.

[0032] The core circuit of the bandgap reference is used to compensate the reference voltage with a current having a high temperature coefficient, thereby generating a reference voltage with a low temperature coefficient.

[0033] Furthermore, the bias circuit includes: eight PMOS transistors P1, P2, P3, P4, P5, P6, P7, and P8; two NMOS transistors N1 and N2; three NPN BJT transistors Q1, Q2, and Q3; and three resistors R1, R2, and R3. The sources of P1, P5, P6, P7, and P8 are all connected to the power supply VDD; the gates of P1, P5, P6, P2, P3, and P4 are connected; and the drain of P4 and the first resistor of R1 are connected... The terminals are connected; the drain of P5 and the collector of Q1 are connected; the base of Q1 and the base of Q2 are connected; the first terminal of R2, the emitter of Q3, and the drain of P8 are connected; the drain of N1, the drain of P6, the gate of N1, and the gate of N2 are connected; the emitter of N1, the base of Q3, and the collector of Q2 are connected; the gate of P7, the gate of P8, the drain of P7, and the drain of N2 are connected; the source of N2 and the collector of Q3 are connected; the second terminals of R1, R2, and R3 are all connected to ground GND.

[0034] Specifically, the bias circuit is obtained using NPN BJT transistors Q1 and Q2 with an area ratio of 4:1, resistors R2 and R3, NPN BJT transistor Q3, current mirrors N1 and N2 with a 1:1 ratio, and current mirrors P7 and P8 with a 1:1 ratio. The resistance values ​​R2 and R1 are equal. Q3 =I Q2 =I Q3 =I P8 This results in a positive temperature coefficient current. And the signal is mirrored to the BJT transistor Q6 through the MOSFET P9.

[0035] Furthermore, the compensation current generation circuit includes: operational amplifier OPA1, five PMOS transistors P9, P10, P11, P12, and P16, three NMOS transistors N3, N4, and N7, two resistors R4 and R5, and four NPN BJT transistors Q4, Q5, Q6, and Q7; wherein: the gate of P9 is connected to the gate of P8; the sources of P9, P10, P11, P12, P13, and P16 are all connected to the power supply VDD; the drain of P9, the drain of N3, the gate of N3, and the gate of N4 are connected; the gate of P10, the drain of P10, the drain of N4, and the gate of P11 are connected; the source of N3 and the collector of Q4, The bases of Q4 and Q5 are connected; the source of N4 and the collector of Q5 are connected; the emitter of Q4, the collector of Q6, the base of Q6, and the negative input node N of operational amplifier OPA1 are connected; the emitter of Q5 and the first terminal of R4 are connected; the drain of P11, the first terminal of R5, the base of Q7, and the collector of Q7 are connected; the gates of P12 and P16 are connected to the input node of operational amplifier OPA1; the second terminal of R5, the drain of P12, and the positive output node P of OPA1 are connected; the drain of P16, the drain of N7, and the gate of N7 are connected; the emitter of Q6, the second terminal of R4, the emitter of Q7, and the source of N7 are all connected to ground GND.

[0036] Furthermore, the operational amplifier OPA1 includes: three PMOS transistors P13, P14, and P15; two NMOS transistors N5 and N6; one resistor R13; and one capacitor C1. Specifically: the source of P13 is connected to the power supply VDD; the drains of P13, P14, and P15 are connected; the drains of P14 and N5 are connected; the drains of P15, N6, N6, and N5 are connected; the gate of P14 is connected to the first terminal of C1; the second terminal of C1 is connected to the first terminal of R13; and the second terminal of R13, the source of N5, and the source of N6 are all connected to ground GND.

[0037] Specifically, regarding the generation of compensation current with high-order temperature coefficients, the high-order temperature coefficient of the BJT transistor is often considered. To facilitate subsequent derivation, we will explain the physical meanings of η and σ in this formula. η is a process-related temperature constant, and σ is a variable related to the temperature characteristics of the collector current of the BJT transistor. Its value is 1 when the collector current is the PTAT current; its value is 0 when the collector current of the BJT transistor is independent of temperature. For BJT transistor Q6, the collector current flowing through it is obtained by mirroring the bias current and is the PTAT current, therefore: After passing through BJT transistors Q4 and Q5, the voltage V at the first terminal of resistor R4 is obtained.A =V BE6 (T), to obtain the current flowing through the point resistance R4. Therefore, I1 is the CTAT current. After mirroring through current mirrors P10 and P11, we get I2 = I1. The collector voltage of BJT transistor Q7 is V. B After being clamped by the op amplifier, V P =V N Then the voltage difference across resistor R5 is V. P -V B When the higher-order temperature coefficient of current I3 is ignored, we obtain That is, I3 is the PTAT current. By adjusting the ratio of R4 and R5, the current I3 with zero temperature coefficient can be obtained. At this time, for the potential at point B, we have Meanwhile, to ensure that the potential at point P is greater than the potential at point B, the area ratio of BJT transistors Q6 and Q7 is set to 1:4. When reconsidering the higher-order temperature coefficient of current I3... Thus, a current I3 with a high-order temperature coefficient is obtained. After this current is generated, it passes through current mirrors P16, P20 and current mirrors N7, N10 to obtain mirror currents I3 = I4 = I5 = I6.

[0038] Furthermore, the startup circuit includes: three PMOS transistors P17, P18, and P19; two NMOS transistors N8 and N9; and six NPN BJT transistors Q8, Q9, Q10, Q11, Q12, and Q17. Specifically: the gate of P17 is connected to the gate of P13; the sources of P17, P18, and P19 are all connected to the power supply VDD; the drain of P17, the drain of N8, the gate of N8, and the gate of N9 are connected; the drain of N9 is connected to the drain of P18; and the gates of P18 and P19 are connected... The drain of P18 is connected to the base of P19, the collector of Q8, the base of Q8, and the base of Q17. The emitter of Q17, the collector of Q10, and the base of Q10 are connected. The emitter of Q8, the collector of Q9, and the base of Q9 are connected. The emitter of Q10, the collector of Q11, and the base of Q11 are connected. The emitter of Q11, the collector of Q12, and the base of Q12 are connected. The emitter of Q9, the emitter of Q12, the source of N8, and the source of N9 are all connected to ground (GND).

[0039] Specifically, for a startup circuit that can automatically shut off after startup, the current from the bias circuit is mirrored to MOSFET P19 and then raised to the base potential of Q17 via diode-connected BJTs Q8 and Q9. After Q17 turns on, MOSFET P23 and diode-connected BJTs Q10, Q11, and Q12 form a path to ground, mirroring the current to P22 and P24, which increases during startup, ultimately causing OPA2 to operate. Node C is connected to the collector of Q10, and its potential changes with V.C As the potential gradually increases, after BJT Q13 turns on, current is generated to ground through resistors R7, R8, R12, and BJT Q13, ultimately starting the bandgap reference core circuit. As the circuit starts, the current mirrored by P22 increases. When this current equals the bias current mirrored by N9, the currents of N18 and N19 become zero, and the startup circuit turns off.

[0040] Furthermore, such as Figure 2 As shown, the core circuit of the bandgap reference includes: operational amplifier OPA2, two NPN BJT transistors Q13 and Q14, two PMOS transistors P20 and P21, one NMOS transistor N10, and seven resistors R6, R7, R8, R9, R10, R11, and R12. Specifically: the sources of P20 and P21 are both connected to the power supply VDD; the first terminal of R6 is connected to the drain of P20; the first terminal of R9 is connected to the second terminal of R6, the drain of P21, and the drain of N10; the first terminal of R7, the second terminal of R9, and R12 are connected to the drain of P20; and the first terminal of R7, the second terminal of R9, and R12 are connected to the drain of P20. The first terminal of R10 is connected; the second terminal of R7, the first terminal of R8, the base of Q13, and the positive input terminal of operational amplifier OPA2 are connected to node X; the second terminal of R10, the collector of Q14, and the negative input terminal of operational amplifier OPA2 are connected to node Y; the second terminal of R8, the collector of Q13, and the base of Q14 are connected; the first terminal of R11 is connected to the emitter of Q14; the first terminal of R12, the second terminal of R11, and the emitter of Q13 are connected, and the second terminal of R12 is connected to ground GND.

[0041] Furthermore, the operational amplifier OPA2 includes: three PMOS transistors P22, P23, and P24; two NMOS transistors N11 and N12; two NPN BJT transistors Q15 and Q16; one resistor R14; and one capacitor C2. Specifically: the drain of P22 is connected to the drain of P18; the drain of P23 is connected to the collector of Q17; the gates of P22, P23, and P24, and the drain of N11 are connected and then connected to the drain of P23; the sources of P22, P23, and P24 are all connected to the power supply VDD; the drain of P24, the drain of N12, the gate of N12, and the gate of N11 are connected; the source of N11 and the collector of Q15 are connected; the source of N12 and the collector of Q16 are connected; and the emitters of Q15 and Q16 are connected and then connected to the first terminal of R12.

[0042] Specifically, for the core circuit of the bandgap reference, the voltages at nodes X and Y are made the same by clamping with OPA2. The collector current flowing through the same circuit is obtained from the mirrored currents of BJT transistors Q13, Q14, Q15, and Q16, and is denoted as I7. The area ratio of BJT transistors Q13 and Q14 is 1:8, then... Therefore, the voltage at node C is V.C =I7(4R 12 +R7+R8+2R9)+V BE13 Since the collector current of BJT transistor Q13 is PTAT current, then we have A current I5 with a high-order temperature coefficient is introduced into the bandgap core circuit, and the final reference voltage V is obtained through R6. BG V BG =V C +I5R6, combining the above results, we get:

[0043]

[0044] As can be seen from the above formula, the higher-order temperature coefficient of the bandgap reference can be completely eliminated by adjusting the ratio of resistors R5 and R6, and the first-order temperature coefficient of the bandgap reference can be eliminated by adjusting the ratio of resistors R8 and R7. Through the above adjustments, a reference voltage that is independent of temperature can be obtained.

[0045] like Figure 3 The figure shown is a DC simulation result of the output voltage VBG of this utility model embodiment. In the temperature range of -55℃ to 125℃, the VBG voltage varies from 1.2203627V to 1.2205836V. Under the condition of normal temperature of 25℃, the VBG voltage is 1.220441V. Its temperature coefficient is calculated to be 1.425ppm / ℃.

[0046] like Figure 4 The figure shown is a Monte Carlo simulation result of the output voltage VBG of this embodiment. With 300 samples, the average VBG voltage is 1.22071V, and the standard deviation is 9.6895mV, indicating that the VBG voltage fluctuation is small and the circuit performance is stable. This invention discloses a high-order temperature-compensated bandgap reference circuit, which includes a bias circuit, a compensation current generation circuit, a bandgap reference core circuit, and a startup circuit. The bandgap reference circuit can generate a low-temperature drift reference voltage V. BG The bias circuit generates a positive temperature coefficient current; the startup circuit ensures the bandgap reference core circuit escapes its degenerate state and starts normally; the compensation current generation circuit outputs a high-order temperature coefficient current to provide high-order compensation for the reference potential. As the most widely used reference source circuit, the bandgap reference circuit utilizes the negative temperature coefficient base-emitter voltage V of the BJT transistor. BE The base-emitter voltage difference ΔV between two BJT transistors with a positive temperature coefficient BE By adding them in a certain proportion, a reference voltage output that is approximately independent of temperature is obtained. The reference voltage V output by this invention... BGIt has the advantage of low temperature drift over a wide temperature range and is suitable for power management chips, digital-to-analog conversion circuits, etc.

[0047] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high-order temperature-compensated bandgap reference circuit, characterized in that, include: The bias circuit, compensation current generation circuit, startup circuit and bandgap reference core circuit are connected in sequence. The bias circuit is used to generate a bias current with a positive temperature coefficient. The compensation current generating circuit is used to generate a current with a high-order temperature coefficient. The startup circuit is used to control the startup of the bandgap reference core circuit according to the bias current generated by the bias circuit. The bandgap reference core circuit is used to compensate the reference voltage with the current having a high temperature coefficient, thereby generating a reference voltage with a low temperature coefficient.

2. The high-order temperature-compensated bandgap reference circuit as described in claim 1, characterized in that, The bias circuit includes PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, NMOS transistors N1, N2, NPN BJT transistors Q1, Q2, Q3, and resistors R1, R2, R3. In this configuration, the sources of P1, P5, P6, P7, and P8 are all connected to the power supply VDD; the gates of P1, P5, P6, P2, P3, and P4 are connected; the drain of P4 is connected to the first terminal of R1; the drain of P5 is connected to the collector of Q1; the base of Q1 and the base of Q2 are connected; the first terminal of R2, the emitter of Q3, and the drain of P8 are connected; the drain of N1, the drain of P6, the gate of N1, and the gate of N2 are connected; the emitter of N1, the base of Q3, and the collector of Q2 are connected; the gates of P7, P8, and P7, and the drain of N2 are connected; the source of N2 and the collector of Q3 are connected; and the second terminals of R1, R2, and R3 are all connected to the ground GND.

3. The high-order temperature-compensated bandgap reference circuit as described in claim 1, characterized in that, The compensation current generating circuit includes: operational amplifier OPA1, PMOS transistors P9, P10, P11, P12, P16, NMOS transistors N3, N4, N7, resistors R4, R5, and NPN type BJT transistors Q4, Q5, Q6, Q7. In this configuration, the sources of P9, P10, P11, P12, P13, and P16 are all connected to the power supply VDD; the drains of P9, N3, N3, and N4 are connected; the gates of P10, P10, N4, and P11 are connected; the source of N3, the collector of Q4, the base of Q4, and the base of Q5 are connected; the source of N4 and the collector of Q5 are connected; and the emitter of Q4, the collector of Q6, the base of Q6, and the operational amplifier OPA are connected. The negative input node N of P11 is connected; the emitter of Q5 and the first terminal of R4 are connected; the drain of P11, the first terminal of R5, the base of Q7, and the collector of Q7 are connected; the gates of P12 and P16 are connected to the input node of operational amplifier OPA1; the second terminal of R5, the drain of P12, and the positive output node P of OPA1 are connected; the drain of P16, the drain of N7, and the gate of N7 are connected; the emitter of Q6, the second terminal of R4, the emitter of Q7, and the source of N7 are all connected to ground GND.

4. The high-order temperature-compensated bandgap reference circuit as described in claim 3, characterized in that, The operational amplifier OPA1 includes: PMOS transistors P13, P14, and P15; NMOS transistors N5 and N6; resistor R13; and capacitor C1. Among them, the source of P13 is connected to the power supply VDD; the drain of P13, the source of P14, and the source of P15 are connected; the drain of P14 and the drain of N5 are connected; the drain of P15, the drain of N6, the gate of N6, and the gate of N5 are connected; the gate of P14, the first terminal of C1, the second terminal of C1, and the first terminal of R13 are connected; the second terminal of R13, the source of N5, and the source of N6 are all connected to the ground GND.

5. The high-order temperature-compensated bandgap reference circuit as described in claim 1, characterized in that, The startup circuit includes: PMOS transistors P17, P18, and P19; NMOS transistors N8 and N9; and NPN BJT transistors Q8, Q9, Q10, Q11, Q12, and Q17. In this configuration, the sources of P17, P18, and P19 are all connected to the power supply VDD; the drain of P17, the drain of N8, the gate of N8, and the gate of N9 are connected; the gate of P18, the gate of P19, and the drain of P18 are connected; the drain of P19, the collector of Q8, the base of Q8, and the base of Q17 are connected; the emitter of Q17, the collector of Q10, and the base of Q10 are connected; the emitter of Q8, the collector of Q9, and the base of Q9 are connected; the emitter of Q10, the collector of Q11, and the base of Q11 are connected; the emitter of Q11, the collector of Q12, and the base of Q12 are connected; and the emitters of Q9 and Q12 are both connected to the ground terminal GND.

6. The high-order temperature-compensated bandgap reference circuit as described in claim 1, characterized in that, The core circuit of the bandgap reference includes: operational amplifier OPA2, NPN BJT transistors Q13 and Q14, PMOS transistors P20 and P21, NMOS transistor N10, and resistors R6, R7, R8, R9, R10, R11, and R12. In this configuration, the sources of P20 and P21 are connected to the power supply VDD; the first terminal of R6 is connected to the drain of P20; the first terminal of R9 is connected to the second terminal of R6, the drain of P21, and the drain of N10; the first terminal of R7, the second terminal of R9, and the first terminal of R10 are connected; the second terminal of R7, the first terminal of R8, the base of Q13, and the positive input terminal of operational amplifier OPA2 are connected to node X; the second terminal of R10, the collector of Q14, and the negative input terminal of operational amplifier OPA2 are connected to node Y; the second terminal of R8, the collector of Q13, and the base of Q14 are connected; the first terminal of R11 is connected to the emitter of Q14; the first terminal of R12, the second terminal of R11, and the emitter of Q13 are connected, and the second terminal of R12 is connected to ground GND.

7. The high-order temperature-compensated bandgap reference circuit as described in claim 6, characterized in that, The operational amplifier OPA2 includes: PMOS transistors P22, P23, and P24; NMOS transistors N11 and N12; NPN BJT transistors Q15 and Q16; resistor R14; and capacitor C2. Specifically, the gates of P22, P23, and P24 are connected to the drain of N11 and then to the drain of P23; the sources of P22, P23, and P24 are all connected to the power supply VDD; the drain of P24, the drain of N12, the gate of N12, and the gate of N11 are connected; the source of N11 is connected to the collector of Q15; the source of N12 is connected to the collector of Q16; and the emitters of Q15 and Q16 are connected and then to the first terminal of R12.

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