Wafer level packaging thermopile infrared array chip

Abstract

The utility model provides a wafer level packaging thermopile infrared array chip comprising a device wafer, the surface of which comprises at least one thermopile chip; the packaging layer covers the front surface of the device wafer; and a condensation structure is arranged at a position, corresponding to the thermopile of the thermopile chip, on the back surface of the device wafer. According to the technical scheme, the packaging process can be implemented under the wafer-level size, the packaging efficiency of the thermopile infrared array chip is improved, and the process cost is reduced.

Description

Technical Field

[0001] This utility model relates to the field of MEMS chips, and in particular to a wafer-level packaged thermopile infrared array chip. Background Technology

[0002] Thermocouple chips convert thermal energy into electrical energy using thermocouples made of two different materials. When one end of the thermocouple is warmer, a temperature difference is created between the two ends, which excites charge movement and generates a voltage. This voltage can be used to power electronic devices, measure temperature, and sense heat sources. It has wide applications in microdevices, wireless sensors, satellite aerospace, and medical devices.

[0003] With the widespread application of thermopile chips, how to reduce chip manufacturing costs and better meet the needs of large-scale applications is a problem that existing technologies need to solve. Summary of the Invention

[0004] The technical problem to be solved by this utility model is to provide a wafer-level packaged thermopile infrared array chip, which can improve the packaging efficiency of the thermopile infrared array chip and reduce the process cost.

[0005] To address the aforementioned issues, this invention provides a wafer-level packaged thermopile infrared array chip, comprising: a device wafer, the surface of which includes at least one thermopile chip; an encapsulation layer covering the front side of the device wafer; and a light-concentrating structure located on the back side of the device wafer at a position corresponding to the thermopile of the thermopile chip.

[0006] Optionally, the encapsulation layer is selected from one of a supporting wafer and a multi-layer wiring layer.

[0007] Optionally, the encapsulation layer includes an infrared reflector at a position corresponding to the thermopile of the thermopile chip.

[0008] Optionally, the light-concentrating structure is selected from a type of superstructure lens.

[0009] Optionally, an infrared anti-reflection coating is included on the surface of the back side of the device wafer.

[0010] Optionally, the device wafer surface may also integrate CMOS driving circuitry for signal readout and processing.

[0011] The above technical solution enables packaging processes to be implemented at the wafer level, improving the packaging efficiency of thermopile infrared array chips and reducing process costs. Attached Figure Description

[0012] Appendix Figure 1The diagram shows the implementation steps of the fabrication method for the wafer-level packaged thermopile infrared array chip according to a specific embodiment of this utility model.

[0013] Appendix Figure 2A To be continued Figure 2E The diagram shown is a process flow chart of the fabrication method of the wafer-level packaged thermopile infrared array chip according to a specific embodiment of this utility model.

[0014] Appendix Figure 3 The diagram shown is a schematic diagram of the structure of the wafer-level packaged thermopile infrared array chip according to a specific embodiment of this utility model.

[0015] Appendix Figure 4 The diagram shown is a schematic diagram of the structure of the wafer-level packaged thermopile infrared array chip according to a specific embodiment of this utility model.

[0016] Appendix Figure 5 The diagram shown is a schematic diagram of the structure of the wafer-level packaged thermopile infrared array chip according to a specific embodiment of this utility model.

[0017] Appendix Figure 6 The diagram shown is a schematic diagram of the structure of the wafer-level packaged thermopile infrared array chip according to a specific embodiment of this utility model. Detailed Implementation

[0018] The specific embodiments of the wafer-level packaged thermopile infrared array chip provided by this utility model are described in detail below with reference to the accompanying drawings.

[0019] Appendix Figure 1 The diagram illustrates the implementation steps of the wafer-level packaged thermopile infrared array chip fabrication method according to this invention. This specific embodiment better explains the chip structure. (See attached diagram.) Figure 1 As shown, the method includes the following steps: Step S10, providing a device wafer, the surface of which includes at least one thermopile chip; Step S11, covering the front side of the device wafer with an encapsulation layer to form an encapsulation structure; Step S12, thinning the back side of the device wafer; Step S13, forming a light-concentrating structure on the back side of the device wafer at a position corresponding to the thermopile of the thermopile chip; and Step S14, forming an infrared anti-reflection film on the surface of the back side of the device wafer.

[0020] Appendix Figure 2AAs shown, referring to step S10, a device wafer 10 is provided, the surface of which includes at least one thermopile chip. Figure 2 shows an example with one thermopile chip 11. In other embodiments, it may also include multiple thermopile chips arranged in parallel, or an array of more thermopile chips. The surface of the device wafer 10 also includes driving circuitry 12, including but not limited to integrated CMOS driving circuitry, for reading out and processing the output signals of the thermopile chips. The output signals of the thermopile chips can also be directly output and processed by an external ASIC.

[0021] Appendix Figure 2B As shown, referring to step S11, a packaging layer is applied to the front side of the device wafer 10 to form a packaging structure. The packaging layer is selected from either a supporting wafer or a multi-layer wiring layer. (See attached image) Figure 2B The diagram illustrates a specific implementation using a support wafer 13 as the packaging structure. The support wafer 13 is mounted on the front side of the device wafer 10 using a wafer-level packaging process to form a sealed packaging structure. Electrical leads are then formed using through-hole etching, and the entire package is diced to complete the packaging.

[0022] Appendix Figure 2C As shown, referring to step S12, the back side of the device wafer 10 is thinned. This step is optional. Since the thermopile chip mainly absorbs infrared light, and the wafer is usually made of materials transparent to infrared light, such as silicon, the thermopile chip 11 can still work without thinning the wafer 10. However, thinning can reduce the absorption rate of the device wafer 10, which is more conducive to improving the sensitivity of the thermopile chip 11. Thinning can be performed by mechanical polishing, wet etching, or a combination of both.

[0023] Appendix Figure 2D As shown, referring to step S13, a focusing structure is formed on the back side of the device wafer 10 at a position corresponding to the thermopile of the thermopile chip 11. The focusing structure is selected from a type of superstructure lens. (See attached image) Figure 2D The light-gathering structure shown is a convex lens 14. The convex lens structure can be released on the back side of the device wafer 10 by wet etching, or it can be assembled onto the surface by mounting a convex lens made of transparent materials such as resin.

[0024] Appendix Figure 2E As shown, referring to step S14, an infrared antireflection film 15 is formed on the back surface of the device wafer 10. This step is optional. The antireflection film 15 facilitates better transmission of infrared light through the surface of the device wafer 10 into the thermopile of the thermopile chip 11, thereby improving the sensitivity of the thermopile chip 11. Preferably, the antireflection film 15 is formed on the surface of the convex lens 14, which serves as a light-concentrating structure.

[0025] The wafer-level packaged thermopile infrared array chip obtained after completing the above steps is shown in the attached figure. Figure 2E As shown, the method includes: a device wafer, the surface of which includes at least one thermopile chip; a packaging layer covering the front side of the device wafer; and a light-concentrating structure on the back side of the device wafer corresponding to the thermopile of the thermopile chip. This method enables packaging processes at the wafer level, improving the packaging efficiency of thermopile infrared array chips and reducing process costs.

[0026] In one specific embodiment of this utility model, refer to the appendix. Figure 3 As shown, the encapsulation layer is a multi-wire layer 30.

[0027] In one specific embodiment of this utility model, refer to the appendix. Figure 4 As shown, the encapsulation layer further includes an infrared reflector 40 at the position corresponding to the thermopile of the thermopile chip, which is used to improve the sensitivity of the thermopile chip 11.

[0028] In one specific embodiment of this utility model, refer to the appendix. Figure 5 As shown, the light-concentrating structure can also be a Fresnel lens 50 composed of multiple concentric rings, which can also serve to converge light.

[0029] In one specific embodiment of this utility model, refer to the appendix. Figure 6 As shown, it may also include multiple thermopile chips arranged in parallel, or an array of more thermopile chips, wherein the structure of each thermopile chip is as described above.

[0030] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. A wafer-level packaged thermopile infrared array chip, characterized in that, include: A device wafer, the surface of which includes at least one thermopile chip; An encapsulation layer covering the front side of the device wafer; A light-concentrating structure is included on the back side of the device wafer at a location corresponding to the thermopile of the thermopile chip.

2. The chip according to claim 1, characterized in that, The encapsulation layer is selected from one of the support wafer and the multiple wiring layer.

3. The chip according to claim 1, characterized in that, The encapsulation layer includes an infrared reflector at a position corresponding to the thermopile of the thermopile chip.

4. The chip according to claim 1, characterized in that, The light-gathering structure is selected from one type of superstructure lens.

5. The chip according to claim 1, characterized in that, The back surface of the device wafer includes an infrared anti-reflection coating.

6. The chip according to claim 1, characterized in that, The device also integrates a CMOS driver circuit on its wafer surface for signal readout and processing.

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