Semiconductor power device packaging structure
By optimizing the pad surface and wiring design, the problem of non-uniform equivalent Rdson in the half-bridge branch of the high-integration package structure was solved, achieving uniform equivalent Rdson and improved chip integration, while reducing signal and power coupling interference.
Patent Information
- Application Number
- CN202520685538.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-12
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-04-12
AI Technical Summary
In highly integrated package structures, the equivalent Rdson of MOS switches in different half-bridge branches is not uniform within the package structure, which affects circuit performance.
The 6-in-1 package design optimizes the pad surface and wiring design to ensure that the equivalent Rdson of the MOS switches corresponding to each half-bridge branch is uniform within the package structure. Adjacent edge pads that are shorted on the pad surface are set at the ground terminal and the phase voltage terminal to increase the pad area and reduce coupling interference between signals and power.
This achieves equivalent Rdson uniformity in each half-bridge branch, increases pad area, reduces coupling interference between signals and power supplies, and improves overall circuit performance and chip integration.
Smart Images
Figure CN223829844U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip technology, and in particular to a semiconductor power device packaging structure. Background Technology
[0002] The packaging structure of electronic components mainly includes chips and pins housed within the package. Pins are used to bring out the internal circuitry of the chip, so that the chip can be connected to external circuits or external devices.
[0003] With the development of computers, communications, automotive electronics, aerospace, and other consumer systems, highly integrated power packaging, through optimized packaging structures and processes, effectively integrates and packages multiple power devices onto a single substrate. This packaging significantly improves chip integration, resulting in a substantial increase in power handling capacity per unit area. A common example is a MOS switching circuit such as... Figure 1 As shown, six MOS switches are connected in pairs to form three half-bridge branches, which are then connected in parallel across the power supply and ground terminals, forming a three-phase bridge circuit. Since the traces on the package substrate have a certain resistance, differences in trace length between different half-bridge branches can result in a difference of approximately 1mΩ in the equivalent resistance. Therefore, how to encapsulate the six MOS switches within a single package structure, ensuring that the equivalent resistance of the MOS switches corresponding to each different half-bridge branch within the package structure is within the correct range, is a key challenge. dson Ensuring the overall performance of the circuit is an urgent problem to be solved. Utility Model Content
[0004] In view of this, the purpose of this utility model is to provide a packaging structure that enables the MOS switches corresponding to different half-bridge branches to have equivalent R within the packaging structure. dson On the one hand, uniformity, and on the other hand, by setting two adjacent edge pads that are shorted on the pad surface for each circuit function terminal in the ground terminal and phase voltage terminal, the pad area can be increased and the equivalent R can be further improved. dson Uniformity is needed to solve the above problems.
[0005] Based on the above objectives, this utility model provides a semiconductor power device packaging structure, including a substrate, three half-bridge branches, and a package body;
[0006] Each of the half-bridge branches includes two switching chips connected in series;
[0007] The switching chip is disposed on the substrate, and the package covers the substrate and the switching chip.
[0008] The semiconductor power device package structure has a pad surface, which has a first side, a second side, a third side and a fourth side that are adjacent to each other in sequence. The first side and the third side are parallel. A power supply edge pad is provided on the first side, and a ground edge pad is provided on the third side. The half-bridge branch is connected between the power supply edge pad and the ground edge pad through a substrate.
[0009] A phase voltage terminal edge pad is provided on the second side; a signal pad is provided on the fourth side; the phase voltage terminal edge pad is electrically connected to the midpoint of the half-bridge branch; the signal pad is electrically connected to the gate of the switching chip.
[0010] The pad surface is also provided with a power supply rectangular pad and three phase voltage rectangular pads; the power supply edge pad and the power supply rectangular pad are connected on the pad surface; the phase voltage rectangular pad array is provided on the side of the power supply rectangular pad near the third side.
[0011] Each half-bridge branch has two adjacent grounding terminal edge pads that are connected on the pad surface;
[0012] Each half-bridge branch has two adjacent pads on the edge of the phase voltage terminal that are connected on the pad surface.
[0013] Preferably, it further includes a first wiring layer, a second wiring layer, and a vertical electrical connector;
[0014] The first wiring layer is disposed on the substrate, the switch chip and the vertical electrical connector are disposed between the first wiring layer and the second wiring layer, and the package further covers the first wiring layer, the second wiring layer and the vertical electrical connector;
[0015] The switch chip has a first side and a second side, the first side is electrically connected to a first wiring layer, and the second side is electrically connected to a second wiring layer; the two ends of the vertical electrical connector are respectively electrically connected to the first wiring layer and the second wiring layer.
[0016] Preferably, the vertical electrical connector includes a vertical signal electrical connector and a vertical power electrical connector; the projection shape of the vertical signal electrical connector on the pad surface is circular, and the projection shape of the vertical power electrical connector on the pad surface is elongated.
[0017] Preferably, there are six vertical power electrical connectors, and a horizontal wiring area is provided between the two switching chips of each half-bridge branch. Three of the vertical power electrical connectors are located in the horizontal wiring area, and the other three of the vertical power electrical connectors are located on the third side adjacent to the package body. The vertical signal electrical connector is located on the fourth side adjacent to the package body.
[0018] Preferably, at least one wiring for forming an electrical connection between the phase voltage terminal edge pad and the midpoint of the half-bridge passes through the lateral wiring area, and at least one wiring for forming an electrical connection between the signal pad and the gate of the switch chip passes through the lateral wiring area.
[0019] Preferably, the source and gate of the switch chip are disposed on the second side, and the drain of the switch chip is disposed on the first side. The drain of each switch chip is electrically connected to a rectangular pad at a corresponding position on the pad surface through a first wiring layer and a substrate.
[0020] In summary, this utility model has the following beneficial effects:
[0021] 1) This utility model adopts a 6-in-1 encapsulation form to improve the chip integration. The pin and wiring arrangement makes the equivalent R of the MOS switches corresponding to different half-bridge branches within the package structure more efficient. dson On the one hand, uniformity, and on the other hand, by setting two adjacent edge pads that are shorted on the pad surface for each circuit function terminal in the ground terminal and phase voltage terminal, the pad area can be increased and the equivalent R can be further improved. dson Uniform;
[0022] 2) Since the power supply edge pads and signal pads are set on adjacent sides, the vertical routing between the signal and power supplies can reduce coupling interference; the signal pads occupy a separate side, and the circuit board layout can also better achieve the regional division of the power supply module and the signal module. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a circuit diagram of an embodiment of the present utility model;
[0025] Figure 2 This is a diagram showing the pin distribution on the pad surface of an embodiment of the present invention;
[0026] Figure 3 This is a schematic diagram of the wiring structure according to an embodiment of the present utility model. Detailed Implementation
[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0028] Figure 1 The circuit diagram of this embodiment is shown. The semiconductor power device package structure of this embodiment includes a first half-bridge branch, a second half-bridge branch, and a third half-bridge branch. Each half-bridge branch includes two semiconductor power devices (MOS switch chips) connected in series. The first half-bridge branch includes a first switch M1 and a second switch M2. The source S1 of the first switch M1 and the drain D2 of the second switch are electrically connected (i.e., the midpoint of the half-bridge) and led out to the first phase voltage terminal pin Ph1. The second half-bridge branch includes a third switch M3 and a fourth switch M4. The source S3 of the third switch M3 and the drain D4 of the fourth switch are electrically connected and led out to the second phase voltage terminal pin Ph2. The third half-bridge... The branch includes the fifth switch M5 and the sixth switch M6. The source S5 of the fifth switch M5 and the drain D6 of the sixth switch are electrically connected and led out to the third phase voltage terminal pin Ph3. The drain D1 of the first switch M1, the drain D3 of the third switch M3 and the drain D5 of the fifth switch M5 are electrically connected and led out to form the power supply terminal pin VDD. The source S2 of the second switch M2, the source S4 of the fourth switch M4 and the source S6 of the sixth switch M6 are led out as the first ground terminal pin GND1, the second ground terminal pin GND2 and the fourth ground terminal pin GND4, respectively. The gates G1 / 2 / 3 / 4 / 5 / 6 of each switch are led out to form signal pins.
[0029] Figure 2The diagram illustrates the pin layout of the semiconductor power device package structure on the pad surface of this embodiment. The pad surface has sequentially adjacent first to fourth sides, with the first and third sides parallel, and the second and fourth sides parallel. The power supply pin VDD includes a VDD rectangular pad spanning the corresponding positions of the three half-bridge branches on the pad surface and six VDD edge pads located on the first side. The six VDD edge pads are connected to the VDD rectangular pad on the pad surface. The first phase voltage pin Ph1 includes a Ph1 rectangular pad and two Ph1 edge pads. The second phase voltage pin Ph2 includes a Ph2 rectangular pad and two Ph2 edge pads. The third phase voltage pin Ph3 includes a Ph3 rectangular pad and two Ph3 edge pads. The Ph1, Ph2, and Ph3 edge pads are arranged sequentially on the second side, with the two Ph1 edge pads, the two Ph2 edge pads, and the two Ph3 edge pads connected to each other on the pad surface. The Ph1, Ph2, and Ph3 rectangular pads are arranged sequentially on the side of the VDD rectangular pad closest to the third side. The drains D1 / 2 / 3 / 4 / 5 / 6 of each switch chip are electrically connected to the corresponding rectangular pads on the pad surface through the first wiring layer 2 and the substrate 1. The first ground pin GND1 includes two GND1 edge pads; the second ground pin GND2 includes two GND2 edge pads; the fourth ground pin GND4 includes two GND4 edge pads. The GND1, GND2, and GND4 edge pads are arranged sequentially on the third side, with the two GND1 edge pads interconnected on the pad surface, the two GND2 edge pads interconnected on the pad surface, and the two GND4 edge pads interconnected on the pad surface. The pads corresponding to the signal pins are arranged sequentially on the fourth side in the order of G1, G3, G5, G2, G4, and G6.
[0030] Figure 3The diagram shows the internal wiring of the semiconductor power device package structure of this embodiment. The semiconductor power device package structure also includes a substrate 1, a package body, a first wiring layer 2, a second wiring layer 3, and several vertical electrical connectors 4. The orange frame indicates the location of each switch chip. The drain D1 / 2 / 3 / 4 / 5 / 6 of each switch is located on the first surface, and the gate G1 / 2 / 3 / 4 / 5 / 6 and source S1 / 2 / 3 / 4 / 5 / 6 are located on the second surface. The first surfaces of the first to sixth switches M1 / 2 / 3 / 4 / 5 / 6 are located on the substrate 1 indicated by the gold square. The green frame indicates the first wiring layer 2, which is located on the substrate 1. The light green circle (located at the signal end) and the light green strip (located at the power path) indicate the vertical electrical connector 4, which is used to realize the vertical cross-layer electrical connection between the first wiring layer 2 and the second wiring layer 3. The black frame indicates the second wiring layer 3. The first to sixth switches M1 / 2 / 3 / 4 / 5 / 6 and the vertical electrical connector 4 are located between the first wiring layer 2 and the second wiring layer 3. The second surfaces of each switch are electrically connected to the second wiring layer 3. The package, indicated by a pink outline, covers substrate 1, each switch chip, and each wiring layer, exposing only the pins. The blue outline corresponds to... Figure 2 The pad area shown is outlined by a dashed line on the pad surface. The circuit routing of each half-bridge branch from the power supply terminal to the ground terminal is arranged as follows: First, the power supply pin VDD is electrically connected to the drain D1 / 3 / 5 of a switch on the first side through substrate 1 and the first wiring layer 2. Then, the source S1 / 3 / 5 of this switch on the second side is electrically connected to the drain D2 / 4 / 6 of another switch on the first side through the second wiring layer 3, the vertical electrical connector 4, and the first wiring layer 2. Finally, the source S2 / 4 / 6 of this switch on the second side is electrically connected to the corresponding ground terminal pin GND1 / 2 / 4 on the third side of the pad surface through the second wiring layer 3, the vertical electrical connector 4 adjacent to the third side, the first wiring layer 2, and the substrate 1. The projection of this circuit routing on the horizontal plane is the direction from the first side to the third side. The three half-bridge branches are arranged parallel to each other, therefore the equivalent R of the corresponding switches is... dson Uniform. A certain width of horizontal wiring area is left between switches M1 / 3 / 5 and switches M2 / 4 / 6 for setting up vertical electrical connectors 4 and a portion of electrical connection wiring leading to the second and fourth sides; that is, on the first wiring layer 2, the electrical connection wiring corresponding to the Ph1 edge pad is led out from the side of the second switch M2 nearby, while the electrical connection wiring corresponding to the Ph2 edge pad and the Ph3 edge pad passes through the area between the first switch M1, the third switch M3 and the vertical electrical connector 4. On the second wiring layer 3, the electrical connection wiring corresponding to each signal pin is set in the adjacent area on the side of the corresponding switch chip facing the first side, so that the direction of each horizontally led-out electrical connection wiring and the vertical circuit wiring from the power supply end to the ground end is staggered.
[0031] The semiconductor power device package structure in this embodiment has an external size of 10*10mm. In the pin arrangement of this embodiment, the circuit path of each half-bridge branch from the power supply terminal to the ground terminal is arranged along the direction from the first side to the third side of the package structure and is parallel to each other, which makes the equivalent R of each half-bridge branch equal to the grounding terminal. dson On the one hand, uniformity is achieved by providing a pair of adjacent edge pads that are connected on the pad surface for each circuit functional terminal in the grounding terminal and phase voltage terminal. This increases the soldering area and further enhances the equivalent R. dson Uniformity. On the other hand, the signal pins are set in a direction perpendicular to the power supply terminal (i.e., the direction of the fourth side), which can reduce signal coupling interference, and the circuit board layout with the package structure of this embodiment can better realize the regional division of the power module and the signal module.
[0032] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A semiconductor power device packaging structure, characterized in that, Includes a substrate, three half-bridge branches, and a package; Each of the half-bridge branches includes two switching chips connected in series; The switching chip is disposed on the substrate, and the package covers the substrate and the switching chip. The semiconductor power device package structure has a pad surface, which has a first side, a second side, a third side and a fourth side that are adjacent to each other in sequence. The first side and the third side are parallel. A power supply edge pad is provided on the first side, and a ground edge pad is provided on the third side. The half-bridge branch is connected between the power supply edge pad and the ground edge pad through a substrate. A phase voltage terminal edge pad is provided on the second side; a signal pad is provided on the fourth side; the phase voltage terminal edge pad is electrically connected to the midpoint of the half-bridge branch; the signal pad is electrically connected to the gate of the switching chip. The pad surface is also provided with rectangular pads, which include one power end rectangular pad and three phase voltage end rectangular pads; the power end edge pads and the power end rectangular pads are connected on the pad surface; the phase voltage end rectangular pad array is arranged on one side of the power end rectangular pads near the third side. Each half-bridge branch has two adjacent grounding terminal edge pads that are connected on the pad surface; Each half-bridge branch has two adjacent pads on the edge of the phase voltage terminal that are connected on the pad surface.
2. The semiconductor power device packaging structure according to claim 1, characterized in that, It also includes a first wiring layer, a second wiring layer, and vertical electrical connectors; The first wiring layer is disposed on the substrate, the switch chip and the vertical electrical connector are disposed between the first wiring layer and the second wiring layer, and the package further covers the first wiring layer, the second wiring layer and the vertical electrical connector; The switch chip has a first side and a second side, the first side is electrically connected to a first wiring layer, and the second side is electrically connected to a second wiring layer; the two ends of the vertical electrical connector are respectively electrically connected to the first wiring layer and the second wiring layer.
3. The semiconductor power device packaging structure according to claim 2, characterized in that, The vertical electrical connector includes a vertical signal electrical connector and a vertical power electrical connector; the projection shape of the vertical signal electrical connector on the pad surface is circular, and the projection shape of the vertical power electrical connector on the pad surface is elongated.
4. The semiconductor power device packaging structure according to claim 3, characterized in that, The vertical power electrical connectors are provided in six parts. A horizontal wiring area is provided between the two switching chips of each half-bridge branch. Three of the vertical power electrical connectors are located in the horizontal wiring area, and the other three of the vertical power electrical connectors are located on the third side of the package. The vertical signal electrical connectors are located on the fourth side of the package.
5. The semiconductor power device packaging structure according to claim 2, characterized in that, A lateral wiring area is provided between the two switching chips of each half-bridge branch. At least one wiring for forming an electrical connection between the phase voltage terminal edge pad and the midpoint of the half-bridge passes through the lateral wiring area, and at least one wiring for forming an electrical connection between the signal pad and the gate of the switching chip passes through the lateral wiring area.
6. The semiconductor power device packaging structure according to claim 2, characterized in that, The switching chip is a MOS switching chip; the source and gate of the switching chip are disposed on the second side, and the drain of the switching chip is disposed on the first side. The drain of each switching chip is electrically connected to a rectangular pad at a corresponding position on the pad surface through a first wiring layer and a substrate.