Aging system of three-phase brushless motor driver
By designing an aging system that includes clock and control signals, analog Hall signals, logic control, and signal acquisition modules, the reliability verification problem of high-power three-phase brushless motor drivers over a wide temperature range was solved, the steady-state life test was effectively carried out, product damage was avoided, and system maintenance was simplified.
Patent Information
- Application Number
- CN202423237681.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2034-12-26
AI Technical Summary
Existing technologies cannot effectively verify the reliability of high-power and wide-temperature-range three-phase brushless motor drivers, and cannot eliminate early-failed products.
A aging system was designed, comprising a clock and control signal generation module, an analog Hall signal generation module, a logic control module, a signal acquisition and processing module, and a load module. The system adopts a fully hardware design and uses the analog Hall signal generation module to simulate the Hall position sensor of the motor, generating six PWM control signals to achieve steady-state life test of a three-phase brushless motor driver.
It has achieved steady-state life test of a maximum 1200V/200A three-phase brushless motor driver across the entire temperature range, avoiding product damage caused by program overrun, and the modular design of the system facilitates use and maintenance.
Smart Images
Figure CN223842029U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a aging system for a three-phase brushless motor driver, and specifically to a aging system for a three-phase brushless motor driver. Background Technology
[0002] Currently, most domestic and international manufacturers of three-phase brushless motor drivers use voltage aging to achieve steady-state life aging tests for their products. For high-power products with wide temperature ranges, such as the current steady-state life aging test requirements for three-phase brushless motor drivers with a maximum voltage of 1200V / 200A across the entire temperature range (-55℃ to 125℃), this method cannot fully verify their reliability or eliminate products that may fail prematurely. Utility Model Content
[0003] The technical problem to be solved by this utility model is, in general, to provide a aging system for a three-phase brushless motor driver.
[0004] To solve the above problems, the technical solution adopted by this utility model is as follows:
[0005] A aging system for a three-phase brushless motor driver is characterized by comprising a clock and control signal generation module, an analog Hall signal generation module, a logic control module, a signal acquisition and processing module, and a load module.
[0006] The clock and control signal generation module, the analog Hall signal generation module, and the logic control module are electrically connected in sequence.
[0007] The logic control module is electrically connected to the input terminals of the clock and control signal generation module and the signal acquisition and processing module, respectively.
[0008] Furthermore, the aging system also includes a power supply;
[0009] The power supply provides power to the clock and control signal generation module, the analog Hall signal generation module, and the logic control module.
[0010] Furthermore, the output of the logic control module provides a signal to the load module of the test product;
[0011] The load module feeds back an electrical signal to the signal acquisition and processing module.
[0012] Furthermore, the signal acquisition and processing module is a current sampling circuit or a voltage sampling circuit.
[0013] Furthermore, the analog Hall signal generation module includes chips U6A, U6B, and U7A, as well as logic AND gates U8A, U8B, and U8C; among them, the clock signal is divided into three paths, which are respectively connected to pin 3 of chip U6A, pin 13 of U6B, and pin 13 of U7A.
[0014] The signal terminal HA is electrically connected to the positive output terminal 1 of chip U6B and pin 11 of chip U7A, respectively.
[0015] The signal terminal HB is electrically connected to the input terminal 6 of the logic AND gate U8B, the input terminal 5 of the chip U6B, and the positive output terminal 15 of the chip U6A, respectively.
[0016] The signal terminal HC is electrically connected to input terminal 2 of AND gate U8A, input terminal 9 of AND gate U8C, and positive output terminal 15 of chip U7A, respectively.
[0017] In chip U6B, pin 6 is connected to the output terminal 3 of AND gate U8A; pin 5 is also connected to the positive output terminal 15 of chip U6A; pins 4 and 7 are grounded; negative output terminal 2 is connected to the input terminal 5 of AND gate U8B and the negative input 8 of AND gate U8C.
[0018] In chip U6A, pin 10 is connected to the negative output terminal 14 of chip U7A; pin 11 is connected to the output terminal 10 of op-amp UBC; pins 6 and 12 are grounded; negative output terminal 14 is connected to input terminal 1 of logic AND gate U8A.
[0019] In chip U7A, pin 10 is connected to output terminal 4 of logic AND gate U8B; pins 6 and 12 are grounded.
[0020] Clock and control signal generation module, including chip U1;
[0021] In chip U1, pin 1 is grounded, pin 3 outputs the CLK clock signal; the CLK clock signal is also electrically connected to oscilloscope XSC1, pin 5 is grounded through capacitor C2, pin 2 is connected to pin 6, pin 2 is grounded through capacitor C1, resistor R3 is connected between pin 7 and pin 2, pins 8 and 4 are respectively connected to VCC; VCC is connected to pin 7 through resistor R1.
[0022] The logic control module includes logic gates U1A-U1D, U2A-U2C, U3A-U3D, and U4A-U4C.
[0023] The three analog Hall signals HB, HC, and HA are connected to one input terminal of the XOR gates U1A-U1C through resistors R4, R3, and R2 respectively. The other output terminal of the XOR gates U1A-U1C is connected to the reference signal through resistor R1.
[0024] The output terminals of XOR gates U1A-U1C are respectively electrically connected to the input terminals of NAND gates U3A, U3B, and U3D;
[0025] The output of XOR gate U1A is also electrically connected to the inputs of JK NAND gates U4C and U2C, respectively;
[0026] The output of XOR gate U1B is also electrically connected to the inputs of NAND gates U2A and U4B, respectively;
[0027] The output of the XOR gate U1C is also electrically connected to the inputs of the NAND gates U2B and U4A, respectively;
[0028] The outputs of NAND gates U3A, U3B, and U3D are electrically connected to the inputs of NAND gates U2A, U2B, and U2C, respectively.
[0029] NAND gates U2A, U2B, and U2C output PWM control signals for the high end of PWM phase B, the high end of PWM phase C, and the high end of PWM phase A, respectively.
[0030] The outputs of NAND gates U3A, U3B, and U3D are also connected to the inputs of NAND gates U4A, U4B, and U4C, respectively.
[0031] The signal acquisition and processing module adopts an overcurrent feedback control signal circuit; the overcurrent feedback control signal circuit includes NOT gates U5A and U5B;
[0032] The signal OC connected to the load module outputs the enable signal EN through NOT gates U5A and U5B; the enable signal EN and PWM are connected to the input of XOR gate U1D through NAND gate U3C; the output of XOR gate U1D is connected to one input of NAND gates U2A-U2C respectively.
[0033] JK NAND gates U4A, U4B, and U4C output PWM control signals at the low end of PWM phase A, the low end of PWM phase C, and the low end of PWM phase B, respectively.
[0034] The load module uses resistors;
[0035] The test product was a three-phase brushless motor driver.
[0036] U1 is an LM555 circuit, and U6A, U6B, and U7A are JK flip-flops;
[0037] U8A, U8B, and U8C are logic AND gates;
[0038] U1A, U1B, U1C, and U1D are logic XOR gates;
[0039] U2A, U2B, U2C, U4A, U4B, and U4C are 3-input logic NAND gates;
[0040] U3A, U3B, U3C, and U3D are logic NAND gates;
[0041] U5A and U5B are logic NOT gates.
[0042] A aging method for a three-phase brushless motor driver, using the system described above, involves performing the following steps;
[0043] S1 powers on and verifies the clock and control signal generation module, the analog Hall signal generation module, and the logic control module, and then powers off after verification is complete.
[0044] S2, Install the driver for the three-phase brushless motor to be aged;
[0045] S3, set the aging parameters according to the preset technical requirements;
[0046] S3, power-on test.
[0047] S4. First, the clock and control signal generation module generates a 1kHz square wave, which is sent to the analog Hall signal generation module as the clock signal CLK. Then, the analog Hall signal generation module generates analog Hall signals through logic transformation, and the analog Hall signals act on the logic control module to generate six-channel PWM commutation signals. Second, the six-channel PWM commutation signals are output to the three-phase brushless motor driver. Third, the signal acquisition and processing module acquires and processes the real-time status of the test product and feeds it back to the logic control module.
[0048] This invention employs a fully hardware design, eliminating the risk of product burnout due to program malfunctions caused by various factors. It can meet the steady-state lifespan aging test requirements for three-phase brushless motor drivers with a maximum voltage of 1200V / 200A across the entire temperature range (-55℃ to 125℃), and its modular design facilitates use and maintenance.
[0049] This utility model is reasonably designed, low in cost, sturdy and durable, safe and reliable, simple to operate, time-saving and labor-saving, cost-saving, compact in structure and easy to use. Attached Figure Description
[0050] Figure 1 This is the circuit schematic diagram of this utility model.
[0051] Figure 2 This is a schematic diagram of the analog Hall signal generation module of this utility model.
[0052] Figure 3 This is a circuit diagram of the clock signal generation circuit of this utility model.
[0053] Figure 4 This is a circuit diagram of the logic control module of this utility model.
[0054] Figure 5 The logic flowchart of this utility model. Detailed Implementation
[0055] like Figure 1-5This utility model adopts a modular design, including a clock and control signal generation module, an analog Hall signal generation module, a logic control module, a signal acquisition and processing module, and a power supply and load module;
[0056] The power supply is used to provide power to the clock and control signal generation module, the analog Hall signal generation module, and the logic control module respectively.
[0057] The clock and control signal generation module, the analog Hall signal generation module, and the logic control module are electrically connected in sequence.
[0058] The logic control module is electrically connected to the input terminals of the clock and control signal generation module and the signal acquisition and processing module, respectively.
[0059] The logic control module outputs a signal to the load module of the test product.
[0060] The load module feeds back an electrical signal to the signal acquisition and processing module;
[0061] This invention generates six PWM control signals through a clock generation module, an analog Hall signal generation module, and a logic control module. The signal acquisition and processing module acquires and processes the real-time status of the test product and implements protection functions through the logic control module. The power supply and load module provides power and load to the system.
[0062] The simulated Hall signal generation module uses pure hardware to implement cyclic simulated Hall signals, which can mimic the Hall position sensor of a motor to achieve simulation control of the test product. It does not have the problem of magnetic components failing when the Curie point is exceeded at high temperatures.
[0063] The clock and control signal generation module, analog Hall signal generation module, logic control module, and signal acquisition and processing module are all designed with pure hardware to meet the steady-state life aging test requirements of three-phase brushless motor drivers with a maximum voltage of 1200V / 200A within the full temperature range (-55℃ to 125℃). The modular design facilitates use and maintenance.
[0064] As a specific circuit description, the analog Hall signal generation module includes chips U6A, U6B, and U7A, as well as logic AND gates U8A, U8B, and U8C; among them, the clock signal is divided into three paths, which are respectively connected to pin 3 of chip U6A, pin 13 of U6B, and pin 13 of U7A.
[0065] The signal terminal HA is electrically connected to the positive output terminal 1 of chip U6B and pin 11 of chip U7A, respectively.
[0066] The signal terminal HB is electrically connected to the input terminal 6 of the logic AND gate U8B, the input terminal 5 of the chip U6B, and the positive output terminal 15 of the chip U6A, respectively.
[0067] The signal terminal HC is electrically connected to input terminal 2 of AND gate U8A, input terminal 9 of AND gate U8C, and positive output terminal 15 of chip U7A, respectively.
[0068] In chip U6B, pin 6 is connected to the output terminal 3 of AND gate U8A; pin 5 is also connected to the positive output terminal 15 of chip U6A; pins 4 and 7 are grounded; negative output terminal 2 is connected to the input terminal 5 of AND gate U8B and the negative input 8 of AND gate U8C.
[0069] In chip U6A, pin 10 is connected to the negative output terminal 14 of chip U7A; pin 11 is connected to the output terminal 10 of op-amp UBC; pins 6 and 12 are grounded; negative output terminal 14 is connected to input terminal 1 of logic AND gate U8A.
[0070] In chip U7A, pin 10 is connected to output terminal 4 of logic AND gate U8B; pins 6 and 12 are grounded.
[0071] The clock and control signal generation module outputs the CLK clock signal;
[0072] The logic control module uses a PLC, which is connected to the signal terminals HA, HB, and HC respectively.
[0073] The signal acquisition and processing module can be a current sampling or voltage sampling module in a conventional circuit.
[0074] like Figure 4 This invention generates six PWM control signals through a clock generation module, an analog Hall effect signal generation module, and a logic control module, which are then output to a three-phase brushless motor driver. The signal acquisition and processing module collects and processes the real-time status of the test product, and the logic control module provides protection functions. The power supply and load module provides power and load to the system.
[0075] When an analog signal is generated, the chips in the analog Hall signal generation module operate according to the logical relationship of the three equations above.
[0076] When the analog Hall signal generator module is working, it receives the CLK clock signal and generates timing signals through logic transformation. It has a self-starting function and can run in a loop from sequence 1 to sequence 6.
[0077] The working principle of this utility model:
[0078] The clock and control signal generation module generates a 1kHz square wave, which is applied to the analog Hall signal generation module as the clock signal CLK. Then, a control signal is generated, which is applied to the logic control module to control the start and stop of the entire system.
[0079] The analog Hall signal generation module generates analog Hall signals through logic transformation, which are then applied to the logic control module to generate six-channel PWM commutation signals.
[0080] The logic control module generates six PWM commutation signals to control the operation of the three-phase brushless motor driver, and receives over-temperature and overload signals generated by the signal acquisition and processing module to control the system status.
[0081] The power module provides both weak and strong electrical signals to the entire system.
[0082] The load module provides a resistive load that meets specifications for the operation of the three-phase brushless motor driver.
[0083] like Figure 1-5 The experimental steps of this utility model are as follows:
[0084] S1. Power on and verify the control module, including the clock and control signal generation module, the analog Hall signal generation module, and the logic control module. Power off after verification.
[0085] S2. Install the driver for the three-phase brushless motor to be aged;
[0086] S3. Set the aging parameters according to the preset technical requirements;
[0087] S3. Power on the control module;
[0088] S4, Power-on module.
[0089] This utility model is described in detail for the purpose of making the disclosure clearer, and the prior art will not be listed one by one.
[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. It is obvious to those skilled in the art that multiple technical solutions of this utility model can be combined. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model. All technical contents not described in detail in this utility model are publicly known technologies.
Claims
1. A aging system for a three-phase brushless motor driver, characterized in that: It includes a clock and control signal generation module, an analog Hall signal generation module, a logic control module, a signal acquisition and processing module, and a load module; The clock and control signal generation module, the analog Hall signal generation module, and the logic control module are electrically connected in sequence. The logic control module is electrically connected to the input terminals of the clock and control signal generation module and the signal acquisition and processing module, respectively.
2. The aging system for a three-phase brushless motor driver according to claim 1, characterized in that: The aging system also includes a power supply; The power supply provides power to the clock and control signal generation module, the analog Hall signal generation module, and the logic control module.
3. The aging system for a three-phase brushless motor driver according to claim 1, characterized in that: The logic control module outputs a signal to the load module of the test product. The load module feeds back an electrical signal to the signal acquisition and processing module.
4. The aging system for a three-phase brushless motor driver according to claim 1, characterized in that: The signal acquisition and processing module is either a current sampling circuit or a voltage sampling circuit.
5. The aging system for a three-phase brushless motor driver according to claim 1, characterized in that: The analog Hall signal generation module includes chips U6A, U6B, and U7A, as well as logic AND gates U8A, U8B, and U8C. The clock signal is divided into three paths, which are connected to pin 3 of chip U6A, pin 13 of U6B, and pin 13 of U7A, respectively. The signal terminal HA is electrically connected to the positive output terminal 1 of chip U6B and pin 11 of chip U7A, respectively. The signal terminal HB is electrically connected to the input terminal 6 of the logic AND gate U8B, the input terminal 5 of the chip U6B, and the positive output terminal 15 of the chip U6A, respectively. The signal terminal HC is electrically connected to input terminal 2 of AND gate U8A, input terminal 9 of AND gate U8C, and positive output terminal 15 of chip U7A, respectively. In chip U6B, pin 6 is connected to the output terminal 3 of AND gate U8A; pin 5 is also connected to the positive output terminal 15 of chip U6A; pins 4 and 7 are grounded; negative output terminal 2 is connected to the input terminal 5 of AND gate U8B and the negative input 8 of AND gate U8C. In chip U6A, pin 10 is connected to the negative output terminal 14 of chip U7A; pin 11 is connected to the output terminal 10 of op-amp UBC; pins 6 and 12 are grounded; negative output terminal 14 is connected to input terminal 1 of logic AND gate U8A. In chip U7A, pin 10 is connected to output terminal 4 of logic AND gate U8B; pins 6 and 12 are grounded.