Array substrate and display device

Abstract

The utility model provides a display device and an array substrate thereof. The array substrate comprises: a substrate; the plurality of grid lines and the plurality of data lines are arranged on the substrate, the plurality of grid lines and the plurality of data lines intersect to define a plurality of sub-pixels, and a common electrode lead is arranged between each grid line and any row of sub-pixels adjacent to the grid line; the plurality of common electrodes are arranged on the substrate base plate and are arranged in the sub-pixels; each common electrode lead is connected with each common electrode in the sub-pixels in the same row, and each common electrode in the sub-pixels in the same row is connected with two common electrode leads on the two sides in the column direction of the sub-pixels in the row respectively.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are now widely used. Typically, the array substrate, as the core component of an LCD, integrates thin-film transistors, gate lines, data lines, pixel electrodes, common electrodes, and common electrode leads. Light leakage is a common problem in LCDs, primarily caused by light leakage around the pixel area.

[0003] To prevent light leakage, liquid crystal displays (LCDs) incorporate a black matrix. This black matrix forms a light-blocking structure around the pixel areas, effectively preventing unwanted light transmission caused by light leakage. Therefore, LCDs with a larger black matrix area can better prevent light leakage. However, using a larger black matrix area reduces the aperture ratio of the LCD, thus affecting the brightness and color performance of the display. Utility Model Content

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and proposes an array substrate and display device that can form a light-shielding structure around the pixel area to block the propagation of unwanted light while reducing the area of ​​the black matrix, thereby improving the aperture ratio of the display device.

[0005] To achieve the above objectives, embodiments of this disclosure provide an array substrate, comprising:

[0006] Substrate;

[0007] Multiple gate lines and multiple data lines are disposed on the substrate. The multiple gate lines and multiple data lines intersect to define multiple sub-pixels. Each gate line and any row of sub-pixels adjacent to it have a common electrode lead.

[0008] Multiple common electrodes are disposed on the substrate and within the sub-pixels; each common electrode lead is connected to each common electrode in the same row of the sub-pixels, and each common electrode in the same row of the sub-pixels is connected to two common electrode leads on both sides along the column direction of the row of the sub-pixels.

[0009] Optionally, the common electrode lead is disposed in the same layer as the gate line.

[0010] Optionally, each of the common electrode leads is disposed on a different layer from each of the common electrodes in the same row of the sub-pixels, and is electrically connected through a first via.

[0011] Optionally, the common electrodes in two adjacent rows of sub-pixels are electrically connected one-to-one via connecting lines;

[0012] The connecting line extends along the column direction of the sub-pixel; the common electrode in each of the two adjacent rows of the sub-pixels is disposed on a different layer from the connecting line and is electrically connected to the connecting line through a second via.

[0013] Optionally, the array substrate further includes a pixel electrode, which is disposed on the substrate and within the sub-pixel;

[0014] The connecting line is disposed on the same layer as the pixel electrode.

[0015] Optionally, the orthographic projection of the common electrode lead on the array substrate overlaps with the orthographic projection of the pixel electrode disposed in the same sub-pixel on the array substrate.

[0016] Optionally, the array substrate further includes a common electrode edge lead disposed in the non-display area, wherein the common electrode edge lead and the common electrode lead are disposed on the same layer in the non-display area and are electrically connected.

[0017] Optionally, the array substrate further includes a gate driving circuit disposed in the non-display area, and the gate driving circuit is connected to the plurality of gate lines in the non-display area through a via.

[0018] There is a gap between the edge lead of the common electrode and the adapter via.

[0019] Optionally, the array substrate further includes: a plurality of data line terminals for connection to a flexible circuit board, and the plurality of data line terminals are electrically connected to the data lines;

[0020] The plurality of data line terminals are at a predetermined distance from the edge of the adjacent array substrate.

[0021] Optionally, the plurality of data line terminals include a first data line terminal and a second data line terminal, wherein the first data line terminal is electrically connected to each of the data lines with odd serial numbers, and the second data line terminal is electrically connected to each of the data lines with even serial numbers.

[0022] Optionally, the plurality of data line terminals include a first data line terminal, a second data line terminal, a third data line terminal, a fourth data line terminal, a fifth data line terminal, and a sixth data line terminal. The first data line terminal is electrically connected to the data lines with odd numbers corresponding to red sub-pixels; the second data line terminal is electrically connected to the data lines with odd numbers corresponding to green sub-pixels; the third data line terminal is electrically connected to the data lines with odd numbers corresponding to blue sub-pixels; the fourth data line terminal is electrically connected to the data lines with even numbers corresponding to red sub-pixels; the fifth data line terminal is electrically connected to the data lines with even numbers corresponding to green sub-pixels; and the sixth data line terminal is electrically connected to the data lines with even numbers corresponding to blue sub-pixels.

[0023] Optionally, the array substrate further includes multiple test signal lines disposed in the non-display area, each test signal line being connected to a corresponding data line terminal, and the other end of each test signal line extending to one of the four corner regions of the non-display area.

[0024] Optionally, the array substrate further includes:

[0025] A pixel electrode, wherein the pixel electrode is disposed on the substrate and within the sub-pixel;

[0026] Multiple test signal lead-out terminals are disposed on the same layer as the pixel electrode and are connected to multiple test signal lines through a third via.

[0027] Optionally, the preset distance is greater than or equal to 200 μm.

[0028] Optionally, each of the common electrode leads includes a first lead segment that overlaps with the data line and a second lead segment that does not overlap with the data line, wherein the line width of the first lead segment is smaller than the line width of the second lead segment.

[0029] On the other hand, this disclosure provides a display device including the array substrate described above. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of an array substrate provided in some embodiments of this disclosure;

[0031] Figure 2 A simulated inverse color map of light leakage on an array substrate of the prior art;

[0032] Figure 3 This is a simulated inverse color map of light leakage from an array substrate provided in some embodiments of this disclosure;

[0033] Figure 4A plan view of the circuit layout in a local area of ​​an array substrate provided in an embodiment of this disclosure;

[0034] Figure 5 For along Figure 4 A sectional view of line A-A' in the middle;

[0035] Figure 6 For along Figure 4 A sectional view of line B-B' in the middle;

[0036] Figure 7 A plan view of the circuit layout in a local area of ​​an array substrate provided in an embodiment of this disclosure;

[0037] Figure 8 A plan view of the circuit layout in a local area of ​​an array substrate provided in an embodiment of this disclosure;

[0038] Figure 9 This is a schematic diagram of the region division of the array substrate provided in some embodiments of this disclosure;

[0039] Figure 10 This is a schematic diagram of the region division of the array substrate provided in some embodiments of this disclosure;

[0040] Figure 11 This is a partial schematic diagram of the region division of the array substrate provided in some embodiments of this disclosure;

[0041] Figure 12 This is a partial schematic diagram showing the connection relationship between the data line terminals of the test signal lines of the array substrate and the corresponding data lines and test signal lines in some embodiments of this disclosure;

[0042] Figure 13 This is a schematic diagram of the region division of the array substrate provided in some embodiments of this disclosure;

[0043] Figure 14 This is a partial structural diagram of the peripheral area and display area of ​​the display substrate provided in some embodiments of this disclosure;

[0044] Figure 15 This is a schematic diagram of a display device provided in some embodiments of the present disclosure. Detailed Implementation

[0045] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0048] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0049] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] In this embodiment of the disclosure, the first direction X, the second direction Y, and the third direction Z intersect each other. In this disclosure, the first direction X and the second direction Y are perpendicular to each other in the plane of the base, the first direction X is a horizontal direction (i.e., the row direction, or the extension direction of the gate line), the second direction Y is a vertical direction (i.e., the column direction, or the extension direction of the data line), and the third direction Z is a vertical direction that is perpendicular to the plane of the base. However, this does not constitute a limitation on this disclosure.

[0051] In the embodiments of this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then formed in a single patterning process using the same photomask. Depending on the specific pattern, the sequential patterning process may include multiple exposure, development, or etching processes, and the specific pattern formed in the same layer may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses. It should be understood that when a layer or element is referred to as being on another layer or substrate, it may mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0052] Before describing the specific structure of the array substrate disclosed herein, the application scenarios and circuit structure of the array substrate provided herein will be explained in detail. The array substrate disclosed herein is used in liquid crystal displays, that is, it is a liquid crystal array substrate.

[0053] like Figure 1 and Figure 4 As shown, this embodiment of the present disclosure provides an array substrate 1. The array substrate 1 includes a substrate 10, a plurality of gate lines 20, a plurality of data lines 30, and a plurality of common electrodes 70. The plurality of gate lines 20 and the plurality of data lines 30 are disposed on the substrate 10. The plurality of gate lines 20 and the plurality of data lines 30 intersect to define a plurality of sub-pixels 50. The plurality of sub-pixels 50 are arranged in an array. Each gate line 20 and any adjacent row of sub-pixels 50 have a common electrode lead 60. In other words, each gate line 20 and another adjacent gate line 20 have two common electrode leads 60, and a row of sub-pixels 50 is formed between the two common electrode leads 60. The plurality of common electrodes 70 are disposed on the substrate 10 and within the sub-pixels 50. Each common electrode lead 60 is connected to each common electrode 70 within the same row of sub-pixels 50, and each common electrode 70 within the same row of sub-pixels 50 is connected to two common electrode leads 60 on each side along the column direction of that row of sub-pixels 50. In other words, for each sub-pixel 50, the two adjacent common electrode leads 60 can be connected to the common electrodes 70 of that sub-pixel 50.

[0054] To prevent the light leakage area from affecting the actual display effect, the black matrix on the substrate needs to block the light leakage area. Specifically, a black matrix is ​​provided on the substrate, which includes multiple light-shielding strips. The orthogonal projection of a portion of the light-shielding strips on the substrate 10 covers the orthogonal projection of the gate line 20 on the substrate 10; the orthogonal projection of another portion of the light-shielding strips on the substrate 10 covers the orthogonal projection of the data line 30 on the substrate 10.

[0055] Existing technologies typically employ increasing the width of the light-shielding strips in the black matrix to prevent light leakage. In contrast, the array substrate 1 of this disclosure, by providing common electrode leads 60 on both sides of the sub-pixels 50 in the same row, can block the light leakage area between the gate line 20 and the sub-pixels 50, reducing the width requirement of the light-shielding strips for blocking and increasing the pixel aperture ratio. At the same time, by providing two common electrode leads 60, the overall conductivity of the common electrode 70 can be improved.

[0056] Figure 2 This is a simulated inverse color map of light leakage on an array substrate using existing technology. Figure 3 This is a simulated inverse color map of light leakage from an array substrate provided in some embodiments of this disclosure. For example... Figure 2 As shown, in the prior art, no common electrode lead is provided between one side of the sub-pixel of the array substrate and the gate line GL. In this case, the width a1 of the light leakage region in this part is approximately 10 μm. In comparison, as... Figure 3 As shown, in some embodiments, the array substrate 1 provides an additional common electrode lead 60, which blocks a portion of the light leakage between the gate line 20 and the sub-pixel 50. This reduces the width a2 of the light leakage region to approximately 5 μm compared to the width a1 in the prior art. Based on this, the width of the first light-shielding strip can be significantly reduced, thereby improving the pixel aperture ratio.

[0057] Figure 5 For along Figure 4 A cross-sectional view of line A-A' in the middle. Figure 6 For along Figure 4 A sectional view along line B-B'. (See example...) Figure 5 As shown, the common electrode lead 60 and the gate line 20 can be arranged on the same layer. By arranging the common electrode lead 60 and the gate line 20 on the same layer, the number of process steps can be reduced, and the production complexity and manufacturing cost can be lowered. At the same time, arranging the common electrode lead 60 and the gate line 20 on the same layer can avoid occupying additional space in the display area. While increasing the coverage of the common electrode lead 60 to reduce resistance, the aperture ratio of the pixels is not reduced as a result.

[0058] In some embodiments, such as Figure 5As shown, each common electrode lead 60 and each common electrode 70 within the same row of sub-pixels 50 can be arranged in different layers, and as... Figure 7 As shown, the common electrode lead 60 is electrically connected to the corresponding common electrode 70 through the first via V1. In this embodiment, the array substrate 1 sets each common electrode lead 60 and each common electrode 70 in the same row of sub-pixels 50 in a different layer, and realizes the electrical connection between the two through the first via V1. This avoids complex wiring on the same layer, simplifies the process flow, reduces the probability of defects such as short circuits and open circuits during production, improves product yield, and at the same time makes the wiring plan more reasonable, further improving space utilization and greatly alleviating the wiring congestion problem that may occur when more common electrode leads 60 are introduced.

[0059] In some embodiments, such as Figure 6 As shown, the common electrodes 70 within adjacent rows of sub-pixels 50 can be electrically connected one-to-one via connecting lines 80. The connecting lines 80 can extend along the column direction of the sub-pixels 50. Figure 7 As shown, the common electrodes 70 and connecting lines 80 within adjacent rows of sub-pixels 50 are disposed on different layers and are electrically connected to the connecting lines 80 through the second via V2. Similarly, the array substrate 1 in this embodiment adopts a different layer arrangement, which avoids complex wiring on the same layer and further improves space utilization.

[0060] In some embodiments, such as he1, Figures 4 to 6 As shown, the array substrate 1 may further include a pixel electrode 90. The pixel electrode 90 is disposed on the substrate 10 and within the sub-pixel 50. The connecting line 80 is disposed on the same layer as the pixel electrode 90. In this embodiment, the connecting line 80 of the array substrate 1 can avoid occupying additional pixel aperture areas, achieving a compact design of the signal transmission path while maintaining the pixel aperture ratio.

[0061] In some embodiments, such as Figure 1 and Figure 4 As shown, the orthographic projection of the common electrode lead 60 on the array substrate 1 overlaps with the orthographic projection of the pixel electrode 90 disposed in the same sub-pixel on the array substrate 1.

[0062] In some embodiments, such as Figures 9 to 11 and Figure 13 As shown, the array substrate 1 has a display area AA and a non-display area BB surrounding the display area AA. The display area AA refers to the area of ​​the array substrate 1 where the actual image is displayed. The non-display area BB refers to the area of ​​the array substrate 1 containing various circuits and traces used to send signals to pixels (e.g., sub-pixels). Sub-pixels 50 are all located in the display area AA. In some embodiments, such as Figure 9 and Figure 10As shown, the array substrate 1 may further include a common electrode edge lead 100 disposed within the non-display area BB. The common electrode edge lead 100 and the common electrode lead 60 are disposed in the same layer within the non-display area BB and are electrically connected. In this embodiment, the array substrate 1 integrates the common electrode edge lead 100 within the non-display area BB and the common electrode lead 60 of the display area AA within the same conductive layer, thereby optimizing the signal transmission path, reducing the impedance of the common electrode, improving the voltage uniformity of the display panel, and reducing problems such as screen flicker or uneven brightness. Simultaneously, this design eliminates the need for additional film layers or process steps, simplifying the manufacturing process and reducing production costs. The common electrode edge lead 100, disposed within the non-display area BB, can fully utilize the bezel space for signal routing, avoiding any impact on the aperture ratio of the display area AA, thus contributing to a narrower bezel design. This structure also enhances the current carrying capacity of the common electrode, improving the stability and reliability of the display device.

[0063] In some embodiments, such as Figure 8 As shown, the array substrate 1 may further include a gate driving circuit GOA disposed within the non-display area BB. The gate driving circuit GOA and multiple gate lines 20 are connected within the non-display area BB via a transition via SV. There is a gap SP between the common electrode edge lead 100 and the transition via SV.

[0064] In some embodiments, such as Figures 9 to 13 As shown, the array substrate 1 may further include multiple data line terminals 210. The multiple data line terminals 210 are used for connection to a flexible circuit board, and are electrically connected to data lines 30. The multiple data line terminals 210 have a predetermined distance h1 from the edge S of the adjacent array substrate 1. In some embodiments, the predetermined distance h1 may be greater than or equal to 200 μm. In the prior art, data line terminals typically extend to the edge of the array substrate, and static electricity from the external environment can easily be conducted to the interior of the array substrate through the metal residue at the data line terminals. The introduction of static electricity often causes the data line terminals to burn out, which severely affects the display effect and reduces product performance and user experience. In comparison, the array substrate 1 of this embodiment can enhance its anti-static capability.

[0065] In some embodiments, such as Figure 1 As shown, each common electrode lead 60 may include a first lead segment 62 that overlaps with the data line 30, and a second lead segment 64 that does not overlap with the data line 30. The line width of the first lead segment is smaller than the line width of the second lead segment. Therefore, the array substrate 1 of this embodiment can ensure that even when the number of common electrode leads 60 increases, the overlap area between the common electrode leads 60 and the data line 30 is reduced, so that the parasitic capacitance Cdc between the common electrode leads 60 and the data line 30 does not increase.

[0066] In some embodiments, such as Figure 9 As shown, the multiple data line terminals 210 may include a first data line terminal 211 and a second data line terminal 212. The first data line terminal 211 is electrically connected to each odd-numbered data line DO. The second data line terminal 212 is electrically connected to each even-numbered data line DE. By connecting the odd and even data lines in groups independently, physically isolated transmission channels can be formed, thereby reducing crosstalk between adjacent data lines and improving signal transmission stability.

[0067] In some embodiments, such as Figures 10 to 13 As shown, the multiple data line terminals 210 may include a first data line terminal 221, a second data line terminal 222, a third data line terminal 223, a fourth data line terminal 224, a fifth data line terminal 225, and a sixth data line terminal 226. The first data line terminal 221 is electrically connected to the data lines DRO corresponding to odd-numbered red sub-pixels. The second data line terminal 222 is electrically connected to the data lines DGO corresponding to odd-numbered green sub-pixels. The third data line terminal 223 is electrically connected to the data lines DBO corresponding to odd-numbered blue sub-pixels. The fourth data line terminal 224 is electrically connected to the data lines DRE corresponding to even-numbered red sub-pixels. The fifth data line terminal 225 is electrically connected to the data lines DGE corresponding to even-numbered green sub-pixels. The sixth data line terminal 226 is electrically connected to the data lines DBE corresponding to even-numbered blue sub-pixels. By connecting the red, green, and blue primary color data lines to the odd and even data line terminals respectively, a transmission channel segmented by color gamut is formed, reducing signal crosstalk between different color sub-pixels. For example, the red data lines DRO and DRE are transmitted through the first data line terminal 221 and the fourth data line terminal 224, avoiding the impact of electromagnetic coupling generated by the high-frequency driving of green sub-pixels on the red channel. During testing, pixels of the red, green, and blue primary colors can be tested separately, such as detecting pure colors of red, green, and blue, improving image detection efficiency.

[0068] In some embodiments, such as Figures 9 to 13As shown, the array substrate 1 may further include multiple test signal lines 300 disposed within the non-display area BB, each test signal line 300 being connected to a corresponding data line terminal 210. The other end of each test signal line 300 extends to one of the four corner areas CC of the non-display area BB. Through the above arrangement, the array substrate 1 of this embodiment can centrally arrange the test signal lines 300 in the corner area CC of the non-display area BB, significantly optimizing wiring space utilization and reducing interference from test signal lines to other functional lines. Simultaneously, this centralized wiring design facilitates unified routing during the array substrate testing phase, improving testing efficiency and reducing testing complexity. Furthermore, extending the test signal lines 300 to the corner area CC ensures that after the array substrate 1 is cut, the terminals used for test signal routing (e.g., the test signal routing terminals 310 described below) will only remain in the corner area CC, thus not affecting the display area AA. Simultaneously, after testing, the test signal lines 300 between adjacent data line terminals 210 are cut off, ensuring that the data line terminals are no longer connected to each other, thus guaranteeing normal display.

[0069] In some embodiments, such as Figure 14 As shown, the array substrate 1 may further include multiple test signal output terminals 310. These multiple test signal output terminals 310 are disposed on the same layer as the pixel electrode 90 and connected to multiple test signal lines 300 via a third via V3. By disposing the test signal output terminals 310 on the same layer as the pixel electrode 90 in this embodiment, the array substrate 1 simplifies the manufacturing process, reduces additional mask and etching steps, thereby lowering production costs and improving production efficiency. Simultaneously, utilizing the third via V3 to connect the test signal output terminals 310 to the test signal lines 300 improves the reliability of test signal transmission. Furthermore, this structural design optimizes wiring space, avoids occupying additional film layers, facilitates a narrow bezel design, and enhances the overall integration of the array substrate.

[0070] like Figure 15 As shown, this disclosure also provides a display device 400, including an array substrate 1. In some embodiments, the display device 400 includes a cell substrate 500, with the array substrate 1 and the cell substrate 500 disposed opposite to each other. The display device 400 may further include a liquid crystal layer 600 located between the array substrate 1 and the cell substrate 500. The cell substrate 500 may specifically be a color filter substrate, which includes a color filter layer and a black matrix 520 disposed on a substrate 510. The black matrix 520 includes a plurality of light-shielding strips to cover the orthogonal projections of devices such as gate lines 20, data lines 30, common electrode leads 60, and connection lines 80 onto the substrate 10.

[0071] In some embodiments, the display device 400 may be a curved display device.

[0072] In some embodiments, the display device 400 can be used in any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0073] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0074] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple gate lines and multiple data lines are disposed on the substrate. The multiple gate lines and multiple data lines intersect to define multiple sub-pixels. Each gate line and any row of sub-pixels adjacent to it have a common electrode lead. Multiple common electrodes are disposed on the substrate and within the sub-pixels; each common electrode lead is connected to each common electrode in the same row of the sub-pixels, and each common electrode in the same row of the sub-pixels is connected to two common electrode leads on both sides along the column direction of the row of the sub-pixels.

2. The array substrate according to claim 1, characterized in that, The common electrode lead is disposed in the same layer as the gate line.

3. The array substrate according to claim 2, characterized in that, Each of the common electrode leads is disposed on a different layer from each of the common electrodes in the same row of the sub-pixels, and is electrically connected through a first via.

4. The array substrate according to claim 3, characterized in that, Each common electrode in an adjacent row of sub-pixels is electrically connected via a connecting line. The connecting line extends along the column direction of the sub-pixel; the common electrode in each of the two adjacent rows of the sub-pixels is disposed on a different layer from the connecting line and is electrically connected to the connecting line through a second via.

5. The array substrate according to claim 4, characterized in that, It also includes a pixel electrode, which is disposed on the substrate and within the sub-pixel; The connecting line is disposed on the same layer as the pixel electrode.

6. The array substrate according to claim 5, characterized in that, The orthogonal projection of the common electrode lead on the array substrate overlaps with the orthogonal projection of the pixel electrode disposed in the same sub-pixel on the array substrate.

7. The array substrate according to claim 3, characterized in that, It also includes a common electrode edge lead disposed in the non-display area, wherein the common electrode edge lead and the common electrode lead are disposed in the same layer in the non-display area and are electrically connected.

8. The array substrate according to claim 7, characterized in that, It also includes a gate driving circuit disposed in the non-display area, the gate driving circuit being connected to the plurality of gate lines in the non-display area via a via; There is a gap between the edge lead of the common electrode and the adapter via.

9. The array substrate according to claim 1, characterized in that, Also includes: Multiple data line terminals are provided for connection to a flexible circuit board, and the multiple data line terminals are electrically connected to the data lines. The plurality of data line terminals are at a predetermined distance from the edge of the adjacent array substrate.

10. The array substrate according to claim 9, characterized in that, The plurality of data line terminals include a first data line terminal and a second data line terminal, wherein the first data line terminal is electrically connected to each of the data lines with odd serial numbers, and the second data line terminal is electrically connected to each of the data lines with even serial numbers.

11. The array substrate according to claim 9, characterized in that, The plurality of data line terminals include a first data line terminal, a second data line terminal, a third data line terminal, a fourth data line terminal, a fifth data line terminal, and a sixth data line terminal. The first data line terminal is electrically connected to the data lines with odd numbers corresponding to red sub-pixels. The second data line terminal is electrically connected to the data lines with odd numbers corresponding to green sub-pixels. The third data line terminal is electrically connected to the data lines with odd numbers corresponding to blue sub-pixels. The fourth data line terminal is electrically connected to the data lines with even numbers corresponding to red sub-pixels. The fifth data line terminal is electrically connected to the data lines with even numbers corresponding to green sub-pixels. The sixth data line terminal is electrically connected to the data lines with even numbers corresponding to blue sub-pixels.

12. The array substrate according to any one of claims 9 to 11, characterized in that, It also includes multiple test signal lines disposed in the non-display area, each of the test signal lines being connected to the corresponding data line terminal, and the other end of each of the test signal lines extending to one of the four corner areas of the non-display area.

13. The array substrate according to claim 12, characterized in that, Also includes: A pixel electrode, wherein the pixel electrode is disposed on the substrate and within the sub-pixel; Multiple test signal lead-out terminals are disposed on the same layer as the pixel electrode and are connected to multiple test signal lines through a third via.

14. The array substrate according to any one of claims 9 to 11, characterized in that, The preset distance is greater than or equal to 200μm.

15. The array substrate according to claim 1, characterized in that, Each of the common electrode leads includes a first lead segment that overlaps with the data line and a second lead segment that does not overlap with the data line, wherein the line width of the first lead segment is smaller than the line width of the second lead segment.

16. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 15.

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