Backboard, electronic paper display panel and display device
By setting a smaller second sub-pixel electrode near the non-linear boundary area of the electronic paper display panel and adjusting the wiring of the driving layer, the problem of jagged edges in the non-linear boundary area display was solved, thereby improving the display effect and increasing the effective display area.
Patent Information
- Application Number
- CN202520576374.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-03-28
AI Technical Summary
In existing e-paper display panels, jagged edges are visible near the non-linear boundary areas, resulting in poor display quality and the bezels cannot be effectively reduced.
A smaller second sub-pixel electrode is set near the nonlinear boundary region. By adjusting the wiring of the driving layer, the second sub-pixel electrode with a smaller projected area is used to fill the omitted area of the nonlinear boundary region. The corresponding driving control is achieved by adjusting the driving signal, which reduces jagged edges, improves the display effect, and increases the effective display area.
It effectively reduces jagged edges near nonlinear boundary areas, improves display quality, and increases the effective display area.
Smart Images
Figure CN223842293U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to a backplane, an electronic paper display panel, and a display device. Background Technology
[0002] Electronic paper display (EPD) is a display technology that mimics the visual characteristics of traditional paper, featuring low power consumption, high contrast, and excellent readability even in sunlight. It is widely used in e-book readers (such as Kindle), electronic tags, smartwatches, and other fields. Utility Model Content
[0003] In view of this, the purpose of this disclosure is to provide a backplane, an electronic paper display panel, and a display device.
[0004] For the purposes described above, this disclosure provides a backplate; the backplate includes a display area, a non-display area, and a non-linear boundary area located between the two;
[0005] The backplate includes a substrate, a driving layer, and a pixel electrode layer stacked together.
[0006] The pixel electrode layer includes at least one first sub-pixel electrode and at least one second sub-pixel electrode; the projected area of the first sub-pixel electrode on the substrate is larger than the projected area of the second sub-pixel electrode on the substrate; wherein,
[0007] The second sub-pixel electrode is located in the display area and is close to the nonlinear boundary region.
[0008] In some embodiments, the outer periphery of the second sub-pixel electrode, which is at least partially adjacent to the nonlinear boundary region, includes a nonlinear edge; any point on the nonlinear edge is equidistant from the nonlinear boundary region.
[0009] In some embodiments, the first sub-pixel electrode and at least a portion of the second sub-pixel electrode have the same shape, and the pixel pitch between two adjacent first sub-pixel electrodes is 2 to 3 times the pixel pitch between two adjacent second sub-pixel electrodes.
[0010] In some embodiments, the shape of a portion of the second sub-pixel electrode and the shape of the first sub-pixel electrode are both rectangular; the length of at least one set of parallel sides of the second sub-pixel electrode is 1 / 3 to 1 / 2 of the length of the corresponding parallel side of the first sub-pixel electrode.
[0011] In some embodiments, the driving layer includes at least one first scan line extending along a first direction and at least one second data line extending along a second direction;
[0012] The first scan line is shared by the second sub-pixel electrodes on both sides, and the second sub-pixel electrodes on both sides correspond to different second data lines.
[0013] In some embodiments, the driver layer further includes at least one first data line extending along a second direction; wherein,
[0014] The first data line is shared by the first sub-pixel electrodes arranged along the second direction; and when the first sub-pixel electrodes and the second sub-pixel electrodes are arranged simultaneously along the second direction, the corresponding first data line and the second data line are connected.
[0015] In some embodiments, the driving layer includes at least one first scan line, at least one second scan line, at least one first data line, and at least one second data line; wherein the first scan line and the second scan line are arranged along a second direction; and the first data line and the second data line are arranged along a first direction.
[0016] The first scan line is shared by the first sub-pixel electrodes arranged along the first direction; the first data line is shared by the first sub-pixel electrodes arranged along the second direction.
[0017] The second scan line is shared by the second sub-pixel electrodes arranged along the first direction; the second data line is shared by the second sub-pixel electrodes arranged along the second direction; wherein,
[0018] When the first sub-pixel electrode and the second sub-pixel electrode are arranged simultaneously along the first direction, the corresponding first scan line and second scan line are connected; when the first sub-pixel electrode and the second sub-pixel electrode are arranged simultaneously along the second direction, the corresponding first data line and second data line are connected.
[0019] In some embodiments, the pixel electrode layer further includes a boundary structure corresponding to the nonlinear boundary region, the boundary structure including a recess; wherein...
[0020] The second sub-pixel electrode portion adjacent to the recess is embedded in the recess and is spaced from the edge of the boundary structure.
[0021] In some embodiments, the driving layer includes at least one first thin-film transistor, which conducts a corresponding first sub-pixel electrode or second sub-pixel electrode via a via.
[0022] The second sub-pixel electrode includes a third sub-pixel electrode; wherein the third sub-pixel electrode is adjacent to the nonlinear boundary region;
[0023] When the ratio of the projected area of the third sub-pixel electrode on the substrate to the projected area of the first sub-pixel electrode on the substrate is greater than a preset value; the projection of the via corresponding to the third sub-pixel electrode on the substrate is located within the projection range of the third sub-pixel electrode on the substrate.
[0024] When the ratio of the projected area of the third sub-pixel electrode on the substrate to the projected area of the first sub-pixel electrode on the substrate is not greater than the preset value, the third sub-pixel electrode is electrically connected to the second sub-pixel electrode or the first sub-pixel electrode around it.
[0025] In some embodiments, the preset value is selected from any value between 0.5 and 0.8.
[0026] In some embodiments, the driving layer includes at least one second thin-film transistor, the second thin-film transistor corresponding to the first sub-pixel electrode or the second sub-pixel electrode;
[0027] The pixel electrode layer further includes a boundary structure corresponding to the nonlinear boundary region; the boundary structure includes at least one through hole.
[0028] The second thin-film transistor corresponding to a portion of the second sub-pixel electrode is located in the nonlinear boundary region, and the projection of the second thin-film transistor on the substrate and the projection of the through hole on the substrate at least partially overlap.
[0029] The backplate of the above embodiments has the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0030] Based on the same inventive concept, this disclosure also provides an electronic paper display panel; the electronic paper display panel includes the back panel described in any of the foregoing embodiments.
[0031] Based on the same inventive concept, this disclosure also provides a display device; the display device includes the electronic paper display panel described in any of the foregoing embodiments.
[0032] As can be seen from the above description, this disclosure provides a backplane, an electronic paper display panel, and a display device. The backplane includes a display area, a non-display area, and a non-linear boundary area located between the two. The backplane includes a substrate, a driving layer, and a pixel electrode layer stacked together. The pixel electrode layer includes at least one first sub-pixel electrode and at least one second sub-pixel electrode. The projected area of the first sub-pixel electrode on the substrate is larger than the projected area of the second sub-pixel electrode on the substrate. The second sub-pixel electrode is located on the side of the at least one first sub-pixel electrode closer to the non-linear boundary area. By providing a relatively small second sub-pixel electrode on the side closer to the non-linear boundary area, the jaggedness of the display near the non-linear boundary area is reduced, the display effect is improved, and the effective display area is increased. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A schematic diagram of a cross-sectional structure of an electronic paper display panel is shown;
[0035] Figure 2A A schematic diagram of the structure of an electronic paper display panel provided by related technologies is shown.
[0036] Figure 2B Show Figure 2A Enlarged structural diagram of dashed box A;
[0037] Figure 2C Show Figure 2A Schematic diagram of the cross-sectional structure of the backplate;
[0038] Figure 3A This diagram shows a partial structural schematic of a backplate provided in an embodiment of the present disclosure;
[0039] Figure 3B This diagram illustrates a design process structure of a backplate according to an embodiment of the present disclosure.
[0040] Figure 3C This diagram illustrates the structure of yet another backplate provided in an embodiment of the present disclosure;
[0041] Figure 3D This diagram shows a partial structural schematic of another backplate provided in an embodiment of the present disclosure;
[0042] Figure 3EThis diagram shows a partial structural schematic of another backplate provided in an embodiment of the present disclosure;
[0043] Figure 4A This diagram illustrates a wiring design for a backplane according to an embodiment of the present disclosure.
[0044] Figure 4B This diagram illustrates another backplane wiring design provided in an embodiment of the present disclosure. Detailed Implementation
[0045] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0046] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0047] Electronic paper display (EPD) is a display technology that mimics the visual characteristics of traditional paper, featuring low power consumption, high contrast, and excellent readability even in sunlight. It is widely used in e-book readers (such as Kindle), electronic tags, smartwatches, and other fields.
[0048] Among related technologies, electronic paper display technologies include, but are not limited to, electrophoretic display, electrowetting display, liquid crystal display, and electronic powder fluid display. Figure 1 A schematic cross-sectional view of an electronic paper display panel is shown, which employs electrophoretic display technology. Figure 1As shown, the electronic paper display panel 100 includes a substrate 101, a backplate 103, and an electronic paper film 102 between them. The electronic paper film 102 contains an electrophoretic solution containing black and white charged particles, which are positively and negatively charged, respectively. A lower electrode (corresponding to a pixel electrode) is disposed in the backplate 103, and an upper electrode is disposed in the substrate 101. Through the vertical electric field provided by the upper and lower electrodes, the black and white charged particles move vertically under the influence of the electric field. When the black charged particles are distributed on one side of the field of view of the electronic paper display structure, it is a black state display; when the white charged particles are distributed on one side of the field of view of the electronic paper display structure, it is a white state display. It should be noted that the electrophoretic solution may also contain red, green, and blue charged particles, and their display method is similar to that of black and white charged particles, which will not be described further.
[0049] Figure 2A This diagram illustrates the structure of an electronic paper display panel provided by related technologies. Figure 2B Show Figure 2A A magnified structural diagram of the dashed box A. (See diagram below.) Figure 2A and Figure 2B As shown, the electronic paper display panel 100 includes a display area 104 and a non-display area 105. It should be noted that the non-display area 105 includes not only the area surrounding the display area 104 (such as...) Figure 2A and Figure 2B As shown in the figure, it may also include a cutout area (not shown in the figure) within the display area 104. It should be noted that the cutout area can be used to install cameras, etc., and this disclosure does not limit it in this regard.
[0050] Figure 2C Show Figure 2A A schematic diagram of the cross-sectional structure of the backplate. (See diagram below.) Figure 2C As shown, the backplane 103 includes a substrate 1031, a driving layer, and a pixel electrode layer 200 stacked together. The driving layer includes an active layer 301, a gate insulating layer 302, a source drain layer, and a gate layer 303, through which multiple thin-film transistors (TFTs) are formed. Figure 2C (As shown in dashed box B). The thin-film transistor includes a gate 303, a first electrode 304, and a second electrode 305. The pixel electrode layer 200 includes a plurality of first sub-pixel electrodes, each of which is connected to the first electrode 304 or the second electrode 305 of the thin-film transistor via a via 306 (e.g., ...). Figure 2CAs shown in the diagram, this enables the thin-film transistor to control the first sub-pixel electrode. It should be noted that the control circuit for the first sub-pixel electrode 2011 can contain multiple thin-film transistors. The first sub-pixel electrode 2011 can be connected to either the first electrode 304 or the second electrode 305 of one of the thin-film transistors. Here, the thin-film transistor directly connected to the first sub-pixel electrode 2011 via a via can be called the first thin-film transistor; the remaining thin-film transistors can be called the second thin-film transistors.
[0051] An upper electrode is provided in the substrate 101. The upper electrode and the first sub-pixel electrode can control the black and white charged particles in the electronic paper film 102 under the action of a driver. In related technologies, conductive connecting lines are typically provided on the outer periphery of the display area 104 to electrically connect the backplate 103 and the substrate 101 to the driver. However, the provision of these conductive connecting lines restricts the reduction of the bezel size and reduces the utilization rate of raw materials (e.g., the glass forming the substrate 1031). Therefore, in related technologies, the formation of the display area 104 is modified to form a concave irregular region, and conductive connecting lines are provided in this irregular region (e.g., the glass forming the substrate 1031). Figure 2A (As shown in the dashed box A), thereby improving the utilization rate of raw materials and reducing the size of the border.
[0052] like Figure 2B As shown, boundary regions 2021 and 2022 are provided between the display area 104 and the non-display area 105. Boundary regions 2021 and 2022 include a linear boundary region 2021 and a non-linear boundary region 2022 to accommodate the irregularly shaped area of the conductive connection line 205. It should be noted that the edge of the non-linear boundary region 2022 is a straight line relative to the edge of the linear boundary region 2021, while the edge of the non-linear boundary region 2022 has a certain curvature. Boundary regions 2021 and 2022 are provided with boundary structures. The display area 104 includes a plurality of first sub-pixel electrodes 2011. The plurality of first sub-pixel electrodes 2011 are arranged in an array. Exemplarily, a first direction (e.g., the x-axis direction) and a second direction (e.g., the y-axis direction) intersect, and the plurality of first sub-pixel electrodes 2011 are arranged in an array along the first and second directions. The boundary structure can be disposed on the same layer as the first sub-pixel electrodes 2011, i.e., the pixel electrode layer 200. Optionally, the pixel electrode layer 200 can be indium tin oxide (ITO).
[0053] Furthermore, multiple first data lines 3011 are arranged along a first direction and can extend along a second direction; multiple first scan lines 3021 are arranged along a second direction and can extend along the first direction. The first data lines 3011 and first scan lines 3021 can be disposed on a driving layer; wherein, the first data lines 3011 can provide data signals to the first electrode 304 or the second electrode 305 of the thin-film transistor, and the first scan lines 3021 can provide scan signals to the gate 303 of the thin-film transistor. It should be noted that... Figure 2BThis example only shows a portion of the first data line 3011 and a portion of the first scan line 3021.
[0054] To avoid interference, a gap is required between the boundary structure and the first sub-pixel electrode 2011. Therefore, the portion of the first sub-pixel electrode 2011 that overlaps with the boundary structure is omitted. This disclosure does not limit the distance of this gap. Because the first sub-pixel electrode 2011 is partially omitted, the arrangement of the first sub-pixel electrodes 2011 around the boundary structure corresponding to the nonlinear boundary region 2022 appears jagged, resulting in poor display quality.
[0055] In view of this, the back panel, electronic paper display panel and display device provided in this disclosure reduce the jaggedness of the display near the nonlinear boundary region, improve the display effect and increase the effective display area by providing a relatively small second sub-pixel electrode on the side close to the nonlinear boundary region.
[0056] Figure 3A This diagram shows a partial structural schematic of a backplate provided in an embodiment of the present disclosure. Figure 3D This diagram shows a partial structural schematic of another backplate provided in an embodiment of the present disclosure. Figure 3E This diagram illustrates a partial structural schematic of yet another backplate provided in an embodiment of the present disclosure. (See reference...) Figure 3A , Figure 3D and Figure 3E The pixel electrode layer includes at least one first sub-pixel electrode 2011 and at least one second sub-pixel electrode 2012. The projected area of the first sub-pixel electrode 2011 on the substrate 1031 is larger than the projected area of the second sub-pixel electrode 2012 on the substrate 1031. The second sub-pixel electrode 2012 is located in the display area 104 and is close to the nonlinear boundary region 2022. By using the second sub-pixel electrode 2012 with a smaller projected area to fill at least part of the area of the first sub-pixel electrode 2011 that is omitted due to the setting of the nonlinear boundary region 2022, it is possible not only to effectively reduce the jaggedness near the nonlinear boundary region 2022 and improve the display effect, but also to help increase the effective display area.
[0057] In some embodiments, such as Figure 3A As shown, the first sub-pixel electrode 2011 and the second sub-pixel electrode 2012 have the same shape. Exemplarily, the shapes of the first sub-pixel 2011 and the sub-pixel 2012 can both be rectangles, squares, trapezoids, etc., and this disclosure does not limit this. Further, the pixel spacing between two adjacent first sub-pixel electrodes 2011 is 2 to 3 times the pixel spacing between two adjacent second sub-pixel electrodes 2012, for example, 2 times, 2.5 times, 3 times, etc.
[0058] In some embodiments, such as Figure 3EAs shown, the shapes of the second sub-pixel electrode 2012 and the first sub-pixel electrode 2011 are both rectangular; the length of at least one set of parallel sides of the second sub-pixel electrode 2012 is 1 / 3 to 1 / 2 of the length of the corresponding parallel side of the first sub-pixel electrode 2011, for example, 1 / 2, 5 / 12, etc. For example, the length of the parallel side of the second sub-pixel electrode 2012 in the y-axis direction is 1 / 2 of the length of the parallel side of the first sub-pixel electrode 2011 in the y-axis direction; the length of the parallel side in the x-axis direction is 1 / 2 of the length of the parallel side of the first sub-pixel electrode 2011 in the x-axis direction.
[0059] Figure 3B This diagram illustrates a design process structure of a backplate according to an embodiment of the present disclosure. Figure 3B As shown, although the projected area of the second sub-pixel electrode 2012 is smaller than that of the first sub-pixel electrode 2011, it still inevitably overlaps with the nonlinear boundary region 2022.
[0060] Therefore, this disclosure provides a grayscale design. Figure 3C A schematic diagram of another backplate provided in an embodiment of this disclosure is shown. For example... Figure 3C As shown, the size of the new second sub-pixel electrode 2012 is determined based on the non-overlapping projected area between the second sub-pixel electrode 2012 and the non-linear boundary region 2022, such that the projected area of the new second sub-pixel electrode 2012 is equal to the non-overlapping projected area. The boundary structure includes a recess 2023; the second sub-pixel electrode 2012 adjacent to the recess is partially embedded in the recess 2023 and spaced from the edge of the boundary structure. This design helps to maximize the area of the second sub-pixel electrode 2012, thereby reducing the impact of the non-linear boundary region 2022 on the display area.
[0061] In some alternative embodiments, such as Figure 3DAs shown, the outer periphery of the second sub-pixel electrode 2012 includes a non-linear edge; the distance between any point on the non-linear edge and the non-linear boundary region 2022 is equal. By changing the outer periphery of the second sub-pixel electrode 2012 according to the shape of the non-linear boundary region 2022, the outer periphery of the second sub-pixel electrode 2012 adapts to the shape of the non-linear boundary region 2022, thereby reducing the impact of the non-linear boundary region 2022 on the display area. Here, the distance between any point on the non-linear edge and the non-linear boundary region 2022 can be completely equal, or it can have a certain error, such as ±5%. It should be understood that the distance between any point on the non-linear edge and the non-linear boundary region 2022 helps to avoid the boundary structure on the non-linear boundary region 2022 from interfering with the second sub-pixel electrode 2012. The specific distance can be determined according to design standards, and this disclosure does not limit it. Furthermore, the error here can be an error within the allowable range of the design standards, and this disclosure does not limit it.
[0062] It should be noted that various design schemes for the second pixel electrode can be used individually, for example... Figure 3A and Figure 3D They can also be used in combination, for example Figure 3E This disclosure does not impose any limitations on this matter.
[0063] In conjunction with the foregoing, the size of the second sub-pixel electrode 2012 is smaller than the size of the first sub-pixel electrode 2011, as referenced. Figure 4A The original position of the first sub-pixel electrode 2011 can be used to set multiple second sub-pixel electrodes 2012. The first data line 2031 and the first scan line 2041 cannot control multiple second sub-pixel electrodes 2012, so the routing of the driving layer needs to be adjusted. Figure 4A This diagram illustrates a wiring design for a backplane according to an embodiment of the present disclosure. Figure 4A As shown, the driving layer includes at least one first scan line 2041, at least one second scan line 2042, at least one first data line 2031, and at least one second data line 2032; wherein, the first scan line 2041 and the second scan line 2042 are along a second direction (e.g., Figure 4A The first data line 2031 and the second data line 2032 are arranged along the first direction (e.g., the y-axis direction); Figure 4A Arranged along the x-axis.
[0064] Further, the first scan line 2041 is shared by the first sub-pixel electrodes 2011 arranged along the first direction; the first data line 2031 is shared by the first sub-pixel electrodes 2011 arranged along the second direction; the second scan line 2042 is shared by the second sub-pixel electrodes 2012 arranged along the first direction; the second data line 2032 is shared by the second sub-pixel electrodes 2012 arranged along the second direction; wherein, when the first sub-pixel electrodes 2011 and the second sub-pixel electrodes 2012 are arranged simultaneously along the first direction, the corresponding first scan line 2041 and the second scan line 2042 are connected; when the first sub-pixel electrodes 2011 and the second sub-pixel electrodes 2012 are arranged simultaneously along the second direction, the corresponding first data line 2031 and the second data line 2032 are connected. It should be noted that, as Figure 4A As shown, when the first sub-pixel electrode 2011 and the second sub-pixel electrode are arranged in a mixed manner, the first sub-pixel electrode 2011 arranged along the first direction (corresponding to one row) can correspond to two rows of second sub-pixel electrodes 2012, and either of these two rows of second sub-pixel electrodes 2012 can be considered to be arranged in the same row as the first sub-pixel electrode 2011. The first sub-pixel electrode 2011 arranged along the second direction (corresponding to one column) can correspond to two columns of second sub-pixel electrodes 2012, and either of these two columns of second sub-pixel electrodes 2012 can be considered to be in the same column as the first sub-pixel electrode 2011.
[0065] By setting a second scan line 2042 connected to the first scan line 2041 and a second data line 2032 connected to the first data line 2031, the second scan line 2042 and the second data line 2032 are used to drive and control the second sub-pixel electrode 2012. Furthermore, because the first scan line 2041 and the second scan line 2042 are connected, and the first data line 2031 and the second data line 2032 are connected, multiple second sub-pixel electrodes 2012 can be controlled using the same drive signal, facilitating drive control.
[0066] The above technical solution requires not only the setting of a second scan line 2042, but also the setting of a second data line 2032, which places high demands on the wiring of the backplane. Figure 4B This diagram illustrates another backplane wiring design provided in an embodiment of the present disclosure. For example... Figure 4BAs shown, the driving layer includes at least one first scan line 2041 extending along a first direction, at least one first data line 2031 extending along a second direction, and at least one second data line 2032 extending along the second direction. The first scan line 2041 is shared by the second sub-pixel electrodes 2012 on both sides, and the second sub-pixel electrodes 2012 on both sides correspond to different second data lines 2032. Further, the first data line 2031 is shared by the first sub-pixel electrodes 2011 arranged along the second direction. When the first sub-pixel electrodes 2011 and the second sub-pixel electrodes 2012 are arranged simultaneously along the second direction, the corresponding first data lines 2031 and second data lines 2032 are connected. This technical solution, by only adding the second data line 2032, can achieve driving control of the first sub-pixel electrodes 2011 and the second sub-pixel electrodes 2012 by relying on the first scan line 2041, the first data line 2031, and the second data line 2032, which is beneficial to the layout of the driving layer's wiring, thin-film transistors, etc.
[0067] In some embodiments, reference Figure 2C The driving layer includes at least one first thin-film transistor B, which conducts through a via 306 to either a corresponding first sub-pixel electrode 2011 or a second sub-pixel electrode 2012. To achieve effective conduction between the second sub-pixel electrode 2012 and the first thin-film transistor B, embodiments of this disclosure are rationally configured based on the position and size of the second sub-pixel electrode 2012 (corresponding to its projected area on the substrate). [Reference] Figure 3A , Figure 3C and Figure 3D The second sub-pixel electrode 2012 includes a third sub-pixel electrode; wherein the third sub-pixel electrode is adjacent to the nonlinear boundary region.
[0068] For example, when the ratio of the projected area of the third sub-pixel electrode on the substrate to the projected area of the first sub-pixel electrode 2011 on the substrate is greater than a preset value, it indicates that the size of the third sub-pixel electrode is large enough to accommodate a via. In this case, a corresponding via is provided, and the projection of the via corresponding to the third sub-pixel electrode onto the substrate is within the projection range of the third sub-pixel electrode onto the substrate. Optionally, the preset value is selected from any value between 0.5 and 0.8, such as 0.5, 0.6, 0.7, 0.8, etc.
[0069] For example, if the ratio of the projected area of the third sub-pixel electrode on the substrate to the projected area of the first sub-pixel electrode 2011 on the substrate is not greater than a preset value, it indicates that the size of the third sub-pixel electrode is large and it is difficult to set a via. In this case, the third sub-pixel electrode is electrically connected to the surrounding second sub-pixel electrode 2012 or first sub-pixel electrode 2011. It should be understood that the periodic second sub-pixel electrode 2012 or first sub-pixel electrode 2011 is connected to the corresponding first thin-film transistor through a via.
[0070] In conjunction with the foregoing, the pixel electrode layer 200 also includes a boundary structure corresponding to the nonlinear boundary region. When a second sub-pixel electrode 2012 is added to the pixel electrode layer 200, the position of the thin-film transistor corresponding to the second sub-pixel electrode 2012 may be the same as the arrangement of the thin-film transistors corresponding to the first sub-pixel electrode 2011, in order to minimize adjustments to the driving layer. Based on this, some of the second thin-film transistors of the second sub-pixel electrode 2012 may be located in the nonlinear boundary region 2022, thereby overlapping with the projection of the boundary structure onto the substrate. In some embodiments, the boundary structure includes a through-hole, and the projections of the second thin-film transistors onto the substrate 1031 and the through-holes onto the substrate 1031 at least partially overlap. This structural arrangement effectively avoids interference from the boundary structure to the second thin-film transistors.
[0071] Based on the same inventive concept, corresponding to the backplate of any of the above embodiments, this disclosure also provides an electronic paper display panel. The electronic paper display panel includes the backplate described in any of the foregoing embodiments.
[0072] The electronic paper display panel of the above embodiments has the same beneficial effects as the corresponding back panel embodiments, which will not be repeated here.
[0073] Based on the same inventive concept, corresponding to the electronic paper display panel of any of the above embodiments, this disclosure also provides a display device. The display device includes the electronic paper display panel described in any of the foregoing embodiments.
[0074] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.
[0075] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A backplate, characterized in that, The back panel includes a display area, a non-display area, and a non-linear boundary area between the two. The backplate includes a substrate, a driving layer, and a pixel electrode layer stacked together. The pixel electrode layer includes at least one first sub-pixel electrode and at least one second sub-pixel electrode; the projected area of the first sub-pixel electrode on the substrate is larger than the projected area of the second sub-pixel electrode on the substrate; wherein, The second sub-pixel electrode is located in the display area and is close to the nonlinear boundary region.
2. The backplate according to claim 1, characterized in that, The outer periphery of the second sub-pixel electrode, which is at least partially adjacent to the nonlinear boundary region, includes a nonlinear edge; any point on the nonlinear edge is equidistant from the nonlinear boundary region.
3. The backplate according to claim 1, characterized in that, The first sub-pixel electrode and at least a portion of the second sub-pixel electrodes have the same shape, and the pixel pitch between two adjacent first sub-pixel electrodes is 2 to 3 times the pixel pitch between two adjacent second sub-pixel electrodes; and / or The shape of the second sub-pixel electrode and the shape of the first sub-pixel electrode are both rectangular; the length of at least one set of parallel sides of the second sub-pixel electrode is 1 / 3 to 1 / 2 of the length of the corresponding parallel side of the first sub-pixel electrode.
4. The backplate according to claim 1, characterized in that, The driving layer includes at least one first scan line extending along a first direction and at least one second data line extending along a second direction; The first scan line is shared by the second sub-pixel electrodes on both sides, and the second sub-pixel electrodes on both sides correspond to different second data lines.
5. The backplate according to claim 4, characterized in that, The driving layer further includes at least one first data line extending along a second direction; wherein... The first data line is shared by the first sub-pixel electrodes arranged along the second direction; and when the first sub-pixel electrodes and the second sub-pixel electrodes are arranged simultaneously along the second direction, the corresponding first data lines and second data lines are connected.
6. The backplate according to claim 1, characterized in that, The driving layer includes at least one first scan line, at least one second scan line, at least one first data line, and at least one second data line; wherein the first scan line and the second scan line are arranged along a second direction; and the first data line and the second data line are arranged along a first direction. The first scan line is shared by the first sub-pixel electrodes arranged along the first direction; the first data line is shared by the first sub-pixel electrodes arranged along the second direction. The second scan line is shared by the second sub-pixel electrodes arranged along the first direction; the second data line is shared by the second sub-pixel electrodes arranged along the second direction; wherein, When the first sub-pixel electrode and the second sub-pixel electrode are arranged simultaneously along the first direction, the corresponding first scan line and second scan line are connected; when the first sub-pixel electrode and the second sub-pixel electrode are arranged simultaneously along the second direction, the corresponding first data line and second data line are connected.
7. The backplate according to claim 1, characterized in that, The pixel electrode layer further includes a boundary structure corresponding to the nonlinear boundary region, the boundary structure including a recess; wherein... The second sub-pixel electrode portion adjacent to the recess is embedded in the recess and is spaced from the edge of the boundary structure.
8. The backplate according to claim 1, characterized in that, The driving layer includes at least one first thin-film transistor, which conducts a corresponding first sub-pixel electrode or second sub-pixel electrode via a via. The second sub-pixel electrode includes a third sub-pixel electrode; wherein the third sub-pixel electrode is adjacent to the nonlinear boundary region; When the ratio of the projected area of the third sub-pixel electrode on the substrate to the projected area of the first sub-pixel electrode on the substrate is greater than a preset value; the projection of the via corresponding to the third sub-pixel electrode on the substrate is located within the projection range of the third sub-pixel electrode on the substrate. When the ratio of the projected area of the third sub-pixel electrode on the substrate to the projected area of the first sub-pixel electrode on the substrate is not greater than the preset value, the third sub-pixel electrode is electrically connected to the second sub-pixel electrode or the first sub-pixel electrode around it.
9. The backplate according to claim 8, characterized in that, The preset value is selected from any value between 0.5 and 0.
8.
10. The backplate according to claim 1, characterized in that, The driving layer includes at least one second thin-film transistor, the second thin-film transistor corresponding to the first sub-pixel electrode or the second sub-pixel electrode; The pixel electrode layer further includes a boundary structure corresponding to the nonlinear boundary region; the boundary structure includes at least one through hole. The second thin-film transistor corresponding to a portion of the second sub-pixel electrode is located in the nonlinear boundary region, and the projection of the second thin-film transistor on the substrate and the projection of the through hole on the substrate at least partially overlap.
11. An electronic paper display panel, characterized in that, Includes the backplate as described in any one of claims 1 to 10.
12. A display device, characterized in that, Includes the electronic paper display panel as described in claim 11.