Ceramic substrate structure for chip atomic clock
By combining ceramic substrates with flexible circuit boards, the problems of temperature difference control and magnetic interference in extreme environments of the chip atomic clock were solved, achieving stable operation with high reliability and low power consumption.
Patent Information
- Application Number
- CN202520860812.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-01
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-05-01
AI Technical Summary
Existing chip atomic clocks suffer from problems such as temperature difference control failure, magnetic interference, and insufficient assembly reliability under extreme environments. Furthermore, the thermo-mechanical properties of core components are not balanced, resulting in a significant performance drop under vacuum failure scenarios.
It adopts a ceramic substrate structure, combined with a flexible circuit board design, and rationally arranges chip pads and heating coils to provide non-magnetic heating function. It reduces power consumption through suspended air insulation and optimizes component layout to solve thermal-mechanical coupling imbalance.
Stable temperature control was achieved in extreme environments, magnetic interference was eliminated, power consumption was reduced, and the structural reliability and yield of components were improved.
Smart Images
Figure CN223842321U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip atomic clock technology, specifically to a ceramic substrate structure for chip atomic clocks. Background Technology
[0002] As a new generation of precision timekeeping devices, chip-based atomic clocks, with their advantages of high integration and low power consumption, have demonstrated significant application value in extreme scenarios such as deep space exploration, deep-sea operations, and underground resource exploration. The mainstream technologies for chip-based atomic clocks focus on MEMS atomic gas chambers, vacuum packaging, and cantilever beam thermal insulation structure design, aiming to improve reliability through miniaturized packaging and thermal management.
[0003] Existing chip atomic clock technology typically places components directly on a polyimide film in the cantilever beam thermal insulation structure design to improve thermal insulation. However, this design significantly increases assembly complexity and the risk of structural failure, making it difficult to meet high reliability requirements. In addition, chip atomic clock products, represented by Microchip's SA and 45S, although dominating the market with advanced packaging technology, have the following significant defects in their core component layout: First, the VCSEL laser, NTC temperature sensor, and TEC heater are directly integrated into the leadless chip carrier (LCC). When the vacuum environment is disrupted, the temperature difference between the upper and lower substrates of the TEC becomes too large (up to 70°C), making it impossible to effectively control the VCSEL temperature, resulting in laser failure. Second, the TEC uses a magnetic heating method, which interferes with the internal magnetic field environment of the atomic clock and reduces timing accuracy.
[0004] Therefore, how to optimize the substrate integration scheme of the above-mentioned core components and improve the thermal insulation efficiency and structural stability through size and layout design is the technical problem that this utility model needs to solve. On the other hand, in the existing chip atomic clock scheme, the multilayer stacking relationship between core components such as VCSEL, non-magnetic heating wire, NTC and substrate, and thin film has not yet achieved a balance of thermal and mechanical performance, resulting in a precipitous drop in performance under vacuum failure scenarios. Therefore, how to replace the traditional TEC heater, eliminate magnetic interference and reduce power consumption is another technical problem that needs to be solved. Summary of the Invention
[0005] To overcome the shortcomings of existing technologies, this utility model provides a ceramic substrate structure for chip atomic clocks. By covering the top and bottom surfaces of the ceramic substrate with a flexible circuit board and rationally arranging multiple chip pads, via pads, and heating coils on the flexible circuit board, core problems such as temperature difference control failure, magnetic interference, and insufficient assembly reliability can be solved, providing technical support for the stable operation of chip atomic clocks in complex environments.
[0006] The technical solution provided by this utility model is as follows:
[0007] A ceramic substrate structure for a chip-based atomic clock includes a square-shaped ceramic substrate, an upper flexible circuit board covering the upper and lower outer surfaces of the ceramic substrate, and a lower flexible circuit board. The ceramic substrate, made of ceramic material, offers higher hardness, better thermal conductivity, and easier processing compared to traditional silicon-based substrates. The ceramic substrate provides support for the VCSEL chip, NTC chip, and atomic gas chamber, and also provides non-magnetic heating for the VCSEL chip and atomic gas chamber. This physical structure, with its integrated heating and temperature measurement design, significantly reduces device packaging costs and increases yield. Furthermore, the ceramic substrate, combined with the single-layer flexible circuit board, can power the VCSEL chip, NTC chip, and heaters on the ceramic substrate, and can also suspend the ceramic and the entire atomic gas chamber structure to achieve air insulation, thereby reducing power consumption.
[0008] The upper flexible circuit board has a first chip negative electrode pad at its center. The first via pad and the fourth via pad are symmetrically arranged on the upper and lower sides of the first chip negative electrode pad. The first via pad is connected to the positive electrode of the first chip. The second via pad and the third via pad are symmetrically arranged on the left and right sides of the first via pad. The second via pad is connected to the first chip negative electrode pad through a wire.
[0009] A first thermally conductive pad and a second thermally conductive pad are symmetrically arranged on the left and right sides of the negative electrode pad of the first chip. The first thermally conductive pad and the second thermally conductive pad are bonded to the atomic gas cell thermally conductive structure. A first positive electrode pad of the first chip is arranged between the negative electrode pad of the first chip and the first via pad and is connected to the first via pad by a wire.
[0010] A second chip positive pad is provided between the first chip negative pad and the second thermal pad, and near the first chip negative pad, and is connected to the third via pad by a wire. A second chip negative pad is provided directly below the second chip positive pad and is connected to the fourth via pad by a wire.
[0011] A heating coil for heating the atomic gas chamber is provided near the outer periphery of the lower flexible circuit board. A heating positive pad and a heating negative pad are provided near the middle position below the bottom surface of the ceramic substrate and connected to the two ends of the heating resistance wire of the heating coil. A fifth via pad connected to the fourth via pad is provided between the heating positive pad and the heating negative pad.
[0012] Furthermore, on the top surface of the ceramic substrate with the first chip negative electrode pad as the origin, the first via pad and the fourth via pad are located on the Y-axis; the first thermally conductive pad passes through the X-axis and is located in the second and third quadrants, the second thermally conductive pad passes through the X-axis and is located in the first and fourth quadrants; the second via pad is located in the second quadrant, the third via pad is located in the first quadrant; the second chip negative electrode pad is located in the fourth quadrant, and the second chip positive electrode pad is located on the X-axis.
[0013] Furthermore, the distance d1 between the left end of the first thermal pad and the right end of the second thermal pad is greater than the distance d2 between the left end of the second via pad and the right end of the third via pad, and the distance d3 between the lower end of the first via pad and the upper end of the fourth via pad is greater than the distance d4 between the upper end of the second chip negative pad and the lower end of the second chip positive pad.
[0014] Furthermore, a sixth via pad is provided at the middle position above the flexible circuit board on the bottom surface of the ceramic substrate. A seventh via pad and an eighth via pad are symmetrically provided on the left and right sides of the sixth via pad. The sixth via pad is communicatively connected to the first via pad, the seventh via pad is communicatively connected to the third via pad, and the eighth via pad is communicatively connected to the second via pad.
[0015] Furthermore, the heating coil is a double-layer frame structure made of a heating resistance wire, which includes a left inner frame wire, a right inner frame wire, and an outer frame wire wound parallel to the left and right inner frame wires. The lower end of the left inner frame wire is the beginning of the conductor, which is connected to the heating positive electrode pad. The upper end of the left inner frame wire is connected to one end of the outer frame wire, and the other end of the outer frame wire is connected to the upper end of the right inner frame wire. The lower end of the right inner frame wire is the end of the conductor, which is connected to the heating negative electrode pad.
[0016] Furthermore, the ceramic substrate is made of aluminum nitride semiconductor material, with a thermal conductivity ranging from 100 W / (m*K) to 260 W / (m*K); a Vickers hardness ranging from 10 GPa to 12 GPa; and a bending strength ranging from 300 MPa to 350 MPa.
[0017] Furthermore, multiple pads are disposed on the upper and lower flexible circuit boards. The cross-section of the multiple pads is composed of a Ni layer, a Cu layer and an Au layer from top to bottom. The thickness of the Ni layer ranges from 5nm to 10nm, the thickness of the Cu layer ranges from 1um to 5um, and the thickness of the Au layer ranges from 50-100 nm. The multiple pads include a first chip negative electrode pad, a first via pad, a second via pad, a third via pad, a first thermally conductive pad, a second thermally conductive pad, a second chip negative electrode pad, a fourth via pad, a heated positive electrode pad, a heated negative electrode pad, a fifth via pad, a second chip positive electrode pad, a seventh via pad, a sixth via pad, an eighth via pad, a first chip positive electrode pad, and a conductive wire.
[0018] Furthermore, the line width of the heating coil frame ranges from 0.1µm to 0.5µm, and the spacing between the inner and outer frame lines ranges from 0.1µm to 0.5µm;
[0019] The heating resistance wire in the heating coil has a cross-section composed of a Ni layer and an Au layer from top to bottom. The thickness of the Ni layer ranges from 5 nm to 10 nm, and the thickness of the Au layer ranges from 100 nm to 200 nm.
[0020] The ceramic substrate structure for chip atomic clocks described in this invention achieves multiple technical improvements through material innovation and integrated design. The specific technical effects are as follows:
[0021] 1. This invention utilizes aluminum nitride semiconductor material, which is high in hardness, high in thermal conductivity, and easy to process, as the ceramic substrate material. Its thermal conductivity reaches 260 W / (m·K); its Vickers hardness reaches 12 GPa; and its bending strength reaches 350 MPa. It effectively replaces traditional silicon-based substrates, possessing excellent mechanical support performance and thermal management capabilities. It not only provides stable support for VCSEL lasers, NTC temperature sensors, and atomic gas chambers, but also integrates non-magnetic heating functionality, thereby replacing traditional TEC heaters and completely eliminating the impact of magnetic interference on atomic clock accuracy. This solves the problem that existing TEC heaters cannot eliminate magnetic interference and reduce power consumption. Simultaneously, it simplifies the physical structure of the heating and temperature measurement system, significantly reducing packaging complexity and manufacturing costs, and improving yield.
[0022] 2. This utility model innovatively integrates power supply and suspended air insulation functions through the collaborative design of a ceramic substrate and a single-layer flexible circuit board (FPC): the single-layer flexible circuit board (FPC) not only supplies power to the chips and heating elements on the ceramic substrate, but also isolates the ceramic substrate and core components such as the atomic gas chamber from the external environment through the suspension structure. The air layer insulation significantly reduces heat loss and can maintain stable temperature control even under extreme conditions such as vacuum destruction, reducing the overall power consumption to less than 10% of the traditional solution. This solves the technical problem in the existing technology where the VCSEL laser, NTC temperature sensor and TEC heater are directly integrated into the leadless chip carrier (LCC), resulting in the inability to effectively control the VCSEL temperature when the vacuum environment is destroyed due to the large temperature difference (up to 70°C) between the upper and lower substrates of the TEC, thus causing the laser to become disabled.
[0023] 3. This utility model solves the problem of thermal-mechanical coupling imbalance caused by stacking design in the prior art by optimizing the size and reconstructing the layout of the pads that carry electronic components on the ceramic substrate. It not only ensures the performance robustness when vacuum packaging fails, but also improves the long-term structural reliability of components in complex environments such as deep space and deep sea, providing key support for the high-precision, low-power and miniaturized development of chip atomic clocks.
[0024] 4. The ceramic substrate structure for chip atomic clocks described in this utility model can not only support multiple components such as VCSEL chips, NTC chips, heating coils and atomic gas chambers, but also provide electrical connections for electrical components and effectively conduct heat to the atomic gas chambers to achieve the purpose of heating them. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of a ceramic substrate structure for a chip atomic clock according to an embodiment of the present invention;
[0026] Figure 2 yes Figure 1 The main view;
[0027] Figure 3 yes Figure 1 Rear view. Detailed Implementation
[0028] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.
[0029] As attached Figure 1 To be continued Figure 2 As shown, this utility model embodiment provides a ceramic substrate structure for a chip atomic clock, including a square ceramic substrate 1 with a thickness of 0.4 mm, a length and width of 4 mm, and rounded corners with a radius of 0.3 mm. The ceramic substrate 1 is made of aluminum nitride semiconductor material, i.e., AlN material, with a thermal conductivity range of 260 W / (m·K), a Vickers hardness range of 12 GPa, and a bending strength of 350 MPa.
[0030] The top surface of the ceramic substrate 1 is covered with an upper flexible circuit board, and the bottom surface is covered with a lower flexible circuit board. Both the upper and lower flexible circuit boards are single-layer flexible circuit boards. The single-layer flexible circuit boards are connected to the ceramic substrate through eight pads on their top surface and six solder points on their bottom surface. This not only provides electrical connection to the ceramic substrate but also suspends the entire chip atomic clock optical system, atomic gas cell, and detection system, thereby reducing the power consumption of the atomic clock.
[0031] A first chip negative electrode pad 2 is provided at the center of the upper flexible circuit board. A first via pad 3 and a fourth via pad 9 are symmetrically provided on the upper and lower sides of the first chip negative electrode pad 2. The first via pad 3 is connected to the positive electrode of the first chip. A second via pad 4 and a third via pad 5 are symmetrically provided on the left and right sides of the first chip negative electrode pad 2. The second via pad 4 is connected to the first chip negative electrode pad 2 through a wire a. In this embodiment, the first chip is a VCSEL chip, the first chip negative electrode pad is the VCSEL chip negative electrode pad, and the first chip positive electrode is the VCSEL chip positive electrode.
[0032] A first thermally conductive pad 6 and a second thermally conductive pad 7 are symmetrically arranged on both sides of the first chip negative electrode pad 2. The first thermally conductive pad 6 and the second thermally conductive pad 7 are bonded to the atomic gas chamber thermal conductive structure; in this embodiment, the atomic gas chamber thermal conductive structure is a gas chamber heating bracket. A first chip positive electrode pad 18 is provided between the first chip negative electrode pad 2 and the first via pad 3 and is connected to the first via pad 3 through a wire b.
[0033] A second chip positive pad 14 is provided between the first chip negative pad 2 and the second thermally conductive pad 7, and near the first chip negative pad 2. It is connected to the third via pad 5 by a wire c. A second chip negative pad 8 is provided directly below the second chip positive pad 14 and connected to the fourth via pad 9 by a wire d. In this embodiment, the second chip is an NTC chip, the second chip positive pad is an NTC chip positive pad, and the second chip negative pad is an NTC chip negative pad.
[0034] The distance d1 between the left end of the first thermal pad 6 and the right end of the second thermal pad 7 is greater than the distance d2 between the left end of the second via pad 4 and the right end of the third via pad 5. The distance d3 between the lower end of the first via pad 3 and the upper end of the fourth via pad 9 is greater than the distance d4 between the upper end of the second chip negative pad 8 and the lower end of the second chip positive pad 14.
[0035] In this embodiment, the via diameter of the via pad is 0.2 to 0.3 mm, preferably 0.3 mm. The via pad includes a first via pad 3, a second via pad 4, a third via pad 5, and a fourth via pad 9. The first chip negative electrode pad 2 has dimensions of 0.16 mm * 0.2 mm and is located at the exact center of the ceramic substrate. The first via pad 3 has dimensions of 3 mm * 3 mm and its center is located directly above the first chip negative electrode pad 2. The dimensions of the second chip positive pad 14 and the second chip negative pad 8 are both 0.15mm*0.15mm. The second chip positive pad 14 is located 0.2mm to the right of the first chip negative pad 2, and the second chip negative pad 8 is located directly below the second chip positive pad 14. The dimensions of the first thermal pad 6 and the second thermal pad 7 are both 0.5mm*1.0mm. They are symmetrically distributed at both ends of the center of the ceramic substrate, with a distance of 0.4mm from the edge.
[0036] In this embodiment, the dimensions of the second via pad 4, the first via pad 3, the third via pad 5, and the fourth via pad 9 are all 0.3mm*0.3mm. The first via pad 3 is located 2mm directly above the center of the ceramic substrate. The second via pad 4 and the third via pad 5 are symmetrically distributed to the left and right of the first via pad 3, with a spacing of 0.2mm. Pad 10 is located directly below the first via pad 3, and the fourth via pad 9 is 0.6mm from the bottom edge of the ceramic substrate.
[0037] As attached Figure 3 As shown, a heating coil 13 for heating the atomic gas chamber is provided near the outer periphery of the lower flexible circuit board. A heating positive pad 10 and a heating negative pad 11, which are connected to the two ends of the heating resistance wire of the heating coil 13, are provided near the middle position below the bottom surface of the ceramic substrate 1. A fifth via pad 12, which connects to the fourth via pad 9, is provided between the heating positive pad 10 and the heating negative pad 11. A sixth via pad 16 is provided at the middle position above the flexible circuit board on the bottom surface of the ceramic substrate 1. A seventh via pad 15 and an eighth via pad 17 are symmetrically provided on the left and right sides of the sixth via pad 16. The sixth via pad 16 is communicatively connected to the first via pad 3, the seventh via pad 15 is communicatively connected to the third via pad 5, and the eighth via pad 17 is communicatively connected to the second via pad 4.
[0038] The heating positive electrode pad 10, the fifth via pad 12, the heating negative electrode pad 11, the seventh via pad 15, the sixth via pad 16, and the eighth via pad 17 all have a length and width of 0.4mm*0.4mm. The heating positive electrode pad 10, the fifth via pad 12, and the heating negative electrode pad 11 are located below the lower flexible circuit board, with the fifth via pad 12 located 1.3mm directly below the center of the lower flexible circuit board. The heating positive electrode pad 10 and the heating negative electrode pad 11 are located on either side of the fifth via pad 12, with a distance of 0.2mm. The seventh via pad 15, the sixth via pad 16, and the eighth via pad 17 are located above the lower flexible circuit board, with the sixth via pad 16 located 1.5mm directly above the center of the lower flexible circuit board. The seventh via pad 15 and the eighth via pad 17 are located on either side of the sixth via pad 16, with a distance of 0.2mm.
[0039] Multiple pads are disposed on the upper and lower flexible circuit boards. These pads include a first chip negative electrode pad 2, a first via pad 3, a second via pad 4, a third via pad 5, a first thermally conductive pad 6, a second thermally conductive pad 7, a second chip negative electrode pad 8, a fourth via pad 9, a heating positive electrode pad 10, a heating negative electrode pad 11, a fifth via pad 12, a second chip positive electrode pad 14, a seventh via pad 15, a sixth via pad 16, an eighth via pad 17, a first chip positive electrode pad 18, and wires a, b, c, and d. In this embodiment, the cross-section of these pads, from top to bottom, consists of a Ni layer, a Cu layer, and an Au layer. The Ni layer has a thickness of 8 nm, the Cu layer has a thickness of 3 μm, and the Au layer has a thickness of 80 nm.
[0040] On the top surface of the ceramic substrate 1 with the first chip negative electrode pad 2 as the origin, the first via pad 3 and the fourth via pad 9 are located on the Y-axis; the first thermally conductive pad 6 passes through the X-axis and is located in the second and third quadrants, the second thermally conductive pad 7 passes through the X-axis and is located in the first and fourth quadrants; the second via pad 4 is located in the second quadrant, the third via pad 5 is located in the first quadrant; the second chip negative electrode pad 8 is located in the fourth quadrant, and the second chip positive electrode pad 14 is located on the X-axis.
[0041] The heating coil 13 is a double-layer frame structure made of a single heating resistance wire. The heating resistance wire adopts a double-wire winding structure to counteract the magnetic field generated by the current. It includes a left inner frame wire, a right inner frame wire, and an outer frame wire wound parallel to the left and right inner frame wires. The lower end of the left inner frame wire is the lead wire end, which is connected to the heating positive electrode pad 10. The upper end of the left inner frame wire is connected to one end of the outer frame wire, and the other end of the outer frame wire is connected to the upper end of the right inner frame wire. The lower end of the right inner frame wire is the lead wire end, which is connected to the heating negative electrode pad 11. In this embodiment, the frame wire width of the heating coil 13 is 0.3 μm, and the spacing between the inner and outer frame wires is 0.3 μm. The heating resistance wire in the heating coil 13 has a cross-section composed of a Ni layer and an Au layer from top to bottom. The thickness of the Ni layer is 8 nm, and the thickness of the Au layer is 150 nm.
[0042] This utility model provides a ceramic substrate structure for a chip atomic clock. By covering the upper side with a flexible circuit board and rationally arranging the first chip negative electrode pad 2, the first via pad 3, the second via pad 4, the third via pad 5, the first thermally conductive pad 6, the second thermally conductive pad 7, the second chip negative electrode pad 8, the fourth via pad 9, the second chip positive electrode pad 14, and the first chip positive electrode pad on the upper flexible circuit board, and then covering the lower side with a flexible circuit board and rationally arranging the heating positive electrode pad 10, the heating negative electrode pad 11, the fifth via pad 12, the seventh via pad 15, the sixth via pad 16, the eighth via pad 17, and the heating coil 13 on the lower flexible circuit board, the thermal-mechanical coupling imbalance problem caused by the stacking design in the prior art is solved. This not only ensures the performance robustness when vacuum packaging fails, but also improves the long-term structural reliability of components in complex environments such as deep space and deep sea, providing key support for the high-precision, low-power, and miniaturized development of chip atomic clocks.
Claims
1. A ceramic substrate structure for a chip atomic clock, comprising a square-shaped ceramic substrate (1), an upper flexible circuit board covering the upper and lower outer surfaces of the ceramic substrate (1), and a lower flexible circuit board, characterized in that, The upper flexible circuit board has a first chip negative electrode pad (2) at its center. The first chip negative electrode pad (2) is symmetrically provided with a first via pad (3) and a fourth via pad (9) on its upper and lower sides. The first via pad (3) is connected to the first chip positive electrode. The second via pad (4) and the third via pad (5) are symmetrically provided on its left and right sides. The second via pad (4) is connected to the first chip negative electrode pad (2) through a wire. The first chip negative electrode pad (2) is symmetrically provided with a first thermally conductive pad (6) and a second thermally conductive pad (7) on its left and right sides. The first thermally conductive pad (6) and the second thermally conductive pad (7) are attached to the atomic gas chamber thermally conductive structure. The first chip negative electrode pad (2) and the first via pad (3) are provided with a first chip positive electrode pad (18) connected to the first via pad (3) by a wire. A second chip positive pad (14) is provided between the first chip negative pad (2) and the second thermal pad (7) and near the first chip negative pad (2), and is connected to the third via pad (5) by a wire. A second chip negative pad (8) is provided directly below the second chip positive pad (14) and is connected to the fourth via pad (9) by a wire. A heating coil (13) for heating the atomic gas chamber is provided on the lower flexible circuit board near the outer peripheral edge. A heating positive electrode pad (10) and a heating negative electrode pad (11) connected to the two ends of the heating resistance wire of the heating coil (13) are provided on the bottom surface of the ceramic substrate (1) near the middle position. A fifth via pad (12) connecting the fourth via pad (9) is provided between the heating positive electrode pad (10) and the heating negative electrode pad (11). The distance d1 between the left end of the first thermal pad (6) and the right end of the second thermal pad (7) is greater than the distance d2 between the left end of the second via pad (4) and the right end of the third via pad (5). The distance d3 between the lower end of the first via pad (3) and the upper end of the fourth via pad (9) is greater than the distance d4 between the upper end of the second chip negative electrode pad (8) and the lower end of the second chip positive electrode pad (14).
2. The ceramic substrate structure for a chip atomic clock as described in claim 1, characterized in that: On the top surface of the ceramic substrate (1) with the first chip negative electrode pad (2) as the origin, the first via pad (3) and the fourth via pad (9) are located on the Y-axis; the first thermally conductive pad (6) passes through the X-axis and is located in the second and third quadrants, the second thermally conductive pad (7) passes through the X-axis and is located in the first and fourth quadrants; the second via pad (4) is located in the second quadrant, the third via pad (5) is located in the first quadrant; the second chip negative electrode pad (8) is located in the fourth quadrant, and the second chip positive electrode pad (14) is located on the X-axis.
3. The ceramic substrate structure for a chip atomic clock as described in claim 2, characterized in that: A sixth via pad (16) is provided at the middle position above the flexible circuit board on the bottom surface of the ceramic substrate (1). A seventh via pad (15) and an eighth via pad (17) are symmetrically provided on the left and right sides of the sixth via pad (16). The sixth via pad (16) is communicatively connected to the first via pad (3), the seventh via pad (15) is communicatively connected to the third via pad (5), and the eighth via pad (17) is communicatively connected to the second via pad (4).
4. The ceramic substrate structure for a chip atomic clock as described in claim 3, characterized in that: The heating coil (13) is a double-layer frame structure made of a heating resistance wire. It includes a left inner frame, a right inner frame, and an outer frame wound parallel to the left and right inner frame. The lower end of the left inner frame is the beginning of the conductor, which is connected to the heating positive electrode pad (10). The upper end of the left inner frame is connected to one end of the outer frame, and the other end of the outer frame is connected to the upper end of the right inner frame. The lower end of the right inner frame is the end of the conductor, which is connected to the heating negative electrode pad (11).
5. The ceramic substrate structure for a chip atomic clock as described in claim 4, characterized in that: The ceramic substrate (1) is made of aluminum nitride semiconductor material, with a thermal conductivity ranging from 100 W / (m*K) to 260 W / (m*K); a Vickers hardness ranging from 10 GPa to 12 GPa; and a bending strength ranging from 300 MPa to 350 MPa.
6. A ceramic substrate structure for a chip atomic clock as described in claim 1 or 5, characterized in that: The upper and lower flexible circuit boards are provided with multiple pads. The cross-section of the multiple pads is composed of a Ni layer, a Cu layer and an Au layer from top to bottom. The thickness of the Ni layer ranges from 5nm to 10nm, the thickness of the Cu layer ranges from 1um to 5um, and the thickness of the Au layer ranges from 50-100nm. The multiple pads include a first chip negative electrode pad (2), a first via pad (3), a second via pad (4), a third via pad (5), a first thermally conductive pad (6), a second thermally conductive pad (7), a second chip negative electrode pad (8), a fourth via pad (9), a heated positive electrode pad (10), a heated negative electrode pad (11), a fifth via pad (12), a second chip positive electrode pad (14), a seventh via pad (15), a sixth via pad (16), an eighth via pad (17), a first chip positive electrode pad (18), and a wire.
7. The ceramic substrate structure for a chip atomic clock as described in claim 6, characterized in that: The frame line width of the heating coil (13) ranges from 0.1um to 0.5um, and the spacing between the inner frame line and the outer frame line ranges from 0.1um to 0.5um; The heating resistance wire in the heating coil (13) has a cross-section composed of a Ni layer and an Au layer from top to bottom. The thickness of the Ni layer ranges from 5 nm to 10 nm, and the thickness of the Au layer ranges from 100 nm to 200 nm.