Driving control circuit and energy storage power supply thereof

Abstract

The embodiment of the utility model discloses a driving control circuit and an energy storage power supply thereof. The driving control circuit comprises a first driving module, a second driving module, a third driving module and a fourth driving module. The four driving modules are respectively connected with the corresponding power tubes, the first outer power tube and the second inner power tube form a first complementary pair, and the first inner power tube and the second outer power tube form a second complementary pair. The first driving module receives a driving signal used for controlling the second inner power tube, the second driving module receives a driving signal used for controlling the second outer power tube, the third driving module receives a driving signal used for controlling the first outer power tube, and the fourth driving module receives a driving signal used for controlling the first inner power tube. Through the above mode, the embodiment of the utility model can realize the dead zone control of the power tube, the interlocking protection of the complementary tube and the outer tube, and the wave-by-wave current limiting function, and improves the reliability of the NPC three-level circuit.

Description

Technical Field

[0001] This utility model relates to the field of electronic technology, and in particular to a drive control circuit and its energy storage power supply. Background Technology

[0002] The selection of inverter circuit topology is an important research direction for energy storage inverters. In high-voltage and high-power applications, the Neutral Point Clamped (NPC) three-level circuit is one of the most commonly used circuit topologies. There are also various drive-locking protection circuits for the NPC three-level circuit. However, in general, two issues need to be considered: the turn-on and turn-off sequence of the inner and outer transistors in the NPC three-level circuit, and how to interlock the complementary drives of the transistors to prevent shoot-through.

[0003] Existing Type I NPC three-level drive circuits mostly use RCD switching delay dead-time circuits to generate the time difference between the switching processes of the inner and outer transistors, thereby ensuring that during the turn-on process, the inner transistor turns on before the outer transistor, and during the turn-off process, the outer transistor turns off before the inner transistor. There are also technologies that use software control to generate drive protection. This method uses complex software algorithms to determine the drive dead time of the inner and outer transistors and complementary drive transistors through the internal triggers of the DSP, thereby realizing the drive protection function.

[0004] Using an RCD switching delay dead-time circuit cannot achieve wave-by-wave current limiting or dead-time control of the switching time difference between the inner and outer transistors under fault protection. Furthermore, the enable signal does not pass through the RCD switching delay time circuit and directly controls the output of the drive signal, posing a risk that the RCD switching delay time is insufficient, causing the inner and outer transistors to switch simultaneously. Moreover, the hardware circuit lacks complementary drive interlocking functionality, making it impossible to implement drive dead-time protection for complementary drive transistors in hardware. Using software control to generate drive protection requires additional DSP resources, is computationally complex, and requires a processing chip with high computing power. In addition, software implementation of drive protection during power-on, power-off, and operation is susceptible to software timing anomalies and DSP crashes, which may cause the drive protection function to fail. Utility Model Content

[0005] The main technical problem solved by this utility model embodiment is to provide a drive control circuit and its energy storage power supply, which can solve some of the problems existing in the above-mentioned existing NPC three-level drive circuit.

[0006] To solve the above-mentioned technical problems, the present invention provides a driving control circuit, comprising: a first driving module, a second driving module, a third driving module, and a fourth driving module, each driving module including a delay unit; the first driving module and the second driving module are respectively connected to a first external power transistor and a first internal power transistor; the third driving module and the fourth driving module are respectively connected to a second internal power transistor and a second external power transistor; wherein, the first external power transistor and the second internal power transistor form a first complementary pair, and the first internal power transistor and the second external power transistor form a second complementary pair; the first driving module receives a third driving signal for controlling the second internal power transistor, and the second driving module receives a fourth driving signal for controlling the second external power transistor; the third driving module receives a first driving signal for controlling the first external power transistor, and the fourth driving module receives a second driving signal for controlling the first internal power transistor; the first driving module and the third driving module generate dead time through their respective delay units, and the second driving module and the fourth driving module generate dead time through their respective delay units.

[0007] In some embodiments, the first driving module further includes a first input terminal and a second input terminal, the first input terminal being used to receive a first pulse signal and the second input terminal being used to receive a second interlock signal; the second driving module further includes a second input terminal, the second input terminal of the second driving module being used to receive the second pulse signal and output the second interlock signal; the first driving module and the second driving module respond to the second interlock signal, and control the first external power transistor to turn off before the first internal power transistor and the first internal power transistor to turn on before the first external power transistor through their respective delay units.

[0008] In some embodiments, the third driving module further includes a second input terminal, which is used to receive a third pulse signal and output a third interlock signal; the fourth driving module further includes a first input terminal and a second input terminal, which is used to receive a fourth pulse signal and the second input terminal is used to receive the third interlock signal; the third driving module and the fourth driving module respond to the third interlock signal by controlling the second external power transistor to turn off before the second internal power transistor and the second internal power transistor to turn on before the second external power transistor through their respective delay units.

[0009] In some embodiments, when the input level of the delay unit of the first driving module changes from high to low, the first driving signal is output after a first delay time; when the input level of the delay unit of the second driving module changes from high to low, the second driving signal is output after a second delay time; wherein the second delay time is greater than the first delay time; when the input level of the delay unit of the first driving module changes from low to high, the first driving signal is output after a third delay time; when the input level of the delay unit of the second driving module changes from low to high, the second driving signal is output after a fourth delay time; wherein the third delay time is greater than the fourth delay time.

[0010] In some embodiments, when the input level of the delay unit of the third driving module changes from high to low, the third driving signal is output after a fifth delay time; when the input level of the delay unit of the fourth driving module changes from high to low, the fourth driving signal is output after a sixth delay time; wherein the sixth delay time is less than the fifth delay time; when the input level of the delay unit of the third driving module changes from low to high, the third driving signal is output after a seventh delay time; when the input level of the delay unit of the fourth driving module changes from low to high, the fourth driving signal is output after an eighth delay time; wherein the seventh delay time is less than the eighth delay time.

[0011] In some embodiments, the drive control circuit further includes a control module connected to the control terminals of the first drive module, the second drive module, the third drive module, and the fourth drive module; the control module is used to receive at least one control signal and output a wave-locked control signal based on the level state of the control signal; the control signal includes at least one of the following: an enable signal, a fault signal, and a current limiting signal; the first drive module, the second drive module, the third drive module, and the fourth drive module respond to the level state of the wave-locked control signal and adjust the conduction state of the corresponding power transistors through their respective delay units; wherein, the delay units generate different delay times based on the level transition of the wave-locked control signal, so that the corresponding power transistors switch operating states according to a preset conduction sequence.

[0012] In some embodiments, the first driving module includes a first diode, a third diode, a first NOT gate, a first AND gate, a first resistor, a fifth resistor, a sixth resistor, a second capacitor, a second diode, and a third AND gate; the anode of the first diode is connected to the interlock signal output terminal of the third driving module, the anode of the third diode is connected to the driving signal output terminal of the third driving module, the cathode of the first diode is connected to the cathode of the third diode, the first terminal of the sixth resistor, and the input terminal of the first NOT gate, the second terminal of the sixth resistor is grounded, the output terminal of the first NOT gate is connected to the first input terminal of the first AND gate, and the second input terminal of the first AND gate is connected to the interlock signal output terminal of the second driving module; the first terminal of the first resistor is connected to the output terminal of the first AND gate, the first terminal of the fifth resistor, and the cathode of the second diode, the second terminal of the first resistor is connected to the anode of the second diode, and the first terminal of the second capacitor, the second terminal of the fifth resistor and the second terminal of the second capacitor are grounded; the first input terminal of the third AND gate is connected to the second terminal of the first resistor, the second input terminal of the third AND gate is connected to a first pulse signal, and the output terminal of the third AND gate is connected to the first external power transistor.

[0013] In some embodiments, the second driving module includes a second NOT gate, a fourth AND gate, an eighth resistor, a tenth resistor, an eleventh resistor, a third capacitor, a fifth diode, and a sixth AND gate; the input terminal of the second NOT gate is connected to the driving signal output terminal of the fourth driving module, the output terminal of the second NOT gate is connected to the first input terminal of the fourth AND gate, and the second input terminal of the fourth AND gate is connected to a second pulse signal; the first terminal of the eighth resistor is connected to the output terminal of the fourth AND gate, the first terminal of the eleventh resistor, and the anode of the fifth diode; the cathode of the fifth diode is connected to the first terminal of the tenth resistor; the second terminal of the eighth resistor is connected to the second terminal of the tenth resistor and the first terminal of the third capacitor; the second terminal of the eleventh resistor and the second terminal of the third capacitor are grounded; the first and second input terminals of the sixth AND gate are both connected to the second terminal of the eighth resistor, and the output terminal of the sixth AND gate is connected to the first internal power transistor.

[0014] In some embodiments, the third driving module includes a third NOT gate, a seventh AND gate, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, an eighth capacitor, a tenth diode, and a ninth AND gate; the input terminal of the third NOT gate is connected to the driving signal output terminal of the first driving module, the output terminal of the third NOT gate is connected to the first input terminal of the seventh AND gate, and the second input terminal of the seventh AND gate is connected to a third pulse signal; the first terminal of the twentieth resistor is connected to the output terminal of the seventh AND gate, the first terminal of the twentieth resistor, and the anode of the tenth diode; the cathode of the tenth diode is connected to the first terminal of the twentieth resistor; the second terminal of the twentieth resistor is connected to the second terminal of the twentieth resistor and the first terminal of the eighth capacitor; the second terminal of the twentieth resistor and the second terminal of the eighth capacitor are grounded; the first and second input terminals of the ninth AND gate are both connected to the second terminal of the twentieth resistor, and the output terminal of the ninth AND gate is connected to the second internal power transistor.

[0015] In some embodiments, the fourth driving module includes a seventh diode, an eighth diode, a fourth NOT gate, a tenth AND gate, a thirteenth resistor, a seventeenth resistor, an eighteenth resistor, a seventh capacitor, a sixth diode, and a twelfth AND gate; the anode of the seventh diode is connected to the interlock signal output terminal of the second driving module, the anode of the eighth diode is connected to the driving signal output terminal of the second driving module, the cathode of the seventh diode is connected to the cathode of the eighth diode, the first terminal of the eighteenth resistor, and the input terminal of the fourth NOT gate, the second terminal of the eighteenth resistor is grounded, and the output terminal of the fourth NOT gate is connected to the first input terminal of the tenth AND gate. The first input terminal of the tenth AND gate is connected to the second input terminal of the tenth AND gate and the interlock signal output terminal of the third driving module; the first terminal of the thirteenth resistor is connected to the output terminal of the tenth AND gate, the first terminal of the seventeenth resistor and the cathode of the sixth diode, the second terminal of the thirteenth resistor is connected to the anode of the sixth diode and the first terminal of the seventh capacitor, and the second terminal of the seventeenth resistor and the second terminal of the seventh capacitor are grounded; the first input terminal of the twelfth AND gate is connected to the second terminal of the thirteenth resistor, the second input terminal of the twelfth AND gate is connected to the fourth pulse signal, and the output terminal of the twelfth AND gate is connected to the second external power transistor.

[0016] In some embodiments, the control module includes a fourth diode, a ninth diode, a thirty-third resistor, a second AND gate, a fifth AND gate, an eighth AND gate, an eleventh AND gate, and a thirteenth AND gate; the fault signal includes a first fault signal and a second fault signal; the cathode of the fourth diode is used to receive the first fault signal, the cathode of the ninth diode is used to receive the second fault signal, the anodes of the fourth and ninth diodes, the first terminal of the thirty-third resistor, and the first input terminal of the thirteenth AND gate are connected, the second terminal of the thirty-third resistor is connected to the input power supply, the second input terminal of the thirteenth AND gate is used to receive the enable signal, and the output terminal of the thirteenth AND gate is connected to the... The first input terminals of the second AND gate, the fifth AND gate, the eighth AND gate, and the eleventh AND gate are connected; the second input terminal of the second AND gate is connected to the output terminal of the first AND gate, the output terminal of the second AND gate is connected to the first terminal of the first resistor, the second input terminal of the fifth AND gate is connected to the output terminal of the fourth AND gate, the output terminal of the fifth AND gate is connected to the first terminal of the eighth resistor, the second input terminal of the eighth AND gate is connected to the output terminal of the seventh AND gate, the output terminal of the eighth AND gate is connected to the first terminal of the twentieth resistor, the second input terminal of the eleventh AND gate is connected to the output terminal of the tenth AND gate, and the output terminal of the eleventh AND gate is connected to the first terminal of the thirteenth resistor.

[0017] To solve the above-mentioned technical problems, another technical solution adopted by this utility model is to provide an energy storage power supply, including: a midpoint clamping three-level circuit; and the drive control circuit as described above.

[0018] The beneficial effects of this utility model embodiment are as follows: Unlike the prior art, this utility model embodiment can realize the drive protection of the NPC three-level circuit through pure hardware, without relying on software control, thus avoiding the complexity and reliability problems of software control; through the cooperation of cross-drive signal control and delay unit, the switching timing of the inner and outer tubes and complementary tubes is ensured, effectively preventing the risk of power tube shoot-through; and when a fault occurs or current limiting is required, the hardware dead-time control of the corresponding power tube can be realized, ensuring the safe and reliable operation of the NPC three-level circuit under various working states. Attached Figure Description

[0019] Figure 1 This is the circuit schematic of a Type I NPC three-level drive circuit;

[0020] Figure 2 This is a schematic diagram of the structure of a drive control circuit provided in an embodiment of the present invention;

[0021] Figure 3 This is a circuit diagram of a drive control circuit provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of another drive control circuit provided in an embodiment of the present invention;

[0023] Figure 5 This is a circuit diagram of another drive control circuit provided in an embodiment of the present utility model;

[0024] Figure 6 It is a waveform diagram of a pulse signal;

[0025] Figure 7 This is the waveform diagram of the first driving signal;

[0026] Figure 8 This is the waveform diagram of the fourth driving signal;

[0027] Figure 9 This is the waveform diagram of the second driving signal;

[0028] Figure 10 This is the waveform diagram of the third driving signal. Detailed Implementation

[0029] To facilitate understanding of this utility model, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this specification are for illustrative purposes only.

[0030] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0031] Figure 1This paper illustrates the circuit structure of a Type I NPC three-level circuit, where power transistors Q1 and Q4 are external power transistors, and power transistors Q2 and Q3 are internal power transistors. Power transistors Q1 and Q3 are complementary drive transistors, as are power transistors Q2 and Q4. During the turn-on process, the internal power transistors must turn on first, followed by the external power transistors, ensuring that both transistors bear half the bus voltage during turn-on. During the turn-off process, the external power transistors must turn off first, followed by the internal power transistors, ensuring that both transistors also bear half the bus voltage during turn-off, thus reducing transistor stress during turn-on and turn-off. The key problems that the Type I NPC three-level circuit urgently needs to solve are: firstly, the operating sequence of the internal and external power transistors during turn-on or turn-off to reduce transistor stress; secondly, the two complementary power transistors must not be turned on and off simultaneously to prevent shoot-through faults.

[0032] Please see Figure 2 The drive control circuit 100 provided in this embodiment of the present invention includes a first drive module 110, a second drive module 120, a third drive module 130 and a fourth drive module 140, and each drive module includes a delay unit.

[0033] Regarding the circuit connections, the output terminal of the first driving module 110 is electrically connected to the first external power transistor 310, the output terminal of the second driving module 120 is electrically connected to the first internal power transistor 320, the output terminal of the third driving module 130 is electrically connected to the second internal power transistor 330, and the output terminal of the fourth driving module 140 is electrically connected to the second external power transistor 340. The first external power transistor 310 and the second internal power transistor 330 form a first complementary pair, and the first internal power transistor 320 and the second external power transistor 340 form a second complementary pair. In this embodiment, a complementary pair refers to a pair of power transistors that need to be complementary in conduction within an NPC three-level circuit.

[0034] Regarding the cross-control of drive signals, the third input terminal of the first drive module 110 is connected to the output terminal of the third drive module 130 to receive the third drive signal for controlling the second internal power transistor 330; the first input terminal of the second drive module 120 is connected to the output terminal of the fourth drive module 140 to receive the fourth drive signal for controlling the second external power transistor 340; the first input terminal of the third drive module 130 is connected to the output terminal of the first drive module 110 to receive the first drive signal for controlling the first external power transistor 310; and the third input terminal of the fourth drive module 140 is connected to the output terminal of the second drive module 120 to receive the second drive signal for controlling the first internal power transistor 320.

[0035] For easier understanding, please refer to... Figure 5Regarding the transmission of interlock signals, the first drive module 110 further includes a first input terminal and a second input terminal, wherein the first input terminal is used to receive a first pulse signal Q1A0, and the second input terminal is used to receive a second interlock signal Q2B2. The first input terminal of the fourth drive module 140 is used to receive a fourth pulse signal Q2A0, and the second input terminal is used to receive a third interlock signal Q1B2.

[0036] Similarly, the second drive module 120 also includes a second input terminal, which is used to receive the second pulse signal Q2B0 and output the second interlock signal Q2B2; the third drive module 130 also includes a second input terminal, which is used to receive the third pulse signal Q1B0 and output the third interlock signal Q1B2. The first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal are the original signals output by the controller.

[0037] In the drive control circuit of this embodiment, the four drive modules achieve switching timing control of the inner and outer transistors and dead-time protection of the complementary transistors through the cooperation of the delay unit.

[0038] In this embodiment, the dead time of the drive signal of the complementary transistors is achieved through the cross-transmission of the drive signal and the delay effect of the delay unit. The working principle is illustrated using the complementary pair of the first external power transistor and the second internal power transistor as an example:

[0039] The first drive module 110 receives a third drive signal for controlling the second internal power transistor, and the third drive module 130 receives a first drive signal for controlling the first external power transistor. When the first drive signal drives the first external power transistor, it is simultaneously received by the third drive module 130. The delay unit in the third drive module 130 performs a delay processing on this signal and then outputs the third drive signal. Due to the effect of the delay unit, the third drive signal is time-delayed relative to the first drive signal; this delay time forms the dead time between the complementary transistors.

[0040] Similarly, the complementary control of the second internal power transistor and the first external power transistor also adopts a similar principle. The third drive signal, while driving the second internal power transistor, is also received by the first drive module 110. After being delayed by the delay unit in the first drive module 110, a drive signal for controlling the first external power transistor is output. This mechanism of signal cross-transmission and delay processing ensures that the complementary power transistors will not conduct simultaneously under any operating state.

[0041] Similarly, the second drive module 120 and the fourth drive module 140 also implement dead-time control of the complementary transistors through a similar signal cross-transmission and delay mechanism. Specifically, the second drive module 120 receives a fourth drive signal for controlling the second external power transistor, and the fourth drive module 140 receives a second drive signal for controlling the first internal power transistor.

[0042] When the second drive signal drives the first internal power transistor, the signal is simultaneously received by the fourth drive module 140. The delay unit in the fourth drive module 140 performs a delay processing on this signal before outputting the fourth drive signal. Due to the effect of the delay unit, the fourth drive signal is time-delayed relative to the second drive signal, creating a dead time between the first internal power transistor and the second external power transistor.

[0043] The reverse control process follows the same principle. The fourth drive signal, while driving the second external power transistor, is received by the second drive module 120. After being delayed by the delay unit in the second drive module 120, a drive signal for controlling the first internal power transistor is output. This bidirectional signal cross-transmission and delay processing mechanism ensures that there is a necessary dead time for both the first internal power transistor and the second external power transistor during any switching process, thereby avoiding shoot-through risk.

[0044] It's important to note that a delay unit refers to a circuit structure that can generate a specific delay for the input signal, typically implemented using an RC delay circuit. Dead time refers to the short period of time set to prevent two power transistors on the same bridge arm from conducting simultaneously (i.e., cross-conduction). During the dead time, the power devices on both the upper and lower bridge arms remain off, avoiding direct power supply short circuits. By using different delays generated by the delay unit, this time interval can be precisely controlled, ensuring the safety of power transistor switching without excessively affecting the system's dynamic response characteristics.

[0045] The following explains the implementation principle of the switching timing control of internal and external transistors:

[0046] First, for the first control unit group composed of the first driving module 110 and the second driving module 120, when the input level of the delay unit changes from high to low, the delay unit of the first driving module 110 outputs a first driving signal after a first delay time, and the delay unit of the second driving module 120 outputs a second driving signal after a second delay time, wherein the second delay time is greater than the first delay time. The delay difference between the first delay time and the second delay time ensures that during the level drop process, the first external power transistor turns off before the first internal power transistor. Conversely, when the input level of the delay unit changes from low to high, the delay unit of the first driving module 110 outputs a first driving signal after a third delay time, and the delay unit of the second driving module 120 outputs a second driving signal after a fourth delay time, wherein the third delay time is greater than the fourth delay time. The delay difference between the third delay time and the fourth delay time ensures that during the level rise process, the first internal power transistor turns on before the first external power transistor.

[0047] Similarly, the working principle of the second set of control units, consisting of the third drive module 130 and the fourth drive module 140, is similar to that of the first set of control units. When the input level of the delay unit changes from high to low, the delay unit of the third drive module 130 outputs the third drive signal after a fifth delay time, and the delay unit of the fourth drive module 140 outputs the fourth drive signal after a sixth delay time, where the sixth delay time is shorter than the fifth delay time. The delay difference between the fifth and sixth delay times ensures that the second external power transistor turns off before the second internal power transistor during the level drop process. When the input level of the delay unit changes from low to high, the delay unit of the third drive module 130 outputs the third drive signal after a seventh delay time, and the delay unit of the fourth drive module 140 outputs the fourth drive signal after an eighth delay time, where the seventh delay time is shorter than the eighth delay time. The delay difference between the seventh and eighth delay times ensures that the second internal power transistor turns on before the second external power transistor during the level rise process.

[0048] Please see Figure 3 This embodiment details the specific circuit structure of the drive control circuit.

[0049] The first driving module 110 includes a first diode D1, a third diode D3, a first NOT gate U2A, a first AND gate U1C, a first resistor R1, a sixth resistor R6, a fifth resistor R5, a second capacitor C2, a second diode D2, and a third AND gate U1A. The anode of the first diode D1 is interlocked with the output terminal of the third driving module 130 (i.e.,...). Figure 3 The output terminal of the seventh AND gate U4D is connected, and the anode of the third diode D3 is connected to the drive signal output terminal of the third drive module 130 (i.e., Figure 3The output terminal of the ninth AND gate U5A is connected. The cathodes of the first diode D1 and the third diode D3, the first terminal of the sixth resistor R6, and the input terminal of the first NOT gate U2A are connected, and the second terminal of the sixth resistor R6 is grounded. The output terminal of the first NOT gate U2A is connected to the first input terminal of the first AND gate U1C, and the second input terminal of the first AND gate U1C is connected to the interlock signal output terminal of the second drive module 120 (i.e., Figure 3 (The output of the fourth AND gate U1D is shown).

[0050] In the delay unit section of the first drive module 110, the first terminal of the first resistor R1 is connected to the output terminal of the first AND gate U1C, the first terminal of the fifth resistor R5, and the cathode of the second diode D2. The second terminal of the first resistor R1 is connected to the anode of the second diode D2 and the first terminal of the second capacitor C2. The second terminal of the fifth resistor R5 and the second terminal of the second capacitor C2 are grounded together. The first input terminal of the third AND gate U1A is connected to the second terminal of the first resistor R1. The second input terminal of the third AND gate U1A receives the first pulse signal. The output terminal of the third AND gate U1A is connected to the first external power transistor.

[0051] The second driving module 120 includes a second NOT gate U2B, a fourth AND gate U1D, an eighth resistor R8, a tenth resistor R10, an eleventh resistor R11, a third capacitor C3, a fifth diode D5, and a sixth AND gate U3A. The input terminal of the second NOT gate U2B is connected to the drive signal output terminal of the fourth driving module 140 (i.e.,...). Figure 3 The output of the twelfth AND gate U4A is connected to the output of the second NOT gate U2B, and the first input of the fourth AND gate U1D is connected to the second input of the fourth AND gate U1D. The second input of the fourth AND gate U1D receives the second pulse signal.

[0052] In the delay unit section of the second drive module 120, the first terminal of the eighth resistor R8 is connected to the output terminal of the fourth AND gate U1D, the first terminal of the eleventh resistor R11, and the anode of the fifth diode D5. The cathode of the fifth diode D5 is connected to the first terminal of the tenth resistor R10. The second terminal of the eighth resistor R8 is connected to the second terminal of the tenth resistor R10 and the first terminal of the third capacitor C3. The second terminal of the eleventh resistor R11 and the second terminal of the third capacitor C3 are grounded. Both input terminals of the sixth AND gate U3A are connected to the second terminal of the eighth resistor R8, and the output terminal of the sixth AND gate U3A is connected to the first internal power transistor.

[0053] The third driving module 130 includes a third NOT gate U2D, a seventh AND gate U4D, a twentieth resistor R20, a twenty-second resistor R22, a twenty-third resistor R23, an eighth capacitor C8, a tenth diode D10, and a ninth AND gate U5A. The input terminal of the third NOT gate U2D is connected to the drive signal output terminal of the first driving module 110 (i.e.,...). Figure 3The output of the third AND gate U1A is connected to the first input of the seventh AND gate U4D, and the second input of the seventh AND gate U4D receives the third pulse signal.

[0054] In the delay unit section of the third drive module 130, the first terminal of the twentieth resistor R20 is connected to the output terminal of the seventh AND gate U4D, the first terminal of the twenty-third resistor R23, and the anode of the tenth diode D10. The cathode of the tenth diode D10 is connected to the first terminal of the twenty-second resistor R22. The second terminal of the twentieth resistor R20 is connected to the second terminal of the twenty-second resistor R22 and the first terminal of the eighth capacitor C8. The second terminal of the twenty-third resistor R23 and the second terminal of the eighth capacitor C8 are grounded. Both input terminals of the ninth AND gate U5A are connected to the second terminal of the twentieth resistor R20, and the output terminal of the ninth AND gate U5A is connected to the second internal power transistor.

[0055] The fourth drive module 140 includes a seventh diode D7, an eighth diode D8, a fourth NOT gate U2C, a tenth AND gate U3C, a thirteenth resistor R13, a seventeenth resistor R17, an eighteenth resistor R18, a seventh capacitor C7, a sixth diode D6, and a twelfth AND gate U4A. The anode of the seventh diode D7 is interlocked with the output terminal of the second drive module 120 (i.e.,...). Figure 3 The output terminal of the fourth AND gate U1D is connected, and the anode of the eighth diode D8 is connected to the drive signal output terminal of the second drive module 120 (i.e., Figure 3 The output of the sixth AND gate U3A is connected. The cathodes of the seventh diode D7 and the eighth diode D8, the first terminal of the eighteenth resistor R18, and the input of the fourth NOT gate U2C are connected, and the second terminal of the eighteenth resistor R18 is grounded. The output of the fourth NOT gate U2C is connected to the first input of the tenth AND gate U3C, and the second input of the tenth AND gate U3C is connected to the interlock signal output of the third drive module 130 (i.e., Figure 3 Connect the output terminal of the seventh AND gate U4D shown.

[0056] In the delay unit section of the fourth drive module 140, the first terminal of the thirteenth resistor R13 is connected to the output terminal of the tenth AND gate U3C, the first terminal of the seventeenth resistor R17, and the cathode of the sixth diode D6. The second terminal of the thirteenth resistor R13 is connected to the anode of the sixth diode D2 and the first terminal of the seventh capacitor C7, while the second terminal of the seventeenth resistor R17 and the second terminal of the seventh capacitor C7 are grounded. The first input terminal of the twelfth AND gate U4A is connected to the second terminal of the thirteenth resistor R13, the second input terminal of the twelfth AND gate U4A receives the fourth pulse signal, and the output terminal of the twelfth AND gate U4A is connected to the second external power transistor.

[0057] In this embodiment, the four driving modules achieve dead-time control and switching timing control of the power transistors through careful circuit structure design. Each driving module includes a signal processing unit and a delay unit. The signal processing unit consists of NOT gates, AND gates, and diodes, while the delay unit is implemented by an RC delay circuit.

[0058] Taking the operation of the first driving module as an example, its signal processing unit receives an interlock signal and a driving signal from the third driving module. These two signals are first leveled by a diode-OR gate composed of a first diode, a third diode, and a sixth resistor, and then inverted by a first NOT gate. The processed signal is then logically operated with the interlock signal from the second driving module in a first AND gate to form a control signal. This control signal then enters a delay unit, where an RC circuit composed of a first resistor, a fifth resistor, and a second capacitor generates a specific delay. Finally, the delayed signal is logically operated with a first pulse signal through a third AND gate to generate the final control signal used to drive the first external power transistor.

[0059] In terms of dead-time control of complementary power transistors, dead time is generated through signal cross-transmission and delay. For example, the output signal of the first driver module is received by the third driver module while driving the first external power transistor. This signal is processed by an RC delay circuit in the third driver module, generating a certain time delay before driving the second internal power transistor, thus forming the dead time between the complementary transistors. This hardware-based dead-time control scheme avoids the timing uncertainties that may occur in traditional software control schemes.

[0060] The switching timing control of the internal and external transistors mainly relies on the proper configuration of the RC parameters in the delay unit. When the input level of the delay unit changes, different RC time constants will cause different delays in the output signal. By designing the RC parameters, it is ensured that the external transistor turns off before the internal transistor during the turn-off process, and the internal transistor turns on before the external transistor during the turn-on process, thereby reducing the switching stress on the power transistors.

[0061] It should be noted that the RC delay circuit in this embodiment not only implements the basic delay function, but also utilizes the unidirectional conduction characteristic of the diode to allow for separate adjustment of the capacitor's charging and discharging times. This enables independent control of the rise and fall edge delay times, providing greater flexibility for precise control of the power transistor. Furthermore, by adjusting the values ​​of the resistor and capacitor, the dead time can be easily optimized, minimizing the impact on the system's dynamic performance while ensuring a safety margin.

[0062] Unlike existing technologies, this utility model embodiment can achieve the driving protection of NPC three-level circuits through pure hardware, without relying on software control, thus avoiding the complexity and reliability issues of software control; through the cooperation of cross-drive signal control and delay unit, the switching timing of internal and external transistors and complementary transistors is ensured, effectively preventing the risk of power transistor shoot-through.

[0063] This application also provides another drive control circuit, please refer to [link / reference]. Figure 4 This embodiment adds a wave-by-wave current limiting function to the aforementioned drive control circuit to achieve a more complete drive protection function. The drive control circuit includes a first drive module 110, a second drive module 120, a third drive module 130, a fourth drive module 140, and a control module 150.

[0064] Regarding the basic connection relationships, the first drive module 110 is electrically connected to the first external power transistor 310, the second drive module 120 is electrically connected to the first internal power transistor 320, the third drive module 130 is electrically connected to the second internal power transistor 330, and the fourth drive module 140 is electrically connected to the second external power transistor 340. The first external power transistor 310 and the second internal power transistor 330 form a first complementary pair, and the first internal power transistor 320 and the second external power transistor 340 form a second complementary pair.

[0065] The control module 150 is electrically connected to the control terminals of the first drive module 110, the second drive module 120, the third drive module 130, and the fourth drive module 140 via its output terminals. The input terminals of the control module 150 are used to receive control signals, including but not limited to enable signals, fault signals, and current limiting signals. By receiving and processing these control signals, the control module 150 can output a wave-locked control signal to uniformly regulate the operating status of each drive module.

[0066] Regarding the cross-control of drive signals, the first drive module 110 receives a third drive signal for controlling the second internal power transistor 330, the second drive module 120 receives a fourth drive signal for controlling the second external power transistor 340, the third drive module 130 receives a first drive signal for controlling the first external power transistor 310, and the fourth drive module 140 receives a second drive signal for controlling the first internal power transistor 320.

[0067] Regarding the transmission of the interlock signal, the first drive module 110 includes a first input terminal and a second input terminal, wherein the first input terminal is used to receive a first pulse signal and the second input terminal is used to receive a second interlock signal. The input terminal of the second drive module 120 is used to receive the second pulse signal and output the second interlock signal. Similarly, the input terminal of the third drive module 130 is used to receive a third pulse signal and output a third interlock signal, and the first and second input terminals of the fourth drive module 140 are used to receive a fourth pulse signal and the third interlock signal, respectively.

[0068] As the core control unit of the system, the control module 150 monitors the operating status of the NPC three-level drive circuit in real time by receiving enable signals, fault signals, and current limiting signals. When any control signal received by the control module 150 is low, such as when a fault occurs or current limiting is required, the control module 150 will output a low-level wave-locking control signal. The wave-locking control signal simultaneously acts on the control terminals of the four drive modules, triggering corresponding protection actions.

[0069] Under normal operating conditions, when all control signals are high, the wave lock control signal remains high, and the four drive modules operate normally according to the preset timing sequence. At this time, the drive control circuit mainly performs two key functions: switching timing control of the internal and external transistors and dead-time protection of the complementary transistors.

[0070] Regarding the switching timing control of the inner and outer transistors, when the input level of the delay unit changes from high to low, the NPC three-level drive circuit ensures that the outer transistor turns off before the inner transistor through different delay times. Specifically, the delay unit of the first drive module 110 outputs a first drive signal after a first delay time, and the delay unit of the second drive module 120 outputs a second drive signal after a second delay time, where the second delay time is greater than the first delay time. When the input level of the delay unit changes from low to high, a similar mechanism ensures that the inner transistor turns on before the outer transistor, at which point the third delay time is greater than the fourth delay time.

[0071] In terms of dead-time protection for complementary transistors, dead time is generated through the cross-transmission and delay of drive signals. For example, the first drive signal is received by the third drive module while controlling the first external power transistor, and after processing by the delay unit, the third drive signal is output, thereby creating the necessary dead time between the complementary power transistors. The hardware-based dead-time control scheme features high reliability and fast response speed.

[0072] When an abnormal condition occurs in the NPC three-level drive circuit, the control module 150 responds quickly. For example, upon detecting an overcurrent or overvoltage fault, the fault signal goes low, and the control module 150 immediately outputs a low-level latching control signal. Upon receiving this signal, each drive module generates a different delay through its respective delay unit to ensure that the power transistors are turned off in a safe sequence: first the outer transistor turns off, then the inner transistor turns off. This orderly turn-off process effectively reduces the switching stress on the power transistors.

[0073] Similarly, when the NPC three-level drive circuit needs to perform wave-by-wave current limiting, changes in the current limiting signal will also trigger a similar protection mechanism. By adjusting the RC parameters of the delay unit, precise control of the power transistor switching process can be achieved, ensuring both the timeliness of the protection action and avoiding any additional stress that may be introduced during the protection process.

[0074] Please see Figure 5 This embodiment details the specific circuit structure of the drive control circuit including the control module. Based on the circuit structure of the aforementioned embodiments, the focus is on describing the detailed composition of the control module.

[0075] The control module includes a fourth diode D4, a ninth diode D9, a thirty-third resistor R33, a second AND gate U1B, a fifth AND gate U3B, an eighth AND gate U4B, an eleventh AND gate U3D, and a thirteenth AND gate U4C. The cathode of the fourth diode D4 receives the first fault signal, and the cathode of the ninth diode D9 receives the second fault signal. The anodes of the fourth and ninth diodes D9, the first terminal of the thirty-third resistor R33, and the first input terminal of the thirteenth AND gate U4C are connected. The second terminal of the thirty-third resistor R33 is connected to the +5V input power supply, and the second input terminal of the thirteenth AND gate U4C receives the enable signal.

[0076] Regarding the signal transmission path, the output of the thirteenth AND gate U4C is connected to the first input of the second AND gate U1B, the first input of the fifth AND gate U3B, the first input of the eighth AND gate U4B, and the first input of the eleventh AND gate U3D, respectively. This parallel connection ensures that the control signal can be applied to each drive module simultaneously.

[0077] Regarding the connections to the various driver modules, the second input of the second AND gate U1B is connected to the output of the first AND gate U1C, and the output of the second AND gate U1B is connected to the first terminal of the first resistor R1. The second input of the fifth AND gate U3B is connected to the output of the fourth AND gate U1D, and the output of the fifth AND gate U3B is connected to the first terminal of the eighth resistor R8. The second input of the eighth AND gate U4B is connected to the output of the seventh AND gate U4D, and the output of the eighth AND gate U4B is connected to the first terminal of the twentieth resistor R20. The second input of the eleventh AND gate U3D is connected to the output of the tenth AND gate U3C, and the output of the eleventh AND gate U3D is connected to the first terminal of the thirteenth resistor R13.

[0078] This circuit achieves unified management and protection of the four drive modules through a control module. The control module adopts a pure hardware logic circuit design, mainly composed of diodes and AND gates. The number of diodes can be increased according to actual needs. Corresponding hardware fault signals are input, enabling real-time monitoring of enable and fault signals.

[0079] Under normal operating conditions, both the enable and fault signals are high. At this time, the diode AND gate formed by the fourth diode D4, the ninth diode D9, and the thirty-third resistor R33 outputs a high level. This high-level signal is logically processed by the thirteenth AND gate U4C, outputting a high-level signal. This high-level signal is simultaneously transmitted to the second AND gate U1B, the fifth AND gate U3B, the eighth AND gate U4B, and the eleventh AND gate U3D, enabling the four drive modules to operate normally.

[0080] When a system malfunctions, the control module responds immediately. For example, when an overcurrent or overvoltage fault is detected, the corresponding fault signal goes low. The diode AND gate formed by the fourth diode D4, the ninth diode D9, and the thirty-third resistor R33 outputs a low-level signal due to the presence of a low-level input. This low-level signal is transmitted to each drive module through the four AND gates, triggering the protection action.

[0081] During abnormal shutdown, the four drive modules respond to the low-level signal from the control module. Through the action of their respective delay units, they ensure that the power transistors are turned off in a safe sequence: first the external transistor turns off, followed by the internal transistor.

[0082] It is important to note that this control scheme employs a multi-stage AND gate structure, ensuring reliable transmission of control signals. For example, the second AND gate U1B receives control signals from both the thirteenth AND gate U4C and the first AND gate U1C. Only when both signals are simultaneously high will the second AND gate U1B output a high level, driving the corresponding power transistor to conduct.

[0083] Similarly, the control module uses a similar mechanism to process the enable signal. When the enable signal is low, regardless of the fault signal state, the thirteenth AND gate U4C will output a low level to ensure that the system can be safely shut down, effectively preventing the power transistor from being damaged due to improper control timing.

[0084] The control module works in tandem with the dead-time control and switching timing control described in the aforementioned embodiments. During normal operation, each drive module generates the necessary dead-time and switching delay through the delay unit; under abnormal conditions, the control module ensures that the system can quickly and safely enter the protection state. This collaborative working mechanism significantly improves the reliability and safety of the system.

[0085] Specifically, the first external power transistor and the second internal power transistor are complementary driver transistors, driving Q1A and Q1B respectively; the first internal power transistor and the second external power transistor are complementary driver transistors, driving Q2A and Q2B respectively. Normal operation is as follows: Figure 8 As shown, Q1A0 and Q1B0 are PWM signals generated by the control circuit. Q1A is in a high-frequency switching state for half a cycle and in a low-level state for the other half; Q1B is in a high-level state for half a cycle and in a high-frequency switching state for the other half; Q2A is in a high-frequency switching state for half a cycle and in a low-level state for the other half; Q2B is in a high-level state for half a cycle and in a high-frequency switching state for the other half.

[0086] like Figure 6 The driving waveform shown, under normal power-on and fault-free conditions, the control module outputs a constant high INVSD signal (the result of ANDing the enable signal and the fault signal, given to the locking unit of each driving module; the enable signal and the fault signal come from the fault detection module and MCU within the system; the fault signal is 0 when there is a fault and 1 when working normally; the enable signal is 0 when there is a fault and 1 when working normally). Taking a positive half-wave as an example, under normal driving, Q2B is constantly high, and Q1B0 can obtain Q1B1 through the delay unit of the third driving module (the turn-on and turn-off delay time can be adjusted according to RC; Q1A0, Q1B0, Q2A0, and Q2B0 are the original PWM signals, and Q1A1, Q1B1, Q2A1, and Q2B1 are the signals that actually control the switching transistors to turn on and off through the logic circuit). Third drive The input and output signals of the module's delay unit can be obtained through the first NOT gate U2A. Q1B0+Q1B1 Finally, Q1A1 can be obtained through the delay unit of the first driving module. Figure 7 It can be seen that Q1A1 and Q1B1 have hardware dead times. Similarly, under negative half-cycle operation, Q2A1 and Q2B1 can also have hardware dead times, such as... Figure 8 As shown.

[0087] like Figure 6 The driving waveform shown indicates that under normal power-on and fault-free conditions, the control module outputs a constant high INVSD signal. Taking a positive half-wave as an example, under normal drive, Q2B is constantly high, and Q1A is also high. However, if an overcurrent or overvoltage fault occurs in the circuit, INVSD will go low. At this time, Q1A0 and Q1B0 will be fault-locked (fault signal ERRn). Figure 5 The diagram shows only two ERR signals. The number of fault signals can be increased according to actual needs, which will output 0. The output of the AND gate formed by the diode resistor is 0. When ANDed with the enable signal IO_EN (U4C), the output INVSD will be 0. After receiving the INVSD lock signal, the corresponding AND gates (U1B, U3B, U3D, U4B) all output 0 (PWM11, PWM21, PWM31, PWM41 are all low). Based on the different delay settings of the delay units in the first and second drive modules (specifically depending on the RC device parameters to ensure the switching order of the internal and external transistors), Q1A0 is immediately locked to become Q1A1, and Q2B0 is discharged after an RC delay to become Q2B1, thus achieving the first external power transistor turning off before the first internal power transistor. When the fault is cleared and the INVSD lock signal goes high, Q1A0 is locked by the delay unit of the first drive module and released after a longer delay to become Q1A1, while Q2B0 is locked by the delay unit of the second drive module and released after a shorter delay to become Q2B1, thus achieving the first internal power transistor turning on before the first external power transistor. Figure 9 As shown; similarly, it can also be seen that the second external power transistor turns off before the second internal power transistor, and the second internal power transistor turns on before the second external power transistor, as shown. Figure 10 As shown.

[0088] When the INVSD signal is used as a hardware-based current limiter, the delay setting for wave-by-wave current limiting and release can be achieved by adjusting the RC constant when the inverter is under impulsive load (in the wave-by-wave current limiting function, the current limiting signal and the fault signal are connected to the control module together; when the current limiting point is reached, the current limiting signal is set to 0, the corresponding AND result is 0, and the output INVSD is 0. After passing through the wave-locking unit and the delay unit, it drives the switching transistor to operate). Additionally, the control module adds an IO enable power-on control function, which can ensure wave locking when the IO state is unstable during power-on, thus enabling power-on. It can also implement software-based wave-by-wave current limiting based on the fault signal bit toggling generated by the circuit and sent to the MCU, simultaneously operating under the same conditions as INVSD to meet the operating requirements of both internal and external switching transistors.

[0089] Unlike existing technologies, this utility model embodiment can achieve the drive protection of the NPC three-level circuit through pure hardware, without relying on software control, thus avoiding the complexity and reliability issues of software control. Through the cooperation of cross-drive signal control and delay unit, the switching timing of the inner and outer transistors and complementary transistors is ensured, effectively preventing the risk of power transistor shoot-through. Furthermore, in the event of a fault or when current limiting is required, hardware dead-time control of the corresponding power transistor can be achieved, ensuring the safe and reliable operation of the NPC three-level circuit under various operating conditions.

[0090] It should be noted that while the preferred embodiments of this utility model are provided in the specification and accompanying drawings, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are not intended to impose additional limitations on the content of this utility model; their purpose is to provide a more thorough and comprehensive understanding of the disclosure of this utility model. Furthermore, the above-described technical features can be combined with each other to form various embodiments not listed above, all of which are considered to be within the scope of this utility model specification. Moreover, those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A drive control circuit, applied to a midpoint clamping three-level circuit, characterized in that, include: The first driving module, the second driving module, the third driving module, and the fourth driving module, each of the driving modules including a delay unit; The first driving module and the second driving module are respectively connected to the first external power transistor and the first internal power transistor; the third driving module and the fourth driving module are respectively connected to the second internal power transistor and the second external power transistor. Wherein, the first external power transistor and the second internal power transistor form a first complementary pair, and the first internal power transistor and the second external power transistor form a second complementary pair; The first driving module receives a third driving signal for controlling the second internal power transistor, and the second driving module receives a fourth driving signal for controlling the second external power transistor; the third driving module receives a first driving signal for controlling the first external power transistor, and the fourth driving module receives a second driving signal for controlling the first internal power transistor. The first driving module and the third driving module generate dead time through their respective delay units, and the second driving module and the fourth driving module generate dead time through their respective delay units.

2. The circuit according to claim 1, characterized in that, The first driving module further includes a first input terminal and a second input terminal, wherein the first input terminal is used to receive a first pulse signal and the second input terminal is used to receive a second interlock signal; The second driving module further includes a second input terminal, which is used to receive the second pulse signal and output the second interlock signal; In response to the second interlock signal, the first driving module and the second driving module control the first external power transistor to turn off before the first internal power transistor and the first internal power transistor to turn on before the first external power transistor through their respective delay units.

3. The circuit according to claim 1, characterized in that, The third driving module further includes a second input terminal, which is used to receive a third pulse signal and output a third interlock signal. The fourth driving module further includes a first input terminal and a second input terminal, wherein the first input terminal is used to receive a fourth pulse signal and the second input terminal is used to receive the third interlock signal. In response to the third interlock signal, the third driving module and the fourth driving module control the second external power transistor to turn off before the second internal power transistor and the second internal power transistor to turn on before the second external power transistor through their respective delay units.

4. The circuit according to claim 2, characterized in that, When the input level of the delay unit of the first driving module changes from high to low, the first driving signal is output after a first delay time; when the input level of the delay unit of the second driving module changes from high to low, the second driving signal is output after a second delay time; wherein, the second delay time is greater than the first delay time. When the input level of the delay unit of the first driving module changes from low to high, the first driving signal is output after a third delay time; when the input level of the delay unit of the second driving module changes from low to high, the second driving signal is output after a fourth delay time; wherein the third delay time is greater than the fourth delay time.

5. The circuit according to claim 3, characterized in that, When the input level of the delay unit of the third driving module changes from high to low, the third driving signal is output after a fifth delay time; when the input level of the delay unit of the fourth driving module changes from high to low, the fourth driving signal is output after a sixth delay time; wherein, the sixth delay time is shorter than the fifth delay time. When the input level of the delay unit of the third driving module changes from low to high, the third driving signal is output after a seventh delay time; when the input level of the delay unit of the fourth driving module changes from low to high, the fourth driving signal is output after an eighth delay time; wherein the seventh delay time is less than the eighth delay time.

6. The circuit according to claim 4 or 5, characterized in that, It also includes a control module, which is connected to the control terminals of the first drive module, the second drive module, the third drive module, and the fourth drive module; The control module is used to receive at least one control signal and output a wave-locking control signal based on the level state of the control signal; the control signal includes at least one of the following: an enable signal, a fault signal, and a current limiting signal; The first driving module, the second driving module, the third driving module, and the fourth driving module respond to the level state of the wave lock control signal and adjust the conduction state of the corresponding power transistor through their respective delay units; The delay unit generates different delay times based on the level transition of the wave lock control signal, so that the corresponding power transistors switch their working states according to a preset conduction sequence.

7. The circuit according to claim 4 or 5, characterized in that, The first driving module includes a first diode, a third diode, a first NOT gate, a first AND gate, a first resistor, a sixth resistor, a fifth resistor, a second capacitor, a second diode, and a third AND gate; The anode of the first diode is connected to the interlock signal output terminal of the third driving module, the anode of the third diode is connected to the driving signal output terminal of the third driving module, the cathode of the first diode is connected to the cathode of the third diode, the first terminal of the sixth resistor and the input terminal of the first NOT gate, the second terminal of the sixth resistor is grounded, the output terminal of the first NOT gate is connected to the first input terminal of the first AND gate, and the second input terminal of the first AND gate is connected to the interlock signal output terminal of the second driving module. The first terminal of the first resistor is connected to the output terminal of the first AND gate, the first terminal of the fifth resistor and the cathode of the second diode, the second terminal of the first resistor is connected to the anode of the second diode and the first terminal of the second capacitor, and the second terminal of the fifth resistor and the second terminal of the second capacitor are grounded. The first input terminal of the third AND gate is connected to the second terminal of the first resistor, the second input terminal of the third AND gate is connected to the first pulse signal, and the output terminal of the third AND gate is connected to the first external power transistor.

8. The circuit according to claim 1, characterized in that, The second driving module includes a second NOT gate, a fourth AND gate, an eighth resistor, a tenth resistor, an eleventh resistor, a third capacitor, a fifth diode, and a sixth AND gate; The input terminal of the second NOT gate is connected to the drive signal output terminal of the fourth drive module, the output terminal of the second NOT gate is connected to the first input terminal of the fourth AND gate, and the second input terminal of the fourth AND gate is connected to the second pulse signal. The first terminal of the eighth resistor is connected to the output terminal of the fourth AND gate, the first terminal of the eleventh resistor, and the anode of the fifth diode. The cathode of the fifth diode is connected to the first terminal of the tenth resistor. The second terminal of the eighth resistor, the second terminal of the tenth resistor, and the first terminal of the third capacitor are connected. The second terminal of the eleventh resistor and the second terminal of the third capacitor are grounded. The first and second input terminals of the sixth AND gate are both connected to the second terminal of the eighth resistor, and the output terminal of the sixth AND gate is connected to the first internal power transistor.

9. The circuit according to claim 1, characterized in that, The third driving module includes a third NOT gate, a seventh AND gate, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, an eighth capacitor, a tenth diode, and a ninth AND gate; The input terminal of the third NOT gate is connected to the drive signal output terminal of the first drive module, the output terminal of the third NOT gate is connected to the first input terminal of the seventh AND gate, and the second input terminal of the seventh AND gate is connected to the third pulse signal. The first terminal of the twentieth resistor is connected to the output terminal of the seventh AND gate, the first terminal of the twentieth resistor and the anode of the tenth diode, the cathode of the tenth diode is connected to the first terminal of the twentieth resistor, the second terminal of the twentieth resistor is connected to the second terminal of the twentieth resistor and the first terminal of the eighth capacitor, and the second terminal of the twentieth resistor and the second terminal of the eighth capacitor are grounded. The first and second input terminals of the ninth AND gate are both connected to the second terminal of the twentieth resistor, and the output terminal of the ninth AND gate is connected to the second internal power transistor.

10. The circuit according to claim 1, characterized in that, The fourth driving module includes a seventh diode, an eighth diode, a fourth NOT gate, a tenth AND gate, a thirteenth resistor, a seventeenth resistor, an eighteenth resistor, a seventh capacitor, a sixth diode, and a twelfth AND gate; The anode of the seventh diode is connected to the interlock signal output terminal of the second driving module, the anode of the eighth diode is connected to the driving signal output terminal of the second driving module, the cathode of the seventh diode is connected to the cathode of the eighth diode, the first terminal of the eighteenth resistor and the input terminal of the fourth NOT gate, the second terminal of the eighteenth resistor is grounded, the output terminal of the fourth NOT gate is connected to the first input terminal of the tenth AND gate, and the second input terminal of the tenth AND gate is connected to the interlock signal output terminal of the third driving module. The first terminal of the thirteenth resistor is connected to the output terminal of the tenth AND gate, the first terminal of the seventeenth resistor and the cathode of the sixth diode, the second terminal of the thirteenth resistor is connected to the anode of the sixth diode and the first terminal of the seventh capacitor, and the second terminal of the seventeenth resistor and the second terminal of the seventh capacitor are grounded. The first input terminal of the twelfth AND gate is connected to the second terminal of the thirteenth resistor, the second input terminal of the twelfth AND gate is connected to the fourth pulse signal, and the output terminal of the twelfth AND gate is connected to the second external power transistor.

11. The circuit according to claim 6, characterized in that, The control module includes a fourth diode, a ninth diode, a thirty-third resistor, a second AND gate, a fifth AND gate, an eighth AND gate, an eleventh AND gate, and a thirteenth AND gate; the fault signals include a first fault signal and a second fault signal. The cathode of the fourth diode is used to receive the first fault signal, the cathode of the ninth diode is used to receive the second fault signal, the anode of the fourth diode and the anode of the ninth diode, the first terminal of the thirty-third resistor and the first input terminal of the thirteenth AND gate are connected, the second terminal of the thirty-third resistor is connected to the input power supply, the second input terminal of the thirteenth AND gate is used to receive the enable signal, and the output terminal of the thirteenth AND gate is connected to the first input terminal of the second AND gate, the first input terminal of the fifth AND gate, the first input terminal of the eighth AND gate and the first input terminal of the eleventh AND gate respectively. The second input terminal of the second AND gate is connected to the output terminal of the first AND gate, the output terminal of the second AND gate is connected to the first terminal of the first resistor, the second input terminal of the fifth AND gate is connected to the output terminal of the fourth AND gate, the output terminal of the fifth AND gate is connected to the first terminal of the eighth resistor, the second input terminal of the eighth AND gate is connected to the output terminal of the seventh AND gate, the output terminal of the eighth AND gate is connected to the first terminal of the twentieth resistor, the second input terminal of the eleventh AND gate is connected to the output terminal of the tenth AND gate, and the output terminal of the eleventh AND gate is connected to the first terminal of the thirteenth resistor.

12. An energy storage power source, characterized in that, include: Midpoint clamping three-level circuit; And, the drive control circuit as described in any one of claims 1-11.

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