Frequency doubling circuit
By replacing the XOR gate with a cross-coupled pair of transistors and an inverter, the double frequency circuit structure is simplified, the complexity caused by the large number of components is solved, and a double frequency signal output with smaller chip area and lower noise is achieved.
Patent Information
- Application Number
- CN202423323814.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Traditional frequency doubling circuits have many components, resulting in a complex circuit structure.
By replacing the XOR gate with two pairs of cross-coupled transistors and an inverter, a frequency doubling circuit is generated, reducing the number of components and making the structure simpler and more reliable.
It achieves reduced components, simplified circuit structure, compatibility with various process feature sizes, reduced noise interference, and increased maximum input operating frequency.
Smart Images
Figure CN223843752U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, specifically to a frequency doubling circuit. Background Technology
[0002] Frequency doubling circuits are widely used in integrated circuit design, generating twice the input clock frequency through a single circuit module. The core of most implementations is an XOR gate logic unit. The XOR gate has two input branches: IN2 has no delay, and IN1 has a delay of 1 / 4 of the input clock signal period. This delay is designed to generate twice the clock cycle with a 50% duty cycle at the output. The XOR gate is generated using traditional gate-level combinational logic. A traditional XOR gate circuit uses four two-input NAND gates. The input-output signal relationship of a traditional frequency doubling circuit is as follows: when the two input branches of the XOR gate have the same level, the output is low; when the two input branches have opposite levels, the output is high.
[0003] However, using XOR gates to implement a frequency doubling circuit requires more components, resulting in a more complex circuit structure. Utility Model Content
[0004] In view of this, this application provides a frequency doubling circuit, which reduces the number of components required for the frequency doubling circuit and has a simpler and more reliable structure. The technical solution is as follows.
[0005] In a first aspect, a frequency doubling circuit is provided, wherein a first input terminal of the circuit is connected to a first node; a second input terminal of the circuit is connected to a second node; and the second input terminal is also connected to a third node via a first inverter.
[0006] The second node is connected to the output terminal of the circuit via a first switch; the first node is connected to the output terminal of the circuit via a second switch; the first node is also connected to the output terminal of the circuit via a third switch; the third node is also connected to the output terminal of the circuit via a fourth switch.
[0007] The first node is connected to the control terminals of the second and fourth switching transistors respectively; the second node is connected to the control terminal of the first switching transistor; the third node is connected to the control terminal of the third switching transistor; there is a 1 / 4 cycle delay between the signals of the first input terminal and the second input terminal.
[0008] In one possible implementation, the first and second switches are PMOS transistors; the third and fourth switches are NMOS transistors.
[0009] In one possible implementation, the first switch and the second switch are PMOS transistors with the same parameters; the third switch and the fourth switch are NMOS transistors with the same parameters.
[0010] In one possible implementation, the output of the circuit is low when the first input terminal and the second input terminal are both low.
[0011] In one possible implementation, the output of the circuit is low when the first input terminal and the second input terminal are at high levels.
[0012] In one possible implementation, the output of the circuit is high when the first input is low and the second input is high.
[0013] In one possible implementation, the output of the circuit is high when the first input is high and the second input is low.
[0014] In one possible implementation, the signal at the first input lags behind the signal at the second input by 1 / 4 cycle.
[0015] In one possible implementation, the clock signal terminal of the circuit is connected to the input terminal of the delay unit via a second inverter; the output terminal of the delay unit is connected to the first input terminal via a third inverter.
[0016] The clock signal terminal of the circuit is also connected to the second input terminal in sequence through a fourth inverter and a fifth inverter.
[0017] In one possible implementation, the output of the circuit is also connected to a second-harmonic signal via a sixth inverter and a seventh inverter.
[0018] The technical solution provided in this application may include the following beneficial effects:
[0019] This application provides a frequency doubler circuit. The circuit's first input terminal is connected to a first node; its second input terminal is connected to a second node; the second input terminal is also connected to a third node via a first inverter; the second node is connected to the circuit's output terminal via a first switch; the first node is connected to the circuit's output terminal via a second switch; the first node is also connected to the circuit's output terminal via a third switch; and the third node is also connected to the circuit's output terminal via a fourth switch. The first node is connected to the control terminals of both the second and fourth switches; the second node is connected to the control terminal of the first switch; and the third node is connected to the control terminal of the third switch. There is a 1 / 4 cycle delay between the signals at the first and second input terminals. This circuit eliminates the need for traditional gate circuits; two pairs of cross-coupled transistors and an inverter can replace the XOR gate function, thus generating a frequency doubler circuit. This reduces the number of components required for the frequency doubler circuit, resulting in a simpler and more reliable structure. Attached Figure Description
[0020] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0021] Figure 1 A schematic diagram of a frequency doubling circuit based on an XOR gate is shown.
[0022] Figure 2 It shows Figure 1 The input-output signal relationship diagram of the corresponding frequency doubling circuit.
[0023] Figure 3 A circuit diagram of a frequency doubling circuit according to an embodiment of this application is shown. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0025] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.
[0026] Please refer to Figure 1 This illustrates a schematic diagram of a frequency doubling circuit based on an XOR gate. For example... Figure 1 As shown, this XOR gate circuit has two input branches. One, IN2, has no delay, while the other, IN1, has a delay of 1 / 4 of the input clock signal period. This delay is intended to generate twice the clock cycle with a 50% duty cycle at the output. Figure 1 In this circuit, four two-input NAND gates are used to form a traditional XOR gate circuit.
[0027] Please refer to Figure 2 It shows Figure 1 The corresponding input-output signal relationship diagram of the frequency doubling circuit. (See diagram below.) Figure 2 As shown, when the two input branches of the XOR gate have the same level, the output is low. When the two input branches of the XOR gate have opposite levels, the output is high.
[0028] The frequency doubling circuit shown in the embodiments of this application can be implemented without using logic gate circuits, reducing the number of components required for the frequency doubling circuit and making the structure simpler and more reliable.
[0029] Please refer to Figure 3 The diagram illustrates a circuit structure of a frequency doubling circuit according to an embodiment of this application. Figure 3 As shown, the first input terminal IN1 of the circuit is connected to the first node; the second input terminal IN2 of the circuit is connected to the second node; the second input terminal IN2 is also connected to the third node through the first inverter A1;
[0030] The second node is connected to the output terminal of the circuit via the first switch P1; the first node is connected to the output terminal of the circuit via the second switch P2; the first node is also connected to the output terminal of the circuit via the third switch N1; the third node is also connected to the output terminal of the circuit via the fourth switch N2.
[0031] The first node is connected to the control terminals of the second switch P2 and the fourth switch N2 respectively; the second node is connected to the control terminal of the first switch P1; the third node is connected to the control terminal of the third switch N1; and there is a 1 / 4 cycle delay between the signals of the first input terminal and the second input terminal.
[0032] Optionally, in this embodiment, the first switch P1 and the second switch P2 are PMOS transistors; the third switch N1 and the fourth switch N2 are NMOS transistors.
[0033] Furthermore, the first switch P1 and the second switch P2 are PMOS transistors with the same parameters; the third switch N1 and the fourth switch N2 are NMOS transistors with the same parameters.
[0034] Furthermore, the clock signal terminal of the circuit is connected to the input terminal of the delay unit via the second inverter A2; the output terminal of the delay unit is connected to the first input terminal via the third inverter A3.
[0035] The clock signal terminal of the circuit is also connected to the second input terminal in sequence through the fourth inverter A4 and the fifth inverter A5.
[0036] Furthermore, the output of this circuit is connected to a second-harmonic signal via a sixth inverter A6 and a seventh inverter A7.
[0037] In this embodiment, two inverters are used multiple times to flip the signal twice. This restores the original shape of the potentially distorted signal while maintaining the signal level order, thus reducing circuit interference. A specific delay, such as a 1 / 4 cycle delay, is introduced between the two inverters to match the timing requirements of the frequency doubling circuit.
[0038] At this time, when the first input terminal and the second input terminal are both low, that is, both the first input terminal IN1 and the second input terminal IN2 are low, one NMOS transistor is turned off, namely the fourth switch N2. The other three MOS transistors are turned on, namely the first switch P1, the second switch P2, and the third switch N1. The input to the left of these three transistors is the IN1 signal, so the combined output of the two pairs of cross-coupled transistors is the OUT1 signal, and the output terminal (OUT) of the circuit is low.
[0039] When the first input is low and the second input is high, the first input IN1 is low and the second input IN2 is high. At this time, three MOSFETs are off: the second switch P2, the third switch N1, and the fourth switch N2. Only the first switch P1 is on. Therefore, the output OUT1 of the upper cross-coupled pair is equal to the level of the second input IN2, i.e., high. The lower cross-coupled pair has no output, and the output of this circuit is high.
[0040] When the first input terminal is low and the second input terminal is high (i.e., the first input terminal IN1 is high and the second input terminal IN2 is low), one PMOS transistor is off (the first switch P1). Three transistors are on: the second switch P2, the third switch N1, and the fourth switch N2. The output of the upper cross-coupled pair is high. The output of the lower cross-coupled pair is also high, resulting in a high-level output for the circuit.
[0041] When both the first and second input terminals are high (i.e., both IN1 and IN2 are high), three MOSFETs are off: P2, N1, and N2. Only one MOSFET is on: P1. The output of the upper cross-coupled pair is low, and the lower cross-coupled pair has no output; therefore, the circuit's output is low.
[0042] The two pairs of cross-coupled transistors and one inverter mentioned in this application, totaling six MOSFETs, replace the XOR gate function to generate a frequency doubling circuit, which can perform the function of... Figure 1 The frequency doubler circuit shown has the same input clock frequency doubler function. Furthermore, the core of the frequency doubler circuit proposed in this application consists of only two pairs of cross-coupled transistors, making it suitable for CMOS processes with various feature sizes. Its ingenious and simple structure allows for a smaller chip area.
[0043] Furthermore, both pairs of cross-coupled transistors are used as direct input / output switches, thus being compatible with signals of various input frequencies, and even allowing for higher maximum input operating frequencies. These two pairs of cross-coupled transistors are not in direct contact with the circuit power supply, resulting in less interference from power supply noise and consequently lower noise in the output double-frequency signal.
[0044] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0045] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A frequency doubling circuit, characterized in that, The first input terminal of the circuit is connected to the first node; the second input terminal of the circuit is connected to the second node; the second input terminal is also connected to the third node via the first inverter; The second node is connected to the output terminal of the circuit via a first switch; the first node is connected to the output terminal of the circuit via a second switch; the first node is also connected to the output terminal of the circuit via a third switch; the third node is also connected to the output terminal of the circuit via a fourth switch. The first node is connected to the control terminals of the second and fourth switching transistors respectively; the second node is connected to the control terminal of the first switching transistor; the third node is connected to the control terminal of the third switching transistor; there is a 1 / 4 cycle delay between the signals of the first input terminal and the second input terminal.
2. The circuit according to claim 1, characterized in that, The first and second switching transistors are PMOS transistors; the third and fourth switching transistors are NMOS transistors.
3. The circuit according to claim 2, characterized in that, The first and second switching transistors are PMOS transistors with the same parameters; the third and fourth switching transistors are NMOS transistors with the same parameters.
4. The circuit according to claim 3, characterized in that, When the first input terminal and the second input terminal are at low level, the output terminal of the circuit is at low level.
5. The circuit according to claim 3, characterized in that, When the first input terminal and the second input terminal are at high level, the output terminal of the circuit is at low level.
6. The circuit according to claim 3, characterized in that, When the first input terminal is low and the second input terminal is high, the output terminal of the circuit is high.
7. The circuit according to claim 3, characterized in that, When the first input terminal is high and the second input terminal is low, the output terminal of the circuit is high.
8. The circuit according to any one of claims 1 to 7, characterized in that, The signal at the first input terminal lags behind the signal at the second input terminal by 1 / 4 cycle.
9. The circuit according to claim 8, characterized in that, The clock signal terminal of the circuit is connected to the input terminal of the delay unit through a second inverter; the output terminal of the delay unit is connected to the first input terminal through a third inverter. The clock signal terminal of the circuit is also connected to the second input terminal in sequence through a fourth inverter and a fifth inverter.
10. The circuit according to claim 8, characterized in that, The output of the circuit is also connected to a second-harmonic signal via a sixth inverter and a seventh inverter.