Display panel and display device

Abstract

The utility model provides a display panel and a display device, the display panel comprises a source drain electrode layer, a flat layer, a common electrode layer, a passivation layer and a pixel electrode layer, and the source drain electrode layer is provided with a first surface and a second surface which are oppositely arranged; the flat layer is arranged on the first surface; the common electrode layer is arranged on one side, far away from the source and drain electrode layer, of the flat layer; the passivation layer is arranged on one side, far away from the flat layer, of the common electrode layer; the pixel electrode layer is arranged on one side, far away from the common electrode layer, of the passivation layer; wherein a first via hole is formed in the flat layer, a second via hole is formed in the passivation layer and the flat layer, the common electrode layer extends along the second via hole and is connected with the source and drain electrode layer through the first via hole, and the pixel electrode layer is connected with the common electrode layer through the second via hole. The problem that the connection effect between the pixel electrode layer and the common electrode layer and the source and drain electrode layer in the display panel becomes poor is solved, and therefore the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a display panel and display device. Background Technology

[0002] LTPS stands for Low-Temperature Polycrystalline Silicon, a high-performance thin-film transistor technology widely used in display technologies such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). LTPS technology offers advantages such as fast response, low power consumption, high resolution, vibrant colors, and reduced eye strain.

[0003] Due to the aforementioned technical characteristics, low-temperature polysilicon (LTPS) technology is frequently used in high-end display panels. However, despite these advantages, the LTPS process involves numerous steps, particularly the use of a relatively thick PLN (planarization) layer. This results in a deterioration in the connection between the subsequent pixel electrode layer, common electrode layer, and source / drain electrode layer, thus affecting the display performance.

[0004] Therefore, providing a display panel and display device that improves display performance has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] This application provides a display panel and a display device.

[0006] This application provides a display panel including a source / drain layer, a planarization layer, a common electrode layer, a passivation layer, and a pixel electrode layer. The source / drain layer has a first surface and a second surface disposed opposite to each other. The planarization layer is disposed on the first surface. The common electrode layer is disposed on the side of the planarization layer away from the source / drain layer. The passivation layer is disposed on the side of the common electrode layer away from the planarization layer. The pixel electrode layer is disposed on the side of the passivation layer away from the common electrode layer. The planarization layer has a first via, and the passivation layer and the planarization layer have a second via. The common electrode layer extends along the second via and is connected to the source / drain layer through the first via. The pixel electrode layer is connected to the common electrode layer through the second via.

[0007] In some embodiments, a semiconductor layer is further included, the semiconductor layer being located on the second side of the source-drain layer, the common electrode layer being connected to the semiconductor layer through the first via, and the semiconductor layer being connected to the source-drain layer.

[0008] In some embodiments, an insulating layer and an interlayer insulating layer are further included, the insulating layer and the interlayer insulating layer being disposed between the source / drain layer and the semiconductor layer, the insulating layer being close to the source / drain layer and the interlayer insulating layer being close to the semiconductor layer, and the first via passing through the insulating layer and the interlayer insulating layer.

[0009] In some embodiments, the semiconductor layer includes a polysilicon conductor layer, a doped layer, and a polysilicon semiconductor layer. The doped layer is located outside the polysilicon semiconductor layer, and the polysilicon conductor layer is located outside the doped layer. A first via is connected to the polysilicon conductor layer. A third via is provided in the insulating layer and the interlayer insulating layer. The source and drain layers are connected to the polysilicon conductor layer through the third via.

[0010] In some embodiments, the opening width of the second via gradually decreases from the passivation layer toward the planarization layer.

[0011] In some embodiments, the first via extends into the planarization layer by a distance not exceeding half the thickness of the planarization layer.

[0012] In some embodiments, the first through hole is a circular hole.

[0013] In some embodiments, a gate layer is further included, the gate layer being located between the insulating layer and the planarization layer.

[0014] In some embodiments, the system further includes a substrate, a light-blocking layer, and a protective layer, wherein the protective layer is located on the side of the semiconductor layer away from the source / drain layer, the light-blocking layer is located on the side of the protective layer away from the semiconductor layer, and the substrate is located on the side of the light-blocking layer away from the protective layer.

[0015] Another embodiment of this application provides a display device, including the display panel described in the above embodiments.

[0016] This application provides a display panel including a source / drain layer, a planarization layer, a common electrode layer, a passivation layer, and a pixel electrode layer. The source / drain layer has a first surface and a second surface disposed opposite to each other. The planarization layer is disposed on the first surface. The common electrode layer is disposed on the side of the planarization layer away from the source / drain layer. The passivation layer is disposed on the side of the common electrode layer away from the planarization layer. The pixel electrode layer is disposed on the side of the passivation layer away from the common electrode layer. The planarization layer has a first via, and the passivation layer and planarization layer have second vias. The common electrode layer extends along the second via and connects to the source / drain layer through the first via. The pixel electrode layer is connected to the common electrode layer through the second via. The planarization layer is connected to the source / drain layer through the first via, the passivation layer and planarization layer are connected to the common electrode layer through the second via, and the pixel electrode layer is connected to the common electrode layer through the second via. These technical features, through a reasonable interlayer connection design, solve the problem of deteriorated connection effect between the pixel electrode layer and the common electrode layer and the source / drain layer in the display panel, thereby improving the display effect. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the display device structure provided in an embodiment of this application.

[0020] 100 Display panel, 10 Source / drain layer, 10a First surface, 10b Second surface, 20 Planarization layer, 30 Common electrode layer, 40 Passivation layer, 50 Pixel electrode layer, 101 First via, 102 Second via, 60 Semiconductor layer, 61 Polysilicon conductor layer, 62 Doped layer, 63 Polysilicon semiconductor layer, 70 Insulating layer, 80 Interlayer insulating layer, 103 Third via, 90 Gate layer, 105 Substrate, 106 Light blocking layer, 107 Protective layer. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0022] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0025] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0026] This application provides a display panel and a display device.

[0027] Please see Figure 1 This application provides a display panel 100, including a source / drain layer 10, a planarization layer 20, a common electrode layer 30, a passivation layer 40, and a pixel electrode layer 50. The source / drain layer 10 has a first surface 10a and a second surface 10b disposed opposite to each other; the planarization layer 20 is disposed on the first surface 10a; the common electrode layer 30 is disposed on the side of the planarization layer 20 away from the source / drain layer 10; the passivation layer 40 is disposed on the side of the common electrode layer 30 away from the planarization layer 20; and the pixel electrode layer 50 is disposed on the side of the passivation layer 40 away from the common electrode layer 30. The planarization layer 20 has a first via 101, and the passivation layer 40 and the planarization layer 20 have a second via 102. The common electrode layer 30 extends along the second via 102 and is connected to the source / drain layer 10 through the first via 101. The pixel electrode layer 50 is connected to the common electrode layer 30 through the second via 102. The planarization layer 20 is connected to the source / drain layer 10 through a first via 101, the passivation layer 40 and the planarization layer 20 are connected to the common electrode layer 30 through a second via 102, and the pixel electrode layer 50 is connected to the common electrode layer 30 through a second via 102. These technical features, through a reasonable interlayer connection design, solve the problem of deteriorated connection between the pixel electrode layer 50 and the common electrode layer 30 and the source / drain layer 10 in the display panel 100, thereby improving the display effect.

[0028] Wherein, the first surface 10a is the upper surface of the source-drain layer 10, and the second surface 10b is the lower surface of the source-drain layer 10. Of course, the positions of the first surface 10a and the second surface 10b can be interchanged according to actual needs. In this embodiment, unless otherwise specified, the first surface 10a is the upper surface of the source-drain layer 10 by default.

[0029] Compared with the prior art, this application provides a first via 101 in the planarization layer 20, allowing the common electrode layer 30 to connect to the source / drain layer 10 through the first via 101. Simultaneously, a second via 102 is provided in the passivation layer 40 and the planarization layer 20, allowing the common electrode layer 30 to extend along the second via 102 and connect to the source / drain layer 10 through the first via 101. The pixel electrode layer 50 connects to the common electrode layer 30 through the second via 102. This design effectively solves the problem of deteriorated connection between the pixel electrode layer 50, the common electrode layer 30, and the source / drain layer 10, thus improving the display effect.

[0030] Furthermore, this application also proposes that the display panel 100 further includes a semiconductor layer located on the second surface 10b of the source-drain layer 10, and the common electrode layer 30 is connected to the semiconductor layer through a first via 101, and the semiconductor layer is connected to the source-drain layer 10.

[0031] This application includes a semiconductor layer disposed on the second surface 10b of the source / drain layer 10, and a common electrode layer 30 connected to the semiconductor layer through a first via 101. The semiconductor layer is connected to the source / drain layer 10. The semiconductor layer can be made of various materials and structures; for example, polysilicon can be used as the semiconductor material, or the semiconductor layer can be designed as a multilayer structure, including a polysilicon conductor layer 61, a doped layer, and a polysilicon semiconductor layer 63. To further improve the connection effect, an insulating layer and an interlayer insulating layer 80 can be disposed between the source / drain layer 10 and the semiconductor layer, with the insulating layer close to the source / drain layer 10 and the interlayer insulating layer 80 close to the semiconductor layer. The first via 101 can pass through the insulating layer and the interlayer insulating layer 80, and connect to the common electrode layer 30 through the polysilicon conductor layer 61. In addition, the shape and size of the via can be optimized according to specific needs; for example, a circular via structure can be used, and the extension distance of the via does not exceed half the thickness of the planarization layer 20.

[0032] This application solves the problem of poor connection between the planarization layer 20, passivation layer 40, and source / drain layer 10 in the prior art by adding a semiconductor layer to the second surface 10b of the source / drain layer 10 and connecting it to the common electrode layer 30 through a first via 101. Compared with the prior art, this application enhances the conductivity between the common electrode layer 30 and the source / drain layer 10, thereby improving the connection effect and display performance of the display panel 100. Therefore, this application provides an improved display panel 100 structure with better connection effect and display performance.

[0033] Furthermore, this application also proposes to include an insulating layer 70 and an interlayer insulating layer 80, which are disposed between the source / drain layer 10 and the semiconductor layer. The insulating layer 70 is close to the source / drain layer 10, and the interlayer insulating layer 80 is close to the semiconductor layer. A first via 101 passes through the insulating layer 70 and the interlayer insulating layer 80. These technical features, through mutual cooperation, form an effective electrical connection between the source / drain layer 10 and the semiconductor layer, thereby solving the connection problem and improving the display effect of the display panel 100. The insulating layer 70 and the interlayer insulating layer 80 can be disposed in various ways. For example, the insulating layer 70 can be made of silicon dioxide or silicon nitride, and the interlayer insulating layer 80 can be made of aluminum oxide or other dielectric materials. The first via 101 can be manufactured using conventional semiconductor processing techniques such as photolithography and etching. Specifically, the size and location of the first via 101 need to be optimized based on the specific structure and material properties of the source / drain layer 10 and the semiconductor layer to ensure the reliability and stability of the electrical connection. As a preferred embodiment, the diameter of the first via 101 can be between 0.1 micrometers and 5 micrometers to accommodate the design requirements of different display panels 100.

[0034] By setting an insulating layer 70 and an interlayer insulating layer 80, and forming a first via 101 thereon, this application achieves an effective electrical connection between the source / drain layer 10 and the semiconductor layer. This structure not only improves the reliability of the electrical connection but also reduces resistance and parasitic capacitance, thereby enhancing the overall performance of the display panel 100. Compared with the prior art, the technical solution of this application is more structurally reasonable and has a simpler manufacturing process, making it suitable for various high-end display panel 100 application scenarios. Therefore, this application improves display performance while also helping to reduce production costs and complexity.

[0035] Furthermore, this application proposes that the semiconductor layer includes a polysilicon conductor layer 61, a doped layer, and a polysilicon semiconductor layer 63. The doped layer is located outside the polysilicon semiconductor layer 63, and the polysilicon conductor layer 61 is located outside the doped layer. A first via 101 is connected to the polysilicon conductor layer 61. A third via 103 is provided on the insulating layer and the interlayer insulating layer 80, and the source / drain layer 10 is connected to the polysilicon conductor layer 61 through the third via 103. The semiconductor layer includes a polysilicon conductor layer 61, a doped layer, and a polysilicon semiconductor layer 63. These layers are arranged in a specific manner such that the polysilicon conductor layer 61 is on the outermost side, the doped layer is in the middle, and the polysilicon semiconductor layer 63 is on the innermost side. The first via 101 is connected to the polysilicon conductor layer 61 to ensure effective transmission of electrical signals. The third via 103 is provided on the insulating layer and the interlayer insulating layer 80, and the source / drain layer 10 is connected to the polysilicon conductor layer 61 through the third via 103. The purpose of this design is to ensure that the polysilicon conductor layer 61 can be effectively connected to the source / drain layer 10, solving the connection problem between the polysilicon semiconductor layer 63 and the source / drain layer 10, thereby improving the performance of the display panel 100. The polysilicon conductor layer 61 is on the outermost side of the semiconductor layer, the doped layer is in the middle, and the polysilicon semiconductor layer 63 is on the innermost side. This hierarchical structure enables good electrical signal transmission. The first via 101 is connected to the polysilicon conductor layer 61, allowing electrical signals to be effectively transmitted from the polysilicon conductor layer 61 to other layers. A third via 103 is provided in the insulating layer and the interlayer insulating layer 80, through which the source / drain layer 10 is connected to the polysilicon conductor layer 61, thus achieving an effective connection between the source / drain layer 10 and the polysilicon conductor layer 61. Specifically, this design can be implemented in various ways, such as using different materials and processes to optimize the via fabrication, to ensure the accuracy and reliability of the vias. This application achieves an effective connection between the source / drain layer 10 and the polysilicon conductor layer 61 by introducing a polysilicon conductor layer 61, a doped layer, and a polysilicon semiconductor layer 63 into the semiconductor layer, and by providing a first via 101 and a third via 103. Compared with the prior art, the design of this application improves the efficiency of electrical signal transmission, solves the connection problem between the polysilicon semiconductor layer 63 and the source / drain layer 10, and further enhances the performance of the display panel 100.

[0036] Furthermore, this application proposes that the opening width of the second via 102 gradually decreases from the passivation layer 40 towards the planarization layer 20. By designing the opening width of the second via 102 to gradually decrease from the passivation layer 40 towards the planarization layer 20, the connection between the pixel electrode layer 50 and the common electrode layer 30 and the source / drain layer 10 can be effectively improved. This design makes the connection between the electrode layers tighter and more stable, thereby improving the display effect.

[0037] Specifically, the opening width of the second via 102 gradually decreases from the passivation layer 40 towards the planarization layer 20. This design allows for a tighter contact between the common electrode layer 30 and the pixel electrode layer 50 when they connect to the source / drain layer 10 through the via, reducing resistance at the connection point and improving the stability and reliability of the electrical connection. Furthermore, this design can reduce poor contact between electrode layers, thereby improving the overall display effect of the display panel 100. For example, in actual manufacturing, the parameters of the etching process can be controlled to create a gradually decreasing opening width for the second via 102 between the passivation layer 40 and the planarization layer 20. As a preferred embodiment, appropriate etching solution and etching time can be selected to ensure that the opening width of the via meets the design requirements. In addition, the design of the etching mask can be optimized to make the shape of the via more regular, thereby further improving the connection effect. Therefore, the design of the second via 102, with its opening width gradually decreasing from the passivation layer 40 towards the planarization layer 20, not only effectively solves the problem of poor electrode layer connection caused by the relatively thick planarization layer 20, but also significantly improves the display effect of the display panel 100. Compared with the prior art, this application provides a simple and effective solution through optimized via design, demonstrating significant technological advancement and practicality.

[0038] Furthermore, this application proposes that the distance by which the first via 101 extends into the planarization layer 20 does not exceed half the thickness of the planarization layer 20. This technical solution plays a role in solving the problem of the thickness of the planarization layer 20 limiting the extension distance of the first via 101 in the display panel 100. By limiting the extension distance of the first via 101 into the planarization layer 20 to no more than half the thickness of the planarization layer 20, the increased manufacturing difficulty and structural instability caused by excessive via depth can be effectively avoided, thereby improving the overall display effect of the display panel 100. This technical approach can be implemented in various ways. For example, the first via 101 can be achieved by precisely controlling the etching depth to ensure that its extension distance does not exceed half the thickness of the planarization layer 20. In addition, the via depth can also be controlled by adjusting the exposure and development parameters in the photolithography process. As a preferred embodiment, the first via 101 can be designed as a circular hole, which makes it easier to control its depth and shape, further improving the stability and reliability of the manufacturing process. Through the aforementioned technical means, this application effectively solves the problem of the thickness of the planarization layer 20 in the display panel 100 limiting the extension distance of the first via 101. Compared with the prior art, the technical solution of this application has the advantages of low manufacturing difficulty and high structural stability, thereby significantly improving the overall display effect of the display panel 100.

[0039] Furthermore, this application proposes that the first via 101 be a circular hole. The technical solution of this application, by designing the first via 101 as a circular hole, improves processing accuracy and stability, reduces connection defects caused by irregular via shapes, thereby improving the connection effect between the source / drain layer 10 and the planarization layer 20, and ultimately improving the display effect of the display panel 100. The circular design of the first via 101 can be achieved in various ways. Specifically, high-precision laser drilling technology or precision die stamping can be used. Laser drilling technology can ensure the consistency of the via diameter and the smoothness of the edges, while die stamping can maintain a consistent via shape in mass production. In addition, chemical etching technology can be used to achieve precise processing of the circular hole by controlling the etching time and solution concentration. As a preferred embodiment, the material selection for the planarization layer 20 can be optimized, selecting materials with good processing performance and stability, such as polyimide or other polymer materials, to further ensure the processing quality of the circular hole. By designing the first via 101 as a circular hole, this application effectively solves the problem of poor connection effect caused by unreasonable via shape in the prior art. Compared with the prior art, this application not only improves the processing accuracy and stability of the via, but also significantly improves the connection effect between the source / drain layer 10 and the planarization layer 20, thereby improving the overall display effect of the display panel 100. Therefore, this application has significant technical advantages in the manufacturing process and performance optimization of the display panel 100.

[0040] Furthermore, this application proposes that the display panel 100 also includes a gate layer 90, which is located between the insulating layer and the planarization layer 20. Specifically, the gate layer 90 can be made of various materials, such as metals or conductive oxides, to ensure good conductivity and stability. The thickness and position of the gate layer 90 can be adjusted according to actual needs to optimize the performance and reliability of the display panel 100. As a preferred embodiment, the gate layer 90 can be deposited by processes such as sputtering or chemical vapor deposition (CVD) to ensure good bonding with surrounding layers. Compared with the prior art, this application significantly improves the connection effect between layers and the overall structural stability of the display panel 100 by adding a gate layer 90 between the insulating layer and the planarization layer 20. This solves the problem of poor connection effect caused by the thickness of the planarization layer 20, thereby improving the display effect and the reliability of the panel.

[0041] Furthermore, this application proposes that the display panel 100 also includes a substrate 105, a light-blocking layer 106, and a protective layer 107. The protective layer 107 is located on the side of the semiconductor layer away from the source / drain layer 10, the light-blocking layer 106 is located on the side of the protective layer 107 away from the semiconductor layer, and the substrate 105 is located on the side of the light-blocking layer 106 away from the protective layer 107. The substrate 105, light-blocking layer 106, and protective layer 107 in this application play a crucial role in solving the problem of deteriorated connectivity. The protective layer 107, located on the side of the semiconductor layer away from the source / drain layer 10, provides protection; the light-blocking layer 106, located on the side of the protective layer 107 away from the semiconductor layer, further optimizes electrical performance; and the substrate 105, located on the side of the light-blocking layer 106 away from the protective layer 107, provides structural support. Through the synergy of these technical features, the problem of deteriorated connectivity caused by the thick planarization layer 20 is effectively solved, thereby improving the display effect. The protective layer 107 can be made of materials such as silicon oxide and silicon nitride, possessing excellent insulation and protective properties. The light-blocking layer 106: When light enters polycrystalline silicon, it generates photogenerated carriers, affecting the activity of the semiconductor layer; therefore, a light-blocking layer is formed to prevent photogenerated carriers. The substrate 105 can be made of materials such as glass or plastic to ensure the mechanical strength and stability of the entire display panel 100. Through the application of these technical features, this application provides an effective solution to the problem of deteriorated connection between the pixel electrode layer 50 and the common electrode layer 30 and the source / drain layer 10 in the low-temperature polycrystalline silicon display panel 100 due to the thick planarization layer 20. Compared with the prior art, this application, by introducing the protective layer 107, the light-blocking layer 106, and the substrate 105, not only improves the connection effect of the display panel 100 but also further optimizes the electrical performance and structural stability, thereby significantly improving the display effect.

[0042] Please see Figure 2 Another embodiment of this application also provides a display device 1000, including the display panel 100 described in the above embodiments. Since the display panel 100 has been described in detail in the above embodiments, the display panel 100 in this application will not be described in detail again.

[0043] The display panel and display device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: The source-drain layer has a first surface and a second surface that are arranged opposite to each other. A planarization layer is disposed on the first surface; A common electrode layer is disposed on the side of the planar layer away from the source and drain electrode layers; A passivation layer is disposed on the side of the common electrode layer away from the planarization layer. A pixel electrode layer is disposed on the side of the passivation layer away from the common electrode layer; The planarization layer is provided with a first via, the passivation layer and the planarization layer are provided with a second via, the common electrode layer extends along the second via and is connected to the source and drain electrode layers through the first via, and the pixel electrode layer is connected to the common electrode layer through the second via.

2. The display panel according to claim 1, characterized in that, It also includes a semiconductor layer located on the second side of the source-drain layer, and the common electrode layer is connected to the semiconductor layer through the first via. The semiconductor layer is connected to the source-drain layer.

3. The display panel according to claim 2, characterized in that, It also includes an insulating layer and an interlayer insulating layer, which are disposed between the source / drain layer and the semiconductor layer. The insulating layer is close to the source / drain layer, and the interlayer insulating layer is close to the semiconductor layer. The first via passes through the insulating layer and the interlayer insulating layer.

4. The display panel according to claim 3, characterized in that, The semiconductor layer includes a polysilicon conductor layer, a doped layer, and a polysilicon semiconductor layer. The doped layer is located outside the polysilicon semiconductor layer, and the polysilicon conductor layer is located outside the doped layer. The first via is connected to the polysilicon conductor layer. The insulating layer and the interlayer insulating layer are provided with a third via. The source and drain layers are connected to the polysilicon conductor layer through the third via.

5. The display panel according to claim 1, characterized in that, The opening width of the second via gradually decreases from the passivation layer toward the planarization layer.

6. The display panel according to claim 1, characterized in that, The first via extends into the planarization layer by a distance not exceeding half the thickness of the planarization layer.

7. The display panel according to claim 6, characterized in that, The first through hole is a round hole.

8. The display panel according to claim 4, characterized in that, It also includes a gate layer located between the insulating layer and the planarization layer.

9. The display panel according to claim 8, characterized in that, It also includes a substrate, a light-blocking layer, and a protective layer, wherein the protective layer is located on the side of the semiconductor layer away from the source-drain layer, the light-blocking layer is located on the side of the protective layer away from the semiconductor layer, and the substrate is located on the side of the light-blocking layer away from the protective layer.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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