Vertical interconnection ceramic packaging substrate

Abstract

The utility model provides a vertical interconnection ceramic packaging substrate. The vertical interconnection ceramic package substrate comprises a first ceramic core plate, a second ceramic core plate, a first through hole, a second through hole, a first metal seed layer, a second metal seed layer, a first metal column, a second metal column, a first conductive pad, a second conductive pad, a first solder mask layer, a second solder mask layer, a first metal bump, a second metal bump and a filling layer, the first metal bumps on the bottom surface of the first ceramic core plate and the second metal bumps on the top surface of the second ceramic core plate are directly aligned and connected to realize electric connection between the first ceramic core plate and the second ceramic core plate, so that the vertically interconnected ceramic packaging substrate structure is realized, and the high-frequency performance of the packaging substrate is improved; according to the high-density packaging substrate, the number of interconnection lines, interconnection resistance and parasitic effect are reduced, signal delay is shortened, noise and loss are reduced, the signal transmission speed is further improved, and the complexity and cost of the high-density packaging substrate are effectively reduced.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a vertical interconnect ceramic packaging substrate. Background Technology

[0002] As electronic packaging technology gradually develops towards miniaturization, high integration, multi-functionality, and high reliability, how to select appropriate packaging materials and processes to improve the heat dissipation capacity of devices has become a technical problem faced in the development of electronic devices. Existing packaging substrates usually use organic substrates and form 2D packaging structures through redistribution layers. This makes the packaging cost of the packaging substrate high and the chip transmission distance long, resulting in large resistance and parasitic effects, leading to problems such as high noise, slow signal transmission speed, and delay.

[0003] Therefore, how to provide a vertical interconnect ceramic packaging substrate to reduce interconnect lines, reduce resistance and parasitic effects, reduce noise and loss, and improve signal transmission speed has become an important problem that needs to be solved by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Utility Model Content

[0005] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide a vertical interconnect ceramic packaging substrate to solve the problems of high resistance and parasitic effects, high noise and loss, slow signal transmission speed and delay in the prior art packaging substrate.

[0006] To achieve the above and other related objectives, this utility model provides a vertical interconnect ceramic packaging substrate, characterized in that it comprises:

[0007] A first ceramic core plate and a second ceramic core plate, wherein the first ceramic core plate has a first through hole and a first metal seed layer is provided on the sidewall of the first through hole; and the second ceramic core plate has a second through hole and a second metal seed layer is provided on the sidewall of the second through hole.

[0008] A first metal pillar and a second metal pillar, wherein the first metal pillar is located in the first through hole and the second metal pillar is located in the second through hole, and the first metal pillar is provided with a first conductive pad at both ends and the second metal pillar is provided with a second conductive pad at both ends.

[0009] A first solder resist layer and a second solder resist layer, wherein the first solder resist layer is located on the top and bottom surfaces of the first ceramic core board, and the second solder resist layer is located on the top and bottom surfaces of the second ceramic core board, and the first solder resist layer has a first opening that exposes the first conductive pad, and the second solder resist layer has a second opening that exposes the second conductive pad.

[0010] A first metal bump and a second metal bump, wherein the first metal bump is located in the first opening and the second metal bump is located in the second opening, and the first metal bump located on the bottom surface of the first ceramic core plate and the second metal bump located on the top surface of the second ceramic core plate are aligned and connected to each other.

[0011] A filler layer is located in the gap between the first solder mask layer and the second solder mask layer.

[0012] Optionally, the thickness of the first ceramic core plate is in the range of 100μm to 300μm, and the thickness of the second ceramic core plate is in the range of 100μm to 300μm.

[0013] Optionally, the width of the first ceramic core plate is in the range of 21mm to 17mm, the length of the first ceramic core plate is in the range of 21mm to 17mm, the width of the second ceramic core plate is in the range of 21mm to 17mm, and the length of the second ceramic core plate is in the range of 21mm to 17mm.

[0014] Optionally, the diameter of the first through hole is in the range of 50μm to 80μm, and the diameter of the second through hole is in the range of 50μm to 80μm.

[0015] Optionally, the longitudinal cross-sectional shape of the first through hole is X-shaped, and the longitudinal cross-sectional shape of the second through hole is X-shaped.

[0016] Optionally, the first metal seed layer includes a first metal transition layer and a first metal conductive layer stacked sequentially, and the second metal seed layer includes a second metal transition layer and a second metal conductive layer stacked sequentially.

[0017] Optionally, the diameter of the first conductive pad is in the range of 50μm to 100μm, the spacing between the first conductive pads is in the range of 150μm to 120μm, the diameter of the second conductive pad is in the range of 50μm to 100μm, and the spacing between the second conductive pads is in the range of 150μm to 120μm.

[0018] Optionally, the diameter of the first opening is in the range of 50 μm to 80 μm, and the diameter of the second opening is in the range of 50 μm to 80 μm.

[0019] Optionally, the first metal bump includes a first metal block and a first solder bump located above the first metal block, and the second metal bump includes a second metal block and a second solder bump located above the second metal block.

[0020] Optionally, the filler layer includes one of a silicone layer and an epoxy resin layer.

[0021] As described above, the vertical interconnect ceramic packaging substrate of this utility model includes a first ceramic core plate, a second ceramic core plate, a first through hole, a second through hole, a first metal seed layer, a second metal seed layer, a first metal pillar, a second metal pillar, a first conductive pad, a second conductive pad, a first solder mask layer, a second solder mask layer, a first metal bump, a second metal bump, and a filler layer. The first metal bump on the bottom surface of the first ceramic core plate and the second metal bump on the top surface of the second ceramic core plate are directly aligned and connected to achieve electrical connection between the first and second ceramic core plates. This realizes a vertical interconnect ceramic packaging substrate structure, improves the high-frequency performance of the packaging substrate, reduces the number of interconnect lines, thereby reducing interconnect resistance and parasitic effects, shortens signal delay, reduces noise and loss, and further improves signal transmission speed. Simultaneously, it effectively reduces the complexity and cost of high-density packaging substrates. Attached Figure Description

[0022] Figure 1 The diagram shown is a structural schematic of a vertical interconnect ceramic packaging substrate according to this utility model.

[0023] Figure 2 This is a schematic diagram of another structure of the vertical interconnect ceramic packaging substrate of this utility model.

[0024] Figure 3 The diagram shows a ceramic core board structure in a method for fabricating a vertically interconnected ceramic packaging substrate.

[0025] Figure 4 This diagram illustrates the structure obtained after forming a metal seed layer in a method for fabricating a vertically interconnected ceramic packaging substrate.

[0026] Figure 5 This diagram illustrates the structure obtained after forming a metal layer in a method for fabricating a vertically interconnected ceramic packaging substrate.

[0027] Figure 6 This diagram illustrates the structure obtained after forming metal pillars and metal bumps in a method for fabricating a vertical interconnect ceramic packaging substrate.

[0028] Figure 7 This diagram illustrates the structure obtained after forming a solder resist layer in a method for fabricating a vertical interconnect ceramic packaging substrate.

[0029] Figure 8 This diagram illustrates the structure obtained after metal bumping in a method for fabricating a vertical interconnect ceramic packaging substrate.

[0030] Figure 9 The diagram shows a unit ceramic substrate obtained by cutting during a method for fabricating a vertical interconnect ceramic packaging substrate.

[0031] Figure 10 The diagram shows a vertical interconnect ceramic package substrate formed in a method for manufacturing a vertical interconnect ceramic package substrate.

[0032] Explanation of reference numerals in the attached figures

[0033] 1 First ceramic core plate

[0034] 2 Second ceramic core plate

[0035] 3 First Metal Column

[0036] 4 Second metal column

[0037] 5 First solder mask layer

[0038] 6 Second solder resist layer

[0039] 7 First metal bump

[0040] 8 Second metal bump

[0041] 9. Filler layer

[0042] 10 First Metal Seed Layer

[0043] 11 Second metal seed layer

[0044] 12 First conductive pad

[0045] 13 Second conductive pad

[0046] 14-unit ceramic substrate

[0047] 15 Ceramic core board

[0048] 16 through holes

[0049] 17 Metal Seed Layer

[0050] 18 Metal Layers

[0051] 19 Metal Columns

[0052] 20 Metal bumps

[0053] 21 Solder mask layer

[0054] 22 metal bumps Detailed Implementation

[0055] Ceramic substrates possess excellent thermal conductivity, heat resistance, high insulation, high strength, low coefficient of thermal expansion, corrosion resistance, and radiation resistance. These properties make ceramic substrates widely used in the packaging of power devices and high-temperature electronic devices, especially in aerospace, military, and other demanding industries. For packaging processes, to achieve smaller, lighter, thinner, higher-performance, and more reliable packaged components, packaging technology has extended along the Z-axis from 2D packaging, resulting in three-dimensional packaging technology. The upper and lower layers of 3D packaging employ vertical interconnection, offering advantages such as increased interconnection speed, reduced response time, and lower power consumption. Vertical interconnect structures, such as through-silicon vias (TSVs), through-metal vias (TMVs), and through-glass vias (TGVs), are key technologies in 3D packaging. Vertical interconnection improves the high-density interconnection capability of the package, resulting in higher integration, faster transmission rates, less parasitic interference, and superior high-frequency characteristics. Therefore, using ceramic substrates as packaging materials, combined with 3D packaging technology and vertical interconnect technology, can effectively improve the heat dissipation capacity of devices and achieve the packaging requirements of smaller, lighter, thinner, higher performance and higher reliability, providing strong support for the miniaturization, high integration and high performance of electronic devices.

[0056] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0057] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0058] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0059] In the detailed description of the embodiments of this utility model, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this utility model. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0060] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0061] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0062] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] Example 1

[0064] This utility model provides a vertical interconnect ceramic packaging substrate. Please refer to [link / reference]. Figure 1This diagram illustrates a structure of a vertical interconnect ceramic packaging substrate according to this embodiment. It includes a first ceramic core plate 1 and a second ceramic core plate 2, a first metal pillar 3, a second metal pillar 4, a first solder mask layer 5, a second solder mask layer 6, a first metal bump 7, a second metal bump 8, and a filler layer 9. The first ceramic core plate 1 has a first through-hole, and the sidewall of the first through-hole has a first metal seed layer 10. The second ceramic core plate 2 has a second through-hole, and the sidewall of the second through-hole has a second metal seed layer 11. The first metal pillar 3 is located in the first through-hole, and the second metal pillar 4 is located in the second through-hole. The first metal pillar 3 has first conductive pads 12 at both ends, and the second metal pillar 4 has second conductive pads 13 at both ends. The first solder mask layer... The first ceramic core plate 1 has a first opening on its top and bottom surfaces, and the second solder resist layer 6 has a second opening on its top and bottom surfaces. The first solder resist layer 5 has a first opening that exposes the first conductive pad 12, and the second solder resist layer 6 has a second opening that exposes the second conductive pad 13. The first metal bump 7 is located in the first opening, and the second metal bump 8 is located in the second opening. The first metal bump 7 located on the bottom surface of the first ceramic core plate 1 and the second metal bump 8 located on the top surface of the second ceramic core plate 2 are aligned and connected to each other to achieve electrical connection between the first ceramic core plate 1 and the second ceramic core plate 2. The filler layer 9 is located in the gap between the first solder resist layer 5 and the second solder resist layer 6.

[0065] Specifically, the first ceramic core plate 1, the first metal seed layer 10, the first metal pillar 3, the first conductive pad 12, the first solder mask layer 5, and the first metal bump 7 constitute a unit ceramic substrate 14. Similarly, the second ceramic core plate 2, the second metal seed layer 11, the second metal pillar 4, the second conductive pad 13, the second solder mask layer 6, and the second metal bump 8 also constitute a unit ceramic substrate 14. The electrical connection between the first metal bump 7 and the second metal bump 8 can be achieved through reflow soldering or thermoforming bonding processes, thereby achieving high-density vertical interconnection between the two unit ceramic substrates 14. This constitutes the vertical interconnect ceramic packaging substrate of this embodiment, improving the high-frequency performance of the packaging substrate, reducing the number of interconnect lines, thereby reducing interconnect resistance and parasitic effects, shortening signal delay, reducing noise and loss, and further improving signal transmission speed. At the same time, it also effectively reduces the complexity and cost of the high-density packaging substrate, thus bringing good economic benefits. In some embodiments, please refer to Figure 2The diagram shows another structural schematic of the vertically interconnected ceramic packaging substrate of the present invention. The number of vertically interconnected unit ceramic substrates 14 is three. In some other embodiments, the number of vertically interconnected unit ceramic substrates 14 may be more, such as four or five.

[0066] As an example, the thickness of the first ceramic core plate 1 ranges from 100μm to 300μm, and the thickness of the second ceramic core plate 2 ranges from 100μm to 300μm.

[0067] As an example, the width of the first ceramic core plate 1 ranges from 21mm to 17mm, the length of the first ceramic core plate 1 ranges from 21mm to 17mm, the width of the second ceramic core plate 2 ranges from 21mm to 17mm, and the length of the second ceramic core plate 2 ranges from 21mm to 17mm. In this embodiment, the width of the first ceramic substrate is 19mm, the length of the first ceramic substrate is 19mm, the width of the second ceramic substrate is 19mm, and the length of the second ceramic substrate is 19mm.

[0068] As an example, the diameter of the first through hole ranges from 50 μm to 80 μm, and the diameter of the second through hole ranges from 50 μm to 80 μm.

[0069] As an example, the longitudinal cross-sectional shape of the first through hole is X-shaped, and the longitudinal cross-sectional shape of the second through hole is X-shaped.

[0070] As an example, the first metal seed layer 10 includes a first metal transition layer and a first metal conductive layer stacked sequentially, and the second metal seed layer 11 includes a second metal transition layer and a second metal conductive layer stacked sequentially.

[0071] As an example, the diameter of the first conductive pad 12 ranges from 50 μm to 100 μm, and the spacing of the first conductive pad 12 ranges from 150 μm to 120 μm. The diameter of the second conductive pad 13 ranges from 50 μm to 100 μm, and the spacing of the second conductive pad 13 ranges from 150 μm to 120 μm. In this embodiment, the diameter of the first conductive pad 12 is 100 μm, the spacing of the first conductive pad 12 is 150 μm, and the diameter of the second conductive pad 13 is 100 μm.

[0072] μm, the spacing of the second conductive pad 13 is 150μm.

[0073] As an example, the diameter of the first opening is in the range of 50 μm to 80 μm, and the diameter of the second opening is in the range of 50 μm to 80 μm.

[0074] As an example, the first metal bump 7 includes a first metal block and a first solder bump located above the first metal block, and the second metal bump 8 includes a second metal block and a second solder bump located above the second metal block.

[0075] As an example, the filler layer 9 includes one of a silicone layer and an epoxy resin layer.

[0076] This embodiment of the vertical interconnect ceramic packaging substrate includes two or more unit ceramic substrates with metal bumps. The metal bumps of the unit ceramic substrates are directly aligned and connected to achieve high-density vertical interconnection between the two or more unit ceramic substrates. This improves the high-frequency performance of the packaging substrate, reduces the number of interconnect lines, thereby reducing interconnect resistance and parasitic effects, shortening signal delay, reducing noise and loss, and further improving signal transmission speed. It also effectively reduces the complexity and cost of the high-density packaging substrate, resulting in significant economic benefits. Furthermore, this embodiment of the vertical interconnect ceramic packaging substrate provides a new approach to heterogeneous integration, which is beneficial to the development of packaging substrate technology. It enables flip-chip (FC) packaging substrate products to have stronger capabilities, promotes the development of high-density interconnect packaging, expands the development platform of the electronic circuit industry, and further drives technological development.

[0077] Example 2

[0078] This embodiment provides a method for manufacturing a vertical interconnect ceramic packaging substrate of the present invention, comprising the following steps:

[0079] Please see Figure 3 First, step S1 is performed: a ceramic core plate 15 is provided, and through holes 16 are formed in the ceramic core plate 15.

[0080] As an example, the ceramic core plate 15 is made of alumina, aluminum nitride, silicon nitride, and zirconia-toughened alumina (ZTA).

[0081] As an example, the method for forming the through hole 16 includes laser drilling or other suitable methods. In this embodiment, the through hole 16 is formed by laser drilling.

[0082] As an example, the longitudinal cross-sectional shape of the through hole 16 is X-shaped, and the diameter of the through hole 16 is in the range of 50μm to 80μm.

[0083] Please see Figure 4 Step S2: Form a metal seed layer 17 on the upper and lower surfaces of the ceramic core plate 15 and on the sidewall of the through hole 16.

[0084] As an example, the method for forming the metal seed layer 17 includes physical vapor deposition or other suitable methods. For example, the metal seed layer 17 can be formed by magnetron sputtering, chemical electroless copper deposition, atomic layer deposition, or vapor deposition.

[0085] As an example, the material of the metal seed layer 17 includes one or more of copper, tungsten, and titanium.

[0086] Please see Figure 5 Step S3: A metal layer 18 is formed on the upper and lower surfaces of the ceramic core plate 15. The metal layer 18 fills the through hole 16 and the metal layer 18 is thinned by a thinning process.

[0087] As an example, the method of forming the metal layer 18 includes electroplating or other suitable methods. In this embodiment, the metal layer 18 is formed by electroplating.

[0088] Please see Figure 6 Step S4: Graphicalize the metal layer 18 and the metal seed layer 17 to expose the upper and lower surfaces of the ceramic core plate 15, forming a metal pillar 19 located in the through hole 16 and metal bumps 20 located at both ends of the metal pillar 19.

[0089] As an example, the process of forming the metal pillar 19 and the metal bump 20 adopts a subtractive tenting process, and other suitable processes may be adopted in other embodiments.

[0090] As an example, the metal layer 18 is made of copper, and the metal bumps 20 are copper disks. In other embodiments, the metal layer 18 may also be made of aluminum, nickel, gold, silver, titanium, or other metals, and there are no restrictions here.

[0091] As an example, the diameter of the metal bump 20 ranges from 50μm to 100μm, and the spacing of the metal bump 20 ranges from 150μm to 120μm. In this embodiment, the diameter of the metal bump 20 is 100μm, and the spacing of the metal bump 20 is 150μm.

[0092] Please see Figure 7 Step S5: A solder resist layer 21 is formed on the upper and lower surfaces of the ceramic core plate 15, and an opening is formed in the solder resist layer 21 to expose the metal bumps 20.

[0093] As an example, the method of forming the solder resist layer 21 includes vacuum pressing, coating or other suitable methods, and the method of forming the opening includes photolithography, laser drilling or other suitable methods.

[0094] Please see Figures 8 to 9Step S6: Form a metal bump 22 in the opening to obtain a ceramic substrate, and cut it to obtain a unit ceramic substrate 14.

[0095] As an example, before forming the metal bump 22, a surface treatment step is included on the upper surface of the metal bump 22 to improve the reliability, conductivity and corrosion resistance of the solder joint of the metal bump 22. The surface treatment method includes solder on pad (SOP), electroplated copper pillars or other suitable methods.

[0096] As an example, the thickness of the unit ceramic substrate 14 ranges from 100μm to 300μm, the width of the unit ceramic substrate 14 ranges from 21mm to 17mm, and the length ranges from 21mm to 17mm. In this embodiment, the width of the unit ceramic substrate 14 is 19mm, and the length of the unit ceramic substrate 14 is 19mm.

[0097] As an example, the method for cutting the ceramic substrate employs laser cutting.

[0098] Please see Figure 10 Step S7: Connect the metal bumps 22 on the opposite side of the two unit ceramic substrates 14 and form a filling layer 9 in the gap between the two ceramic substrates to obtain a vertically interconnected ceramic packaging substrate.

[0099] As an example, the process of connecting the metal bumps 22 on one side of the two unit ceramic substrates 14 includes reflow soldering, hot-press bonding, or other suitable processes.

[0100] As an example, the filler layer 9 includes one of a silicone layer and an epoxy resin layer.

[0101] As an example, the number of unit ceramic substrates 14 is two or more.

[0102] This completes the fabrication of the vertical interconnect ceramic packaging substrate. The method described above for fabricating the vertical interconnect ceramic packaging substrate of this invention greatly simplifies the core board fabrication process, achieves high-density vertical interconnection between two or more unit ceramic substrates, improves the high-frequency performance of the packaging substrate, reduces the number of interconnect lines, thereby reducing interconnect resistance and parasitic effects, shortening signal delay, reducing noise and loss, and further improving signal transmission speed.

[0103] In summary, the vertical interconnect ceramic packaging substrate of this invention includes a first ceramic core plate, a second ceramic core plate, a first through-hole, a second through-hole, a first metal seed layer, a second metal seed layer, a first metal pillar, a second metal pillar, a first conductive pad, a second conductive pad, a first solder mask layer, a second solder mask layer, a first metal bump, a second metal bump, and a filler layer. The first metal bump on the bottom surface of the first ceramic core plate and the second metal bump on the top surface of the second ceramic core plate are directly aligned and connected to achieve electrical connection between the first and second ceramic core plates. This realizes a vertical interconnect ceramic packaging substrate structure, improves the high-frequency performance of the packaging substrate, reduces the number of interconnect lines, thereby reducing interconnect resistance and parasitic effects, shortens signal delay, reduces noise and loss, and further improves signal transmission speed. It also effectively reduces the complexity and cost of high-density packaging substrates. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0104] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A vertical interconnect ceramic packaging substrate, characterized in that, include: A first ceramic core plate and a second ceramic core plate, wherein the first ceramic core plate has a first through hole and a first metal seed layer is provided on the sidewall of the first through hole; and the second ceramic core plate has a second through hole and a second metal seed layer is provided on the sidewall of the second through hole. A first metal pillar and a second metal pillar, wherein the first metal pillar is located in the first through hole and the second metal pillar is located in the second through hole, and the first metal pillar is provided with a first conductive pad at both ends and the second metal pillar is provided with a second conductive pad at both ends. A first solder resist layer and a second solder resist layer, wherein the first solder resist layer is located on the top and bottom surfaces of the first ceramic core board, and the second solder resist layer is located on the top and bottom surfaces of the second ceramic core board, and the first solder resist layer has a first opening that exposes the first conductive pad, and the second solder resist layer has a second opening that exposes the second conductive pad. A first metal bump and a second metal bump, wherein the first metal bump is located in the first opening and the second metal bump is located in the second opening, and the first metal bump located on the bottom surface of the first ceramic core plate and the second metal bump located on the top surface of the second ceramic core plate are aligned and connected to each other. A filler layer is located in the gap between the first solder mask layer and the second solder mask layer.

2. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The thickness of the first ceramic core plate is in the range of 100μm to 300μm, and the thickness of the second ceramic core plate is in the range of 100μm to 300μm.

3. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The width of the first ceramic core plate is 21mm to 17mm, the length of the first ceramic core plate is 21mm to 17mm, the width of the second ceramic core plate is 21mm to 17mm, and the length of the second ceramic core plate is 21mm to 17mm.

4. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The diameter of the first through hole is in the range of 50μm to 80μm, and the diameter of the second through hole is in the range of 50μm to 80μm.

5. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The longitudinal cross-sectional shape of the first through hole is X-shaped, and the longitudinal cross-sectional shape of the second through hole is X-shaped.

6. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The first metal seed layer includes a first metal transition layer and a first metal conductive layer stacked sequentially, and the second metal seed layer includes a second metal transition layer and a second metal conductive layer stacked sequentially.

7. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The diameter of the first conductive pad is in the range of 50μm to 100μm, and the spacing between the first conductive pads is in the range of 150μm to 120μm. The diameter of the second conductive pad is in the range of 50μm to 100μm, and the spacing between the second conductive pads is in the range of 150μm to 120μm.

8. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The diameter of the first opening is in the range of 50μm to 80μm, and the diameter of the second opening is in the range of 50μm to 80μm.

9. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The first metal bump includes a first metal block and a first solder bump located above the first metal block, and the second metal bump includes a second metal block and a second solder bump located above the second metal block.

10. The vertical interconnect ceramic packaging substrate according to claim 1, characterized in that: The filler layer includes one of a silicone layer and an epoxy resin layer.

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