Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure comprises a device layer with a transistor device and a PN junction structure coupled to the transistor device. The PN junction structure includes a first doped region and a second doped region, and the first doped region is electrically connected to a gate stack of the transistor device. The semiconductor structure includes a front-side interconnect structure over the front side of the device layer, the front-side interconnect structure including a thermal path metal feature electrically connected to the second doped region of the PN junction structure. The semiconductor structure includes a bonding oxide layer over the front-side interconnect structure that embeds a thermal path metal contact electrically connected to the thermal path metal feature. The semiconductor structure includes a carrier substrate over the bonding oxide layer, the carrier substrate falling on a top surface of the thermal path metal contact.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] The electronics industry's demand for smaller, faster electronic devices that can simultaneously support a multitude of increasingly complex and sophisticated functions is constantly growing. To meet these demands, the integrated circuit (IC) industry continues its trend towards low-cost, high-efficiency, and low-power ICs. To date, these goals have been largely achieved by shrinking IC dimensions (e.g., the smallest IC feature size), thereby increasing production efficiency and reducing associated costs. However, this size reduction also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require similar progress in IC manufacturing processes and technologies.

[0003] As technology nodes shrink, signal and power connections can be routed to the back side of the circuit structure to optimize power and chip space. In these cases, after front-side IC features are formed above the device substrate, the circuit structure can be attached to the carrier substrate via oxide bonding. The circuit structure is then thinned from the back side to partially or completely remove the device substrate, and back-side interconnect features such as back-side vias, back-side metal lines, and back-side power rails are formed on the back side of the thinned circuit structure. However, because the device substrate is partially or completely removed, device self-heating becomes a problem. The device substrate provides a thermal path to absorb the heat generated by the transistor device. When it is removed, the heat is trapped, potentially causing damage to the transistor device due to self-heating.

[0004] Therefore, although existing IC structures with back-side features for signal and power connections are generally sufficient to meet their intended purpose, they are not entirely satisfactory in every respect. Utility Model Content

[0005] This invention provides a semiconductor structure. The semiconductor structure includes a device layer having transistor devices and a PN junction structure coupled to the transistor devices. The transistor devices include a channel region between source / drain (S / D) regions and a gate stack above the channel region. The PN junction structure includes a first doped region and a second doped region, with the first doped region electrically connected to the gate stack. This semiconductor structure includes a front-side interconnect structure above the front side of the device layer, the front-side interconnect structure including a thermal path metal feature electrically connected to the second doped region of the PN junction structure. This semiconductor structure includes a bonding oxide layer above the front-side interconnect structure, the bonding oxide layer embedding thermal path metal contacts electrically connected to the thermal path metal features. This semiconductor structure includes a carrier substrate above the bonding oxide layer, the carrier substrate resting on the top surface of the thermal path metal contacts.

[0006] This invention provides a semiconductor structure. The semiconductor structure includes a transistor device having a channel region between source / drain (S / D) regions and a gate stack above the channel region. The semiconductor structure includes a PN junction structure having a first doped region and a second doped region with opposite doping to the first doped region, and the first doped region is electrically connected to the gate stack. The semiconductor structure includes a thermal path metal feature located above the PN junction structure and electrically connected to the second doped region of the PN junction structure. The semiconductor structure includes a carrier substrate located above and in metal contact with the thermal path metal feature. Attached Figure Description

[0007] The best understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0008] Figure 1 A semiconductor structure having a thermally conductive path from a transistor device to a carrier substrate is shown according to an embodiment of the present disclosure.

[0009] Figure 2 A flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown, the semiconductor structure having a thermally conductive path from a portion or all of a transistor device to a carrier substrate.

[0010] Figures 3 to 9 The following diagram illustrates an intermediate stage of manufacturing according to an embodiment of this disclosure and, according to Figure 2 The method is used to process semiconductor structures with a thermally conductive path from the transistor device to the carrier substrate.

[0011] Figure 10A A top view of a semiconductor structure having multiple thermally conductive paths from multiple transistor devices to a carrier substrate is shown according to an embodiment of the present disclosure.

[0012] Figure 10B-1 The following is illustrated along an embodiment according to this disclosure. Figure 10A A cross-sectional view of a semiconductor structure cut by line B-B'.

[0013] Figure 10B-2 It shows the results from the following: Figure 10B-1 The mechanism by which transistor devices with semiconductor structures release heat.

[0014] Figure 10C The following is illustrated along an embodiment according to this disclosure. Figure 10A A cross-sectional view of a semiconductor structure cut by line C-C'.

[0015] Figures 11A to 11CThe metal wire and via dimensions of the thermal conductive paths and functional circuit paths according to various embodiments of this disclosure are shown.

[0016] Figure 12 A circuit diagram of multiple transistor devices whose gates are coupled to a carrier substrate is shown.

[0017] Figure 13 The bonding between the device wafer and the carrier wafer according to an embodiment of the present disclosure is shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features do not directly contact each other. Additionally, reference numerals and / or letters may be repeated in various instances in this disclosure. Such repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one component or feature relative to another component(s) as shown in the figures. Besides the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0020] Furthermore, when using terms such as "approximately," "about," and similar terms to describe numbers or ranges of numbers, the purpose of these terms is to encompass numbers within a reasonable range that takes into account variations inherent during manufacturing, as understandable to those skilled in the art to which this invention pertains. For example, based on known manufacturing tolerances associated with manufacturing a component having features associated with a number, a number or range of numbers includes a reasonable range of the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "approximately 5 nm" encompasses a size range from 4.5 nm to 5.5 nm, where the manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to which this invention pertains are + / - 10%. And when comparing the size or dimensions of one feature with another feature, terms such as "substantially identical," "truly the same," "similar in size," etc., can be understood as features compared within + / - 10%. Furthermore, the dimensions of different features disclosed may implicitly disclose the size ratio between the different features. Moreover, different examples in the disclosure may use repeated reference numerals and / or wording. These repeated symbols or wording are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0021] This disclosure relates to a semiconductor structure having thermal paths for dissipating heat generated by a transistor device. Specifically, this disclosure describes creating thermally conductive paths from the gate terminals of the transistor device to a carrier substrate, thereby mitigating undesirable thermal effects by allowing the carrier substrate to absorb dissipated heat. These thermal paths are made possible by patterning the bonding oxide between the carrier wafer and the device wafer, allowing metal contacts to penetrate the bonding oxide to electrically connect between the carrier substrate and the metal lines connected to the gate terminals. Each thermally conductive path includes a PN junction structure coupled between the gate terminal and the metal lines connected to the carrier substrate. The PN junction structure acts as a reverse diode, blocking electrical signals while allowing heat transfer. In this way, multiple gate terminals can be connected to a common carrier substrate while avoiding gate short-circuit problems between different gates.

[0022] Figure 1A semiconductor structure 100 having a thermally conductive path from transistor device 110 to carrier substrate 302 is shown according to an embodiment of this disclosure. For simplicity, transistor device 110 is shown as a dashed box and is further described in later figures. Transistor device 110 may be one of a plurality of transistor devices 110 formed in device layer 120. Each transistor device 110 includes a channel region between source / drain (S / D) regions and has a gate stack (which includes a gate dielectric above the channel region). Device layer 120 also includes a PN junction structure 115 disposed adjacent to transistor device 110. PN junction structure 115 may be one of a plurality of PN junction structures 115 formed in device layer 120. For example, additional pairs of PN junction structures 115 and transistor devices 110 may be formed in device layer 120 in a similar manner. PN junction structure 115 is shown as a reverse diode having a first terminal and a second terminal. PN junction structure 115 will be further described in later figures.

[0023] Still referencing Figure 1 An interconnect structure 220 is formed above the front side of device layer 120. The interconnect structure 220 electrically couples various devices (e.g., p-type transistor devices 110 and / or n-type transistor devices 110, other transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate stacks and / or epitaxial source / drain features of p-type transistor devices 110 and / or n-type transistor devices 110) such that the various devices and / or components can operate in a manner specified by design requirements. The interconnect structure 220 includes a combination of dielectric and conductive layers (e.g., metal layers) configured to form various interconnect components. The conductive layers are configured to form vertical interconnect components such as metal vias and / or horizontal interconnect components such as metal wires, wherein the metal wires are vertically disposed between the metal vias. The vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the interconnect layer. During operation, the interconnect structure 220 is configured to route signals between devices and / or components of the semiconductor structure 100 and / or distribute signals (e.g., frequency signals, voltage signals, and / or ground signals) to devices and / or components of the semiconductor structure 100.

[0024] exist Figure 1In some embodiments, the interconnect structure 220 includes front vias, such as front vias 222, 223a, and 223b falling on the device layer 120. The front via 222 may be disposed above the gate stack and electrically connected to the gate stack and / or the epitaxial source / drain assembly of the transistor device 110. The front vias 223a and 223b may be disposed above and electrically connected to the respective first and second terminals of the PN junction structure 115. The interconnect structure 220 also includes a metal feature 225 disposed above the front via 222 and electrically connected to one or more front vias 222. The metal feature 225 includes a metal line perpendicularly disposed between the metal vias and may include a bottom metal line electrically connecting the front via 222 to the front via 223a (e.g., coupled to the top surfaces of the front vias 222 and 223a). The interconnect structure 220 also includes a metal feature 227 disposed above and electrically connected to the front via 223b. The metal feature 227 may include a bottom metal line bonded to the top surface of the front via 223b. The metal feature 225 includes insertion metal vias and metal lines that route device signals (e.g., power lines and signal lines) to various metal layers. The metal feature 227 includes insertion metal vias and metal lines that route heat dissipation paths to the carrier substrate 302. In this embodiment, the metal feature 227 immediately adjacent to the right-hand metal feature 225 routes gate signals and may be referred to as gate metal feature 225 or gate path metal line 225. In this embodiment, the metal feature 227 is thermally coupled to a set of gate metal features and thermally coupled to the transistor device 110 through the PN junction structure 115 and may be referred to as thermal path metal feature 227 or thermal path metal line 227. Front vias 222, 223a, and 223b, as well as metal features 225 and 227, are embedded in an inter-metal dielectric (IMD) structure 229, which isolates the various metal features. The front vias 222, 223a, and 223b, as well as the metal features 225 and 227, may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), or molybdenum (Mo). The IMD structure 229 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable dielectric materials.

[0025] Still referencing Figure 1A bonding oxide layer 350 is disposed above the interconnect structure 220, and a bonding metal contact 322 penetrates the bonding oxide layer 350 to land on the top metal line of the metal feature 227. The bonding oxide layer 350 and the bonding metal contact 322 can be formed by hybrid bonding (oxide-to-oxide and metal-to-metal). As shown, bonding oxide layer 350a is bonded to bonding oxide layer 350b, and bonding metal contact 322a is bonded to bonding metal contact 322b. In this embodiment, the bonding metal contact includes copper, and the bonding oxide layer 350a may include a via portion and a metal line portion wider than the via portion above the via portion. A carrier substrate 302 is disposed above the bonding oxide layer 350 and the bonding metal contact 322. As shown, the carrier substrate 302 lands directly on and contacts the top surface of the bonding metal contact 322. The carrier substrate 302 may include silicon (Si), or other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. In this embodiment, the carrier substrate 302 is made of silicon.

[0026] Still referencing Figure 1 Interconnect structure 240 is formed on the back side of device layer 120 (i.e., below device layer 120). Interconnect structure 240 electrically couples various devices (e.g., p-type transistor devices 110 and / or n-type transistor devices 110, other transistors, resistors, capacitors and / or inductors) and / or components (e.g., gate stacks) and / or epitaxial source / drain components of p-type transistor devices 110 and / or n-type transistor devices 110 to the back side of device layer 120. Similar to interconnect structure 220, interconnect structure 240 includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form various interconnect components. The conductive layers are configured to form vertical interconnect components such as metal vias and / or horizontal interconnect components such as metal wires, wherein the metal wires are vertically disposed between the metal vias. Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the interconnect layer.

[0027] exist Figure 1In one embodiment, the interconnect structure 240 includes a back-side via 242 falling on the back side of the device layer 120. The back-side via 242 may be disposed above and electrically connected to the back side of an epitaxial source / drain feature of a transistor. The interconnect structure 240 also includes a back-side metal feature 245 disposed above and electrically connected to one or more back-side vias 242. The back-side metal feature 245 includes metal lines perpendicularly disposed between the metal vias and may include a top metal line electrically connected to and bonded to the back side of the back-side via 242, and a bottom metal line routed to power and / or I / O bonding pads 410. The bonding pads 410 may be bonded to other circuit structures not shown. The back-side metal feature 245 includes insertion vias and metal lines that route device signals (e.g., power lines and signal lines) to various metal layers. A back-side via 242 and a back-side metal feature 245 are embedded in an inter-metal dielectric (IMD) structure 249 that isolates the various metal features. The back-side via 242 and the back-side metal feature 245 may comprise materials similar to those used for the front-side via 222 and the metal feature 225. The IMD structure 249 may comprise materials similar to those used for the IMD structure 229.

[0028] like Figure 1 As shown by the dashed lines, the semiconductor structure 100 is formed by bonding a device wafer 200 to a carrier wafer 300. The device wafer 200 and the carrier wafer 300 are bonded together via bonding oxide layers 350a and 350b, and bonded metal contacts 322a and 322b as described above. The device wafer 200 includes a device layer 120, interconnect structures 220 and 240, and a bonding oxide layer 350a. The carrier wafer 300 includes a carrier substrate 302 and a bonding oxide layer 350b. After bonding, a thermal path is formed to the carrier substrate 302 for one or more transistor devices 110. For example, the thermal path propagates from the gate stack of transistor device 110 to front via 222, to metal feature 225 (i.e., gate path metal line 225), to front via 223a, through PN junction structure 115, to front via 223b, to metal feature 227 (i.e., thermal path metal line), to bonding metal contact 322, and to carrier substrate 302. As will be explained in more detail below, PN junction structure 115 acts as a reverse diode, blocking electrical signals to prevent gate short circuits while allowing heat transfer.

[0029] According to embodiments of this disclosure, some or all of the heat dissipation paths (similar to) are formed. Figure 1The flowchart illustrates a method 1000 for a semiconductor structure 100 (showing a heat dissipation path). Semiconductor structure 100 corresponds to a semiconductor device, and the two terms (i.e., device and structure) are used interchangeably. A semiconductor device can be an integrated circuit (IC) chip, a system-on-a-chip (SoC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device is incorporated into non-volatile memory, such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof.

[0030] Figures 3 to 9 It shows according to Figure 2 Method 1000 processes the formation of semiconductor structure 100 in an intermediate stage of manufacturing. Note that the embodiments shown in this disclosure utilize the gate-on-ring (GAA) field effect to realize a transistor (FET), but this disclosure is not limited thereto. A GAA FET refers to a transistor having a gate stack (gate electrode and gate dielectric) surrounding a transistor channel, such as vertically stacked gates surrounding a horizontal nanowire or nanosheet MOSFET assembly. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other structures to achieve the same purposes and / or the same advantages as the embodiments described herein.

[0031] Now for reference Figure 3 In method 1000, at operation 1002, a transistor device 110 is formed in a device layer 120 above a substrate 102. The substrate 102 may include silicon (Si) or other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. As shown, each transistor device 110 includes an active region 104 and a gate stack 108 above a channel region 104a, the active region 104 having a channel region 104a located between source / drain (S / D) regions 104b. Each transistor device 110 may be a GAA FET assembly, a finned FET assembly, or a planar assembly. In the illustrated embodiment, the active region 104 may be a finned active region 104 protruding from the substrate 102 over an isolation structure. The finned active region 104 forms the active region 104 for a GAA or finned FET assembly.

[0032] Gate stack 108 includes a gate electrode 108b above a gate dielectric 108a, and the gate dielectric 108a is disposed on a channel region 104a. In some embodiments, an interface layer (e.g., a silicon oxide layer) is vertically disposed between the channel region 104a and the gate dielectric 108a. The gate dielectric 108a includes a high-k dielectric material, such as a material with a dielectric constant greater than that of silicon oxide (k ≈ 3.9). The gate dielectric 108a may include HfO, LaO, ZrO, AlO, TiO, or TaO. The gate electrode 108b includes a suitable conductive material, such as Al, W, Co, TiAl, TiN, or other metallic gate materials. As shown in the following figures (e.g., Figure 10B-1 and Figure 10C As shown, gate dielectric 108a and gate electrode 108b may each surround multiple transistor channels in channel region 104a. Each channel region 104a may also include spacer wall features (see example...). Figure 10B-1 The spacer features 108c include, for example, gate spacers and internal spacers. Gate spacers may align the sidewalls of the gate stack 108 above the topmost channel, and internal spacers may be vertically disposed between the transistor channels and laterally disposed between the gate stack 108 and the S / D region 104b. Gate spacers and internal spacers may comprise silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. In an embodiment, the spacer features are surrounded by an oxide dielectric layer, and therefore the spacer features include silicon nitride for etchant selectivity.

[0033] Each S / D region 104b may include an epitaxial S / D feature doped with n-type and / or p-type dopants, sandwiching a transistor channel within a channel region 104a. In some embodiments, for an n-type transistor, the S / D region 104b includes an epitaxial S / D feature of silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming a Si:C epitaxial source / drain feature, a Si:P epitaxial source / drain feature, or a Si:C:P epitaxial source / drain feature). In some embodiments, for a p-type transistor, the S / D region 104b includes an epitaxial S / D feature of silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain feature). In some embodiments, the portion of the epitaxial feature closest to the transistor channel in the channel region 104a has a lower doping concentration than the portion of the epitaxial feature laterally away from the transistor channel.

[0034] Still refer to Figure 3In method 1000, at operation 1004, a PN junction structure 115 is formed in device layer 120. Each of the PN junction structures 115 may be formed as one of the adjacent transistor devices 110. Although only one is shown, this disclosure contemplates forming multiple pairs of PN junction structures 115 and transistor devices 110. The PN junction structure 115 is shown as a diode with two terminals corresponding to PN junction electrodes 217a and 217b. The two terminals are configured such that the PN junction structure 115 is reverse biased in operation. Each PN junction structure 115 includes a first doped region and a second doped region (not shown here, but...). Figure 10B-1 The first doped region (shown as 215a and 215b) is doped with dopants of opposite types. The first doped region is electrically connected to a first terminal (i.e., PN junction electrode 217a), and the second doped region is electrically connected to a second terminal (i.e., PN junction electrode 217b). The first doped region and PN junction electrode 217a may be electrically connected to the gate stack 108 in a later operation 1006, and the second doped region and PN junction electrode 217b may be electrically connected to the carrier substrate 302 in a later operation 1012. Additional details of the PN junction structure 115 are described in later figures.

[0035] Now for reference Figure 4 In method 1000, in operation 1006, a front-side internal interconnect structure 220 is formed above device layer 120. The front-side internal interconnect structure 220 includes front-side vias 222, 223a, and 223b, and metal features 225 and 227 embedded in an intermetallic dielectric (IMD) structure 229. (As mentioned above regarding...) Figure 1 These features can be formed through any suitable patterning and deposition process. Some metal features 225 may be gate path metal lines 225 electrically connected to one or more gate stacks 108 via one or more front vias 222 falling on the gate stack 108. In an embodiment, the bottommost metal line of the gate path metal line 225 is bonded to the front vias 222 and 223a, wherein the front via 222 is bonded to the gate stack 108 and the front via 223a is bonded to the first terminal (i.e., PN junction electrode 217a) of the PN junction structure 115. In an embodiment, metal feature 227 (or thermal path metal line 227) is electrically connected to the second terminal (i.e., PN junction electrode 217b) of the PN junction structure 115 via bonded to the front via 223b, wherein the front via 223b is bonded to the second terminal of the PN junction structure 115. As shown, the thermal path metal line 227 is coupled to the gate path metal line 225 through the PN junction structure 115 formed therebetween. Note that other metal features 225 and other features that can be coupled to other transistor devices 110 are also shown.

[0036] Now for reference Figure 5 In method 1000, at operation 1008, a first bonding oxide layer 350a is deposited over the front-side interconnect structure 220. The first bonding oxide layer 350a is embedded in a first bonding metal contact 322a that falls on the top surface of a thermal path metal line 227 (e.g., the top metal line of the thermal path metal line 227). In an embodiment, the first bonding oxide layer 350a comprises silicon oxide. The first bonding oxide layer 350a can be deposited over the interconnect structure 220 first through any suitable deposition process, then the first bonding oxide layer 350a is patterned to form a trench, and then the trench is filled with a metallic material (e.g., copper) to form the bonding metal contact 322a. A planarization process can then be performed to planarize the top surfaces of the bonding metal contact 322a and the bonding oxide layer 350a. The bonding metal contact 322a can include a wider metal contact portion over a narrower via portion, and different portions can be formed in a dual damascene process. In this embodiment, the bonding metal contact 322a is made of copper.

[0037] Now for reference Figure 6 Referring specifically to the top figure, method 1000 forms a carrier chip 300 having a second bonding oxide layer 350b on a carrier substrate 302 at operation 1010. The second bonding oxide layer 350b is embedded in a second bonding metal contact 322b on the carrier substrate 302. These features have been referenced. Figure 1 The second bonding oxide layer 350b can first be deposited on the surface of the carrier substrate 302 using any suitable deposition process. The second bonding oxide layer 350b is then patterned to form trenches, which are then filled with a metallic material (e.g., copper) to form a bonding metal contact 322b. A planarization process can then be performed to planarize the top surfaces of the bonding metal contact 322b and the bonding oxide layer 350b. In this embodiment, the bonding metal contact 322b is made of copper.

[0038] Still referencing Figure 6Referring specifically to the bottom figure, method 1000 performs a bonding process at operation 1012 to bond a first bonding oxide layer 350a to a second bonding oxide layer 350b, such that a first bonding metal contact 322a directly contacts a second bonding metal contact 322b. The bonding process may include flipping a carrier wafer 300 (or device wafer 200) to perform front-to-front hybrid bonding at the dashed interface. As shown, device wafer 200 includes a substrate 102, a device layer 120, and a front-side interconnect structure 220. After the bonding process, bonding oxide layer 350 is formed through bonding oxide layers 350a and 350b, and bonding metal contacts 322 are formed from bonding metal contacts 322a and 322b. Bond metal contacts 322 penetrate bonding oxide layer 350 to create a thermal path from carrier substrate 302 to one or more transistor devices 110.

[0039] Now for reference Figure 7 In method 1000, at operation 1014, the substrate 102 is thinned from the back side to expose the transistor device 110 in the device layer 120. Operation 1014 can be performed before or after the bonded semiconductor structure 100 is flipped for further flipping. Due to the flipping, the vertically upward axis now appears as the -Z direction. Operation 1014 thins the exposed back side of the substrate 102 through a suitable process such as mechanical polishing and / or chemical thinning. In the illustrated embodiment, the thinning process completely removes the substrate 102, such that the device layer 120 is fully exposed on the back side. In other embodiments, the substrate 102 may be partially removed, but a portion of the device layer 120 is exposed to expose features of the transistor device 110 (e.g., gate stack 108 and S / D region 104b). In either case, since the substrate 102 is partially or completely removed, the substrate 102 is no longer able or efficient at absorbing heat caused by device self-heating. Thus, the carrier substrate 302 supplements or replaces the heat-absorbing function of the substrate 102 through the formed thermal path.

[0040] Now for reference Figure 8 In method 1000, operation 1016 forms a back-side interconnect structure 240 on the back side of device layer 120 and the back side of transistor device 110. The back-side interconnect structure 240 includes a back-side via 242 and a back-side metal feature 245 embedded in an inter-metal dielectric (IMD) structure 249, as described above regarding... Figure 1These features can be formed through any suitable patterning and deposition process. The back-side metal feature 245 may include metal lines and vias electrically connected from the back side to one or more S / D regions 104b. In one embodiment, one or more metal lines of the back-side metal feature 245 may fall on one or more back-side vias 242, wherein the back-side vias 242 fall on the back side of one or more S / D regions 104b of the transistor device 110. During or after operation 1016, method 1000 may form bonding pads 410, which are shown to fall on one or more back-side metal features 245. Bonding pads 410 may be I / O bonding pads 410 for power supply and / or routing to other circuit structures not shown. Figure 9 It shows the orientation along the positive z-direction. Figure 8 It corresponds to the above. Figure 1 .

[0041] Figure 10A A top view of a semiconductor structure 100 having multiple heat conduction paths for multiple transistor devices 110 is shown. Note that, for simplicity, Figure 10A Only certain features are shown, and others are omitted. In the illustrated embodiment, semiconductor structure 100 includes an active region 104 formed as part of the previously described transistor device 110 and an active region 104 formed as part of the previously described PN junction structure 115. Each PN junction structure 115 includes adjacent N-type doped regions (e.g., a first doped region 215a) and P-type doped regions (e.g., a second doped region 215b). As shown, semiconductor structure 100 may also include active regions 104 as part of other transistors and / or as separate epitaxial features. Gate stack 108 extends longitudinally over the channel regions 104a of each active region 104. Semiconductor structure 100 also includes thermal path metal lines 227 routed to a common carrier substrate 302 (not shown here). Figure 10A The various features described herein can be isolated from each other through the isolation structure 101. The isolation structure 101 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0042] Still referencing Figure 10AThe gate stack 108 is electrically connected to a first terminal of the PN junction structure 115. The first terminal is electrically connected to a first doped region 215a, such as an n-type doped region of the PN junction structure 115. A thermal path metal line 227 is electrically connected to a second terminal of the PN junction structure 115. The second terminal is electrically connected to a second doped region 215b, such as a p-type doped region of the PN junction structure 115. In other embodiments, the N-type and P-type doped regions are interchanged. For example, if the transistor device 110 is an n-type transistor with n-type source / drain characteristics, then the first doped region 215a is n-type doped and the second doped region 215b is p-type doped. And if the transistor device 110 is a p-type transistor with p-type source / drain characteristics, then the first doped region 215a is p-type doped and the second doped region 215b is n-type doped. These orientations are to facilitate reverse bias conditions during circuit operation.

[0043] Figure 10B-1 The following is illustrated along an embodiment according to this disclosure. Figure 10A The image shows a cross-sectional view of the semiconductor structure 100 cut by line segment B-B'. Please note that... Figure 10B-1 Similar to Figure 1 (or Figure 9 The enlarged portion of the diagram, where previously described features are similarly labeled. For the sake of brevity, similar features will not be described again. However, Figure 10B-1 More detailed features of device layer 120 are shown, including details of PN junction structure 115, gate stack 108, and other device layer components in device layer 120. Figure 10B-1 More detailed features of example dielectric layers within the front interconnect structure 220 and the back interconnect structure 240 are further shown.

[0044] refer to Figure 10B-1 The gate stack 108 may be part of a gate structure having a gate stack 108 (which includes a gate dielectric 108a and a gate electrode 108b) and a spacer wall component 108c. The gate structure is disposed above a channel region 104a, which may include a stack of transistor channels 104a-1. The gate dielectric 108a may surround the transistor channel 104a-1, and the bottom portion of the gate electrode 108b may surround the gate dielectric 108a. The top of the gate electrode 108b is disposed above the stack of transistor channels 104a-1.

[0045] Still referencing Figure 10B-1The PN junction structure 115 is a semiconductor active region configured differently from the active region 104 of the transistor device 110. The PN junction structure 115 includes a semiconductor portion 208 in which a first doped region 215a and a second doped region 215b are formed. For example, the remote ends of the semiconductor portion 208 can be recessed to form trenches, and the first doped region 215a and the second doped region 215b are formed by growing corresponding doped epitaxial features within the trenches. The first doped region 215a is doped with a dopant of the opposite type to that of the second doped region 215b. In this embodiment, the first doped region 215a is doped with an n-type dopant, and the second doped region 215b is doped with a p-type dopant. In this case, the gate stack 108 coupled to the first doped region 215a is the gate stack 108 of the n-type transistor device 110, wherein the S / D region of the transistor device 110 is n-type doped. In one embodiment, the first doped region 215a, doped with an n-type dopant, includes epitaxial features doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si:C epitaxial features, Si:P epitaxial features, or Si:C:P epitaxial features). In another embodiment, the second doped region 215b, doped with a p-type dopant, includes epitaxial features doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial features). Note that in an alternative embodiment, the first doped region 215a is doped with a p-type dopant, and the second doped region 215b is doped with an n-type dopant. In this case, the gate stack 108 coupled to the first doped region 215a is the gate stack 108 of the p-type transistor device 110, wherein the S / D region of the transistor device 110 is p-type doped. In another embodiment, the first doped region 215a, doped with a p-type dopant, includes epitaxial features doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial features). In an embodiment, the second doped region 215b, doped with an n-type dopant, includes epitaxial features doped with carbon, phosphorus, arsenic, other n-type dopants or combinations thereof (e.g., forming Si:C epitaxial features, Si:P epitaxial features or Si:C:P epitaxial features).

[0046] In this embodiment, the semiconductor portion 208 includes a stack of interleaved silicon channels 204 and silicon-germanium channels 206, which may be formed as part of forming a GAA device in other portions of the semiconductor structure 100. However, this disclosure is not limited to this, and the semiconductor portion 208 may be formed from a single semiconductor layer (e.g., silicon).

[0047] In this embodiment, the first doped region 215a and the second doped region 215b are separated by a channel portion of semiconductor portion 208, which acts as a channel between them. In this embodiment, this channel portion may include a stack of staggered silicon channels 204 and silicon-germanium channels 206. The channel portion may be doped with p-type or n-type dopant. In some cases, the channel portion is lightly doped than the first doped region 215a and the second doped region 215b. If the channel portion is doped with p-type dopant, the interface between the channel portion and the n-type doped first doped region 215a may define a PN junction. If the channel portion is doped with n-type dopant, the interface between the channel portion and the p-type doped second doped region 215b may define a PN junction. However, in some embodiments, the first doped region 215a and the second doped region 215b may be directly adjacent to each other to share a common interface. In this case, there is no channel portion between the first doped region 215a and the second doped region 215b, and the common interface between the first doped region 215a and the second doped region 215b defines a PN junction. In any case, the PN junction of the PN junction structure 115 will be reverse biased during operation, as shown in a diode.

[0048] The PN junction structure 115 also includes PN junction electrodes 217a and 217b, which serve as the first and second terminals of a reverse diode. PN junction electrode 217a is bonded to the top surface of the first doped region 215a, and PN junction electrode 217b is bonded to the top surface of the second doped region 215a. PN junction electrodes 217a and 217b may comprise suitable metallic materials, such as Al, W, Co, TiAl, TiN, or other metallic materials.

[0049] Still referencing Figure 10B-1Assuming the gate stack 108 is the gate stack 108 of the first transistor device 110, the device layer 120 may include the S / D region 104b of the second transistor device 110. The S / D region 104b of the second transistor device is laterally adjacent to the gate stack 108 of the first transistor device 110, wherein the gate stack 108 of the first transistor device 110 is laterally adjacent to the PN junction structure 115. S / D contacts 214 are arranged above and fall on the S / D region 104b. The S / D contacts 214 may include a material similar to the PN junction electrodes 217a and 217b. As shown, the device layer 120 includes an isolation structure 101 embedded in and surrounding the PN junction structure 115, the gate stack 108, and the S / D region 104b. The isolation structure 101 may have a top surface substantially coplanar with the top surfaces of the PN junction structure 115 and the S / D region 104b. Furthermore, the top surface of the gate stack 108 can be located above the top surfaces of the PN junction structure 115, the isolation structure 101, and the S / D region 104b. The device layer 120 also includes an interlayer dielectric (ILD) layer 219 disposed above the isolation structure 101. The ILD layer 219 is embedded in and surrounds the PN junction electrodes 217a and 217b, the gate stack 108, and the S / D contact 214. The ILD layer 219 can have a top surface that is substantially coplanar with the top surfaces of the PN junction electrodes 217a and 217b and the S / D contact 214. And the top surface of the ILD layer 219 can be above the top surface of the gate stack 108. ILD layer 219 may comprise tetraethyl orthosilicate, undoped silicate glass, or an oxide formed from doped silicon oxide, such as borosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), a low-k dielectric material, other suitable dielectric materials, or combinations thereof. In embodiments, for etchant selectivity, the isolation structure 101 and ILD layer 219 are formed from different dielectric materials (e.g., the isolation structure 101 is formed from silicon oxide, and the ILD layer 219 is formed from a low-k dielectric).

[0050] As previously described, the front inline interconnect structure 220 is disposed above the device layer 120. The front inline interconnect structure 220 includes an IMD structure 229 embedded in and surrounding the various metal features previously described. In an embodiment, the IMD structure 229 may have a first layer 229a, a second layer 229b above the first layer 229a, and a third layer 229c above the second layer 229b. The first layer 229a may include silicon nitride, the second layer 229b may include silicon oxide, and the third layer 229c may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other dielectrically suitable materials. The first layer 229a and the second layer 229b may be embedded in and surrounding the front vias 222, 223a, and 223b falling on the device layer 120, and the third layer 229c may be embedded in and surrounding the metal features 225 and 227. The first layer 229a, the second layer 229b, and the third layer 229c can be configured to have different materials for etchant selectivity when forming various embedded metal features.

[0051] As previously described, a backside interconnect structure 240 is disposed on the back side of device layer 120. The backside interconnect structure 240 includes an IMD structure 249 embedded in and surrounding the various metal features previously described. In an embodiment, the IMD structure 249 may have a first layer 229a, a second layer 229b above the first layer 229a, and a third layer 229c above the second layer 229b. The first layer 249a may include silicon nitride, the second layer 249b may include silicon oxide, and the third layer 249c may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable dielectric materials. The first layer 249a and the second layer 249b may be embedded in and surrounding a backside via 242 falling on the S / D region 104b, and the third layer 249c may be embedded in and surrounding a metal feature 245. The first layer 249a, the second layer 249b, and the second layer 249c may be embedded in and surrounding the metal feature 245. The third layer 249c can be configured to have different materials for etchant selectivity when forming various embedded metal features.

[0052] As mentioned above and as Figure 10B-1As shown, the thermal path metal feature 227 is routed to the carrier substrate 302 via bonding metal contacts 322a and 322b embedded in bonding oxide layers 350a and 350b. Note that in some embodiments, other metal contacts or metal features 225 embedded in bonding oxide layer 350a may be present for further device signal routing. However, these metal features 225 are not electrically connected to the carrier substrate 302. As shown, bonding oxide layer 350 isolates these metal features 225 to prevent them from making metal contact with the carrier substrate 302. Because the metal features 225 are not electrically isolated, bonding oxide layer 350 prevents any undesirable short-circuit effects compared to any PN junction structure 115.

[0053] Figure 10B-2 It shows the results from the following: Figure 10B-1 The mechanism by which the transistor device 110 of the semiconductor structure 100 releases heat. Although heat may be generated in other parts of the transistor device 110 (e.g., the S / D region 104b), the heat energy is mainly generated in the channels of the channel region 104a. Since the gate stack 108 has a larger coupling surface to the channels than the S / D region 104b, routing the heat path to the gate stack 108 is more efficient than routing it to the S / D region. As indicated by the dashed arrow, the heat path from the gate stack 108 to the carrier substrate 302 allows the heat energy generated by the transistor device 110 to be absorbed by the carrier substrate 302. Without a heat path to the carrier substrate 302, the heat energy is trapped and poorly absorbed by the various dielectric layers (e.g., bonding oxide layers 350a and 350b). Through the heat path to the carrier substrate 302, heat absorption is significantly improved. For example, studies have shown that the thermal conductivity of silicon can be 120 times that of dielectric oxides. Using a silicon carrier substrate 302, the heat energy can be mitigated by 120 times. As referenced Figure 12 As further described, although a thermal path is created, the PN junction structure 115 blocks the signal path to the carrier substrate 302. That is, the PN junction structure 115 blocks the electrical coupling between the gate stack 108 and the carrier substrate 302, while allowing thermal coupling between the gate stack 108 and the carrier substrate 302.

[0054] Figure 10C The following is illustrated along an embodiment according to this disclosure. Figure 10A A cross-sectional view of the semiconductor structure 100 cut by line segment C-C'. Figure 10C It shows the relationship with Figure 10B-1Features similarly labeled, and for brevity, will not be described again. As shown, transistor device 110 includes channel region 104a having a plurality of transistor channels 104a-1 connected between S / D regions 104b. Transistor channels 104a-1 are surrounded by gate stack 108 having gate dielectric 108a and gate electrode 108b above the gate dielectric 108a. As described above, gate stack 108 can be thermally routed to carrier substrate 302. Dielectric structure 113 surrounds and embeds a portion of gate stack 108, S / D region 104b, and S / D contact 214 above S / D region 104b. This dielectric structure 113 may include the previously described spacer feature 108c and other dielectric layers. In an embodiment, dielectric structure 113 includes silicon nitride. Please note that one of the S / D regions 104b may be routed to an adjacent active region having epitaxial feature 105 and to the back-side metal feature 245 corresponding to the drain node of transistor device 110. Please note that the other of the S / D regions 104b may be routed directly to the back-side metal feature 245 corresponding to the source node of transistor device 110 (e.g., directly through a back-side via 242 between the S / D region 104b and the back-side metal feature 245). Please note that the gate electrode 108b of the gate stack 108 may be routed to an adjacent active region having epitaxial feature 107 and to the back-side metal feature 245 corresponding to the gate node of transistor device 110. Epitaxial features 105 and 107 are extended epitaxial features that provide spacing margins for routing the drain, source, and gate terminals of transistor device 110. S / D contact 214 is disposed above and engaged on epitaxial feature 105, and gate contact 218 is disposed above and engaged on epitaxial feature 105. S / D region 104b, epitaxial features 105 and 107, S / D contact 214 and gate contact 218 are surrounded and embedded in the previously described dielectric structure 113.

[0055] Figures 11A to 11C The dimensions of metal lines and vias for heat-conducting paths and functional circuit paths according to various embodiments of this disclosure are shown. Metal lines and vias that are part of thermal path metal line 227 are labeled metal line 227a and metal via 227b. And metal lines and vias that are part of functional circuit paths such as gate path metal line 225 are labeled metal line 225a and metal via 225b. Figures 11A to 11CAs shown, metal line 227a can typically be shorter than metal line 225a. This is because metal line 227a does not need to be routed to other vias connected to signal or power lines. Instead, metal line 227a only needs to provide a vertical path to the carrier substrate 302. In this embodiment, metal line 227a has a width d1, the shortest metal line 225a has a width d2, and metal line 227a is shorter than the shortest metal line 225a.

[0056] like Figure 11A As shown, the metal via 227b can have a larger dimension than the metal via 225b (e.g., wider in the x-direction). For example, the metal via 227b has a width d3, and the metal via 225b has a width d4, with width d3 being greater than width d4. The wider dimension increases the surface contact with the metal line 227a. Figure 11B As shown, the metal via 227b can have similar dimensions to the metal via 225b. For example, both metal vias 227b and 225b have a width d4. However, multiple metal vias 227b can exist connecting the metal lines 227a to increase surface contact. Figure 11C As shown, the metal via 227b can have similar dimensions to the metal wire 227a to maximize surface contact. For example, both the metal via 227b and the metal wire 227a have a width d1. In any case, short metal wires 227a but dense metal vias 227b or even large metal vias 227b (e.g., slot vias) can be used for efficient thermal bonding.

[0057] Figure 12 A circuit diagram of multiple transistor devices 110 is shown, wherein their gates are coupled to a carrier, such as the carrier substrate 302 described above. As shown, multiple thermal paths exist coupled between the respective gates and the common carrier. Each thermal path includes a reverse-biased diode, which can be implemented via the PN junction structure 115 described herein. The reverse diode prevents the gates of the multiple transistor devices 110 from short-circuiting together due to the common carrier. For example, when a voltage of 1V is applied to the first transistor device 110, the gates of the second, third, and fourth transistor devices 110 remain at 0V. This is because the reverse-biased diode coupled to the first transistor device 110 prevents electrical signals from reaching the common carrier. Nevertheless, heat is still transferred to the common carrier through the thermal paths. In a similar manner, if a voltage is applied to the second, third, or fourth transistor device 110, the gates of the other transistor devices 110 will remain at 0V due to their respective reverse-biased diodes.

[0058] Figure 13A bonding between a device wafer 200 and a carrier wafer 300 according to an embodiment of the present disclosure is shown. As shown, the bonding can bond a plurality of bonding metal contacts 322a to a plurality of bonding metal contacts 322b. Each bonding between metal contacts 322a and metal contacts 322b completes a thermal path for the transistor device 110. The plurality of thermal paths are transmitted through, as described above... Figure 12 The reverse bias diodes configured and described are electrically isolated from each other.

[0059] While not limiting, this disclosure provides advantages for semiconductor structures with back-side characteristics by incorporating thermal paths between the transistor device and the carrier substrate. One exemplary advantage is that the carrier substrate absorbs heat generated by the transistor device. Another exemplary advantage is that the target is connected to the gate of the transistor device to maximize thermal relaxation. Yet another exemplary advantage is that multiple transistor devices are thermally coupled to a common carrier substrate. Yet another exemplary advantage is the use of a PN junction structure that provides electrical isolation between different thermal paths to prevent short-circuit problems.

[0060] One aspect of this disclosure relates to a semiconductor structure. The semiconductor structure includes a device layer having transistor devices and a PN junction structure coupled to the transistor devices. The transistor devices include a channel region between source / drain (S / D) regions and a gate stack above the channel region. The PN junction structure includes a first doped region and a second doped region, with the first doped region electrically connected to the gate stack. This semiconductor structure includes a front-side inline interconnect structure above the front side of the device layer, the front-side inline interconnect structure including a thermal path metal feature electrically connected to the second doped region of the PN junction structure. This semiconductor structure includes a bonding oxide layer above the front-side inline interconnect structure, the bonding oxide layer embedding thermal path metal contacts electrically connected to the thermal path metal features. This semiconductor structure includes a carrier substrate above the bonding oxide layer, the carrier substrate resting on the top surface of the thermal path metal contacts.

[0061] In this embodiment, the carrier substrate is a semiconductor material.

[0062] In an embodiment, the thermal path metal features include metal lines vertically disposed between metal vias, and the front internal interconnect structure also includes an intermetallic dielectric (IMD) layer embedded in the metal lines and metal vias.

[0063] In one embodiment, the front internal interconnect structure also includes a front gate metal feature electrically connected to the gate stack.

[0064] In an embodiment, the device layer further includes another transistor device, and also includes a backside interconnect structure on the back side of the device layer, wherein the backside interconnect structure includes a backside metal feature electrically connected to the S / D region of the other transistor device, and the S / D region of the other transistor device is electrically connected to the gate stack through a frontside gate metal feature in the frontside interconnect structure.

[0065] In a further embodiment, the device layer further includes an isolation layer for embedding a transistor device, another transistor device, and a PN junction structure, wherein the back-side metal features include a back-side via having a top surface substantially coplanar with the bottom surface of the isolation layer.

[0066] In an embodiment, the first doped region is adjacent to the second doped region, the first doped region is doped with a first type dopant, and the second doped region is doped with a second type dopant that is opposite to the first type dopant.

[0067] In another embodiment, the S / D region of the transistor device is doped with an n-type dopant, the first doped region is doped with an n-type dopant, and the second doped region is doped with a p-type dopant.

[0068] In another embodiment, the S / D region of the transistor device is doped with a p-type dopant, the first doped region is doped with a p-type dopant, and the second doped region is doped with an n-type dopant.

[0069] In one embodiment, the device layer further includes a second transistor device and a second PN junction structure coupled to the second transistor device. The second transistor device includes a second channel region located between the second S / D regions and a second gate stack located above the second channel region. The second PN junction structure includes a third doped region and a fourth doped region, the third doped region being electrically connected to the gate electrode of the second gate stack. The front-side interconnect structure also includes a second thermal path metal feature electrically connected to the fourth doped region of the second PN junction structure. A bonding oxide layer is embedded with a second thermal path metal contact electrically connected to the second thermal path metal feature. A carrier substrate is located on the top surface of the second thermal path metal contact.

[0070] Another aspect of this disclosure relates to a semiconductor structure. This semiconductor structure includes a transistor device having a channel region between source / drain (S / D) regions and a gate stack above the channel region. The semiconductor structure includes a PN junction structure having a first doped region and a second doped region with opposite doping to the first doped region, and the first doped region is electrically connected to the gate stack. The semiconductor structure includes a thermal path metal feature located above the PN junction structure and electrically connected to the second doped region of the PN junction structure. The semiconductor structure includes a carrier substrate located above and in metal contact with the thermal path metal feature.

[0071] In one embodiment, the semiconductor structure further includes a bonding oxide layer located between the thermal path metal feature and the carrier substrate. The thermal path metal contact directly contacts the carrier substrate and penetrates the bonding oxide layer to land on the top metal feature of the thermal path metal feature.

[0072] In an embodiment, the semiconductor structure further includes an isolation structure, in which transistor devices and PN junction structures are embedded. Above the isolation structure is an interlayer dielectric (ILD) structure, a gate via embedded in the gate stack, a first metal electrode embedded in a first doped region, a second metal electrode embedded in a second doped region, a first PN junction via embedded in the first metal electrode, and a second PN junction via embedded in the second metal electrode. The semiconductor structure also includes a front-side interconnect structure above the ILD structure, the front-side interconnect structure having an intermetallic dielectric (IMD) structure, a first metal line embedded in the gate via, and a first PN junction via and a second metal line embedded in the second PN junction via, wherein the top surfaces of the first metal line and the second metal line are substantially coplanar.

[0073] In another embodiment, the thermal path metal feature includes thermal path metal lines vertically disposed between thermal path metal vias, and the first metal line is the bottommost metal line of the thermal path metal lines.

[0074] In another embodiment, the semiconductor structure further includes a second transistor device having a second channel region located between the second S / D regions and a second gate stack above the second channel region, and one of the second S / D regions being electrically connected to one of the gate stacks through a conductive path having a via located in a second metal line.

[0075] In the embodiment, the first doped region and the second doped region are laterally adjacent, and the first doped region is separated from the second doped region through a doping channel.

[0076] Another aspect of this disclosure relates to a method for forming a semiconductor structure. This method includes forming transistor devices in a device layer above a substrate, each transistor device having a channel region between source / drain (S / D) regions and a gate stack above the channel region; forming PN junction structures in the device layer, each PN junction structure having a first doped region and a second doped region doped opposite to the first doped region, the first doped region being electrically connected to one of the gate stacks; and forming a front-side interconnect structure above the device layer, the front-side interconnect structure including gate path metal lines electrically connected to the gate stacks and thermal path metal lines electrically connected to the second doped regions of the PN junction structures. A first bonding oxide is deposited above the front-side interconnect structure, the first bonding oxide being embedded in a first bonding metal contact on the top surface of a thermal path metal line; a carrier wafer structure having a second bonding oxide is formed above a carrier substrate, the second bonding oxide being embedded in a second bonding metal contact above the carrier substrate; a bonding process is performed to bond the first bonding oxide to the second bonding oxide such that the first bonding metal contact directly contacts the second bonding metal contact; the substrate is thinned from the back side to expose the transistor device in the device layer; a back-side interconnect structure is formed on the back side of the transistor device.

[0077] In an embodiment, the method further includes forming second transistor devices in a device layer, each second transistor device having a second channel region located between second source / drain (S / D) regions and a second gate stack located above the second channel region. The formation of the backside interconnect structure includes forming backside metal features electrically connected to the second source / drain (S / D) regions, the second S / D regions being electrically connected to one of the gate stacks.

[0078] In one embodiment, forming a carrier wafer structure includes forming a second bonding oxide on a carrier substrate; patterning the second bonding oxide to form trenches exposing the carrier substrate; and forming second bonding metal contacts in the trenches.

[0079] In an embodiment, the method further includes forming a gate via above the gate stack of the transistor device; forming a first metal electrode on a first doped region; forming a second metal electrode on a second doped region; forming a first PN junction via connected to the first metal electrode; and forming a second PN junction via connected to the second metal electrode. The front-side interconnect structure includes bottom metal lines of gate path metal lines formed on the gate via and the first PN junction via, and bottom metal lines of thermal path metal lines formed on the second PN junction via. The top surfaces of the bottom metal lines of the gate path metal lines and the thermal path metal lines are substantially coplanar.

[0080] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A device layer having a transistor device and a PN junction structure coupled to the transistor device, the transistor device including a channel region between a source / drain region and a gate stack above the channel region, the PN junction structure including a first doped region and a second doped region, and the first doped region being electrically connected to the gate stack. A front-side internal interconnect structure is located above the front side of the device layer, and the front-side internal interconnect structure includes a thermal path metal feature electrically connected to the second doped region of the PN junction structure; A bonding oxide layer is embedded above the front inner interconnect structure, the bonding oxide layer being electrically connected to the thermal path metal contact of the thermal path metal feature; as well as A carrier substrate, above the bonding oxide layer, is located on the top surface of the thermal path metal contact.

2. The semiconductor structure according to claim 1, characterized in that, The thermal path metal feature includes metal lines vertically disposed between metal vias, and the front internal interconnect structure also includes an intermetallic dielectric layer embedded in the metal lines and the metal vias.

3. The semiconductor structure according to claim 1, characterized in that, The front internal interconnect structure also includes a front gate metal feature electrically connected to the gate stack.

4. The semiconductor structure according to claim 1, characterized in that, The device layer also includes another transistor device, and further includes: The back-side internal interconnect structure is located above the back side of the device layer. The back-side interconnect structure includes a back-side metal feature electrically connected to the source / drain region of the other transistor device. The source / drain region of the other transistor device is electrically connected to the gate stack via a front gate metal feature in the front interconnect structure.

5. The semiconductor structure according to claim 4, characterized in that, The device layer also includes an isolation layer into which the transistor device, the other transistor device, and the PN junction structure are embedded, wherein the back-side metal features include a back-side via having a top surface substantially coplanar with the bottom surface of the isolation layer.

6. The semiconductor structure according to claim 1, characterized in that, The device layer further includes a second transistor device and a second PN junction structure coupled to the second transistor device. The second transistor device includes a second channel region located between a second source / drain region and a second gate stack located above the second channel region. The second PN junction structure includes a third doped region and a fourth doped region, the third doped region being electrically connected to the gate electrode of the second gate stack. The front-side interconnect structure further includes a second thermal path metal feature electrically connected to the fourth doped region of the second PN junction structure. The bonding oxide layer is embedded in a second thermal path metal contact that is electrically connected to the second thermal path metal feature. The carrier substrate is located on the top surface of the second thermal path metal contact.

7. A semiconductor structure, characterized in that, include: A transistor device having a channel region located between the source and drain regions and a gate stack above the channel region; The PN junction structure has a first doped region and a second doped region doped with the opposite doping to the first doped region, wherein the first doped region is electrically connected to the gate stack. A thermal path metallic feature is located above the PN junction structure and electrically connected to the second doped region of the PN junction structure; as well as A carrier substrate is located above and in contact with the thermal path metal feature.

8. The semiconductor structure according to claim 7, characterized in that, Also includes: A bonding oxide layer is formed between the thermal path metal feature and the carrier substrate; as well as A thermal path metal contact that directly contacts the carrier substrate and penetrates the bonding oxide layer to be on the top metal feature of the thermal path metal feature.

9. The semiconductor structure according to claim 7, characterized in that, Also includes: An isolation structure is provided, in which the transistor device and the PN junction structure are embedded; An interlayer dielectric structure is located above the isolation structure and is embedded in the gate stack, a gate via, a first metal electrode embedded in the first doped region, a second metal electrode embedded in the second doped region, a first PN junction via embedded in the first metal electrode, and a second PN junction via embedded in the second metal electrode; and A front-side internal interconnect structure is located above the interlayer dielectric structure. The front-side internal interconnect structure has an intermetallic dielectric structure, a first metal wire embedded in the gate via, and a first PN junction via and a second metal wire embedded in the second PN junction via, wherein the top surfaces of the first metal wire and the second metal wire are substantially coplanar.

10. The semiconductor structure according to claim 7, characterized in that, The first doped region is laterally adjacent to the second doped region, and the first doped region is separated from the second doped region by a doping channel.

Images