Chip packaging structure

Abstract

The utility model discloses a chip packaging structure, and belongs to the technical field of semiconductors. The chip packaging structure comprises a first rewiring structure, the first rewiring structure comprises a first rewiring layer and a first circuit layer, the first rewiring layer comprises a first dielectric layer and a second circuit layer penetrating through the first dielectric layer, the first circuit layer is located on the first rewiring layer and connected with the second circuit layer, and the second circuit layer is located on the second dielectric layer and connected with the first dielectric layer; the first circuit layer comprises a plurality of circuits which are arranged at intervals; the first chip is located on the first rewiring structure and connected with the first circuit layer; and the first packaging layer covers the first chip and the first rewiring structure and is filled among the plurality of circuits in the first circuit layer. The structure can be simplified, the cost is reduced, and the structural flexibility is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure. Background Technology

[0002] In related technologies, such as Figure 1 As shown, the chip packaging structure includes a redistribution structure 100, a chip 200, and a packaging layer 300. The redistribution structure 100 includes a bottom circuit layer 101, a bottom dielectric layer 102, a connection structure 103, a top circuit layer 104, and a top dielectric layer 105. The bottom dielectric layer 102 covers the bottom circuit layer 101 and has a first opening 106 corresponding to the position of the bottom circuit layer 101. The connection structure 103 fills the first opening 106 and is connected to the bottom circuit layer 101. The top circuit layer 104 is located on the bottom dielectric layer 102 and is connected to the connection structure 103. The top dielectric layer 105 covers the top circuit layer 104 and has a second opening 107 corresponding to the position of the top circuit layer 104. The chip 200 is connected to the top circuit layer 104 at the bottom of the second opening 107. The packaging layer 300 covers the chip 200 and the top dielectric layer 105 in the redistribution structure 100. This type of chip packaging structure is complex and costly, and the thickness of the circuit layers is uncontrollable, affecting the flexibility of the structure. Utility Model Content

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a chip packaging structure that simplifies the structure, reduces costs, and improves structural flexibility.

[0004] This application provides a chip packaging structure, including:

[0005] The first redistribution structure includes a first redistribution layer and a first line layer. The first redistribution layer includes a first dielectric layer and a second line layer that penetrates the first dielectric layer. The first line layer is located on the first redistribution layer and is connected to the second line layer. The first line layer includes a plurality of lines spaced apart.

[0006] The first chip is located on the first redistribution structure and is connected to the first circuit layer;

[0007] A first packaging layer covers the first chip and the first redistribution structure, and fills the spaces between multiple lines in the first circuit layer.

[0008] According to one embodiment of this application, the first rerouting structure includes a plurality of first rerouting layers stacked together, wherein the second line layers in the plurality of first rerouting layers are connected in sequence; and the first line layers are located on the plurality of first rerouting layers.

[0009] According to one embodiment of this application, the chip packaging structure further includes:

[0010] The pads are located between the first circuit layer and the first chip, and the first chip is connected to the first circuit layer through the pads.

[0011] According to one embodiment of this application, the chip packaging structure further includes:

[0012] The second rewiring structure is located on the first chip and is connected to the first circuit layer;

[0013] The second chip is located on the second redistribution structure and is connected to the second redistribution structure;

[0014] The second packaging layer covers the second chip and the second redistribution structure.

[0015] According to one embodiment of this application, the second rerouting structure includes a second rerouting layer, the second rerouting layer including a second dielectric layer and a third circuit layer penetrating the second dielectric layer; the third circuit layer is connected to the first circuit layer and the second chip respectively.

[0016] According to one embodiment of this application, the second redistribution structure further includes a fourth circuit layer, which is located between the second redistribution layer and the second chip, and the second chip is connected to the third circuit layer through the fourth circuit layer; the fourth circuit layer includes a plurality of lines spaced apart, and the second packaging layer further fills the spaces between the plurality of lines in the fourth circuit layer.

[0017] According to one embodiment of this application, the second rerouting structure includes a plurality of stacked and connected fifth line layers, the plurality of fifth line layers being respectively connected to the first line layer and the second chip; each fifth line layer includes a plurality of lines spaced apart, and the second encapsulation layer further fills the spaces between the plurality of lines in each fifth line layer.

[0018] According to one embodiment of this application, the chip packaging structure further includes:

[0019] The conductive pillars are disposed between the first rewiring structure and the second rewiring structure, spaced apart from the first chip, and are respectively connected to the first circuit layer and the second rewiring structure;

[0020] The first encapsulation layer is also disposed around the conductive pillar.

[0021] According to one embodiment of this application, the chip packaging structure further includes:

[0022] A protective layer is located on the side of the first rewiring structure opposite to the first chip and covers the second circuit layer.

[0023] According to one embodiment of this application, the first dielectric layer comprises resin; and / or, the first encapsulation layer comprises resin.

[0024] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects:

[0025] The second circuit layer in the first redistribution layer penetrates the first dielectric layer and is directly connected to the first circuit layer. There is no need for a connection structure between the first circuit layer and the second circuit layer. Furthermore, there is no need to set a dielectric layer between multiple circuits in the first circuit layer. They are directly filled by the first packaging layer, which simplifies the chip packaging structure and reduces the cost of the chip packaging structure. Moreover, by controlling the thickness of the first redistribution layer, the thickness of the second circuit layer can be controlled, which improves the structural flexibility and helps to improve the stability and reliability of the chip packaging structure.

[0026] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0027] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0028] Figure 1 This is a schematic diagram of a chip packaging structure in related technologies;

[0029] Figure 2 This is one of the schematic diagrams of the chip packaging structure provided in the embodiments of this application;

[0030] Figure 3 This is a second schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0031] Figure 4 This is the third schematic diagram of the chip packaging structure provided in the embodiments of this application. Detailed Implementation

[0032] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0033] The chip packaging structure provided in the embodiments of this application is described below with reference to the accompanying drawings.

[0034] Figure 2 This is one of the schematic diagrams of the chip packaging structure provided in the embodiments of this application.

[0035] like Figure 2 As shown, the chip packaging structure provided in this application embodiment includes a first redistribution structure 1, a first chip 2, and a first packaging layer 31.

[0036] The first redistribution structure 1 includes a first redistribution layer 10 and a first line layer 11. The first redistribution layer 10 includes a first dielectric layer 15 and a second line layer 12 that penetrates the first dielectric layer 15. The first line layer 11 is located on the first redistribution layer 10 and is connected to the second line layer 12. The first line layer 11 includes a plurality of lines spaced apart.

[0037] The second circuit layer 12 may include a plurality of lines spaced apart, and the plurality of lines of the second circuit layer 12 respectively penetrate the first dielectric layer 15. The plurality of lines of the first circuit layer 11 are correspondingly connected to the plurality of lines of the second circuit layer 12. The materials of the first circuit layer 11 and the second circuit layer 12 may include metals such as copper.

[0038] During the fabrication of the first redistribution layer 10, a second circuit layer 12 can be formed first, followed by the formation of a first dielectric layer 15 covering the second circuit layer 12. The first dielectric layer 15 fills the spaces between multiple circuits in the second circuit layer 12. Then, the first dielectric layer 15 and the second circuit layer 12 are thinned by grinding to expose the second circuit layer 12. By controlling the degree of grinding of the first dielectric layer 15 and the second circuit layer 12, the thickness of the second circuit layer 12 can be controlled. Maintaining a suitable thickness for the second circuit layer 12 helps improve the stability and reliability of the chip packaging structure.

[0039] During the fabrication of the first circuit layer 11, a first mask layer is first formed on the first redistribution layer 10. The first mask layer has a first mask opening, and then the first circuit layer 11 is formed in the first mask opening. After removing the first mask layer, there is no need to cover the first circuit layer 11 with a dielectric layer, which simplifies the process flow and simplifies the first redistribution structure 1.

[0040] The first chip 2 is located on the first redistribution structure 1 and is connected to the first circuit layer 11. For example... Figure 2As shown, the first chip 2 is located on the side of the first circuit layer 11 opposite to the first redistribution layer 10. The first chip 2 can be connected to multiple circuits of the first circuit layer 11. There can be one or more first chips 2. When the chip package structure includes multiple first chips 2, the multiple first chips 2 are respectively located on the first redistribution structure 1 and respectively connected to the first circuit layer 11 in the first redistribution structure 1. The first chip 2 may include radio frequency chips, or other functional chips, which are not specifically limited here.

[0041] The first encapsulation layer 31 covers the first chip 2 and the first redistribution structure 1, and fills the spaces between multiple lines in the first circuit layer 11. For example... Figure 2 As shown, the first encapsulation layer 31 covers the first chip 2, covers the upper surface of the first redistribution structure 1, and fills the spaces between multiple lines in the first circuit layer 11.

[0042] In this embodiment, the second circuit layer 12 in the first redistribution layer 10 penetrates the first dielectric layer 15 and is directly connected to the first circuit layer 11. That is, the second circuit layer 12 and the first circuit layer 11 do not require a connection structure, and the first circuit layer 11 does not need to be covered by a dielectric layer or have openings in it. The first circuit layer 11 is directly connected to the first chip 2, and no dielectric layer is needed between the multiple circuits of the first circuit layer 11; they are directly filled by the first packaging layer 31, simplifying the chip packaging structure and reducing its cost. Furthermore, by controlling the thickness of the first redistribution layer 10, the thickness of the second circuit layer 12 can be controlled, improving structural flexibility. Controlling the thickness of the second circuit layer 12 to a suitable level helps improve the stability and reliability of the chip packaging structure.

[0043] In some embodiments, the first rerouting structure 1 includes a plurality of stacked first rerouting layers 10, with second line layers 12 of the plurality of first rerouting layers 10 sequentially connected. The first rerouting structure 1 may include N first rerouting layers 10, which are stacked and connected sequentially, where N > 1. Each first rerouting layer 10 may include a first dielectric layer 15 and a second line layer 12 penetrating the first dielectric layer 15, and each second line layer 12 may include a plurality of lines spaced apart. The lines of the second line layers 12 in adjacent first rerouting layers 10 are connected, such that the second line layers 12 of the N first rerouting layers 10 are sequentially connected.

[0044] The first line layer 11 is located on a plurality of first redistribution layers 10. The first line layer 11 is located on the top first redistribution layer among the plurality of first redistribution layers 10, and the lines of the first line layer 11 are connected to the lines of the second line layer 12 in the top first redistribution layer.

[0045] In some embodiments, the first dielectric layer 15 comprises a resin. The resin may include compound, etc. Compound is composed of materials such as resin, filler, hardener, and catalyst.

[0046] In related technologies, the dielectric layer of the chip packaging structure uses materials such as PI (Polyimide) adhesive. PI adhesive is expensive and has unstable physical properties, making it prone to abnormal problems such as delamination, peeling, and warping, which affect the reliability and yield of the chip packaging structure.

[0047] In this embodiment, the first dielectric layer 15 can be made of resin material. The physical properties of resin material are more stable than those of PI glue, which reduces the risk of abnormal problems such as delamination, peeling and warping in the chip packaging structure, improves the reliability and yield of the chip packaging structure, and the cost of resin material is lower, further reducing the cost of chip packaging structure.

[0048] In some embodiments, the first encapsulation layer 31 comprises resin. The first encapsulation layer 31 may also comprise other materials, which are not limited here.

[0049] In this embodiment, the materials of the first dielectric layer 15 and the first encapsulation layer 31 can be the same, such as both being resin, in order to reduce the types of main materials of the chip packaging structure, improve the stress control of the chip packaging structure, and further improve the reliability of the chip packaging structure.

[0050] In some embodiments, such as Figure 2 As shown, the chip package structure also includes a pad (i.e., a first pad 4), which is located between the first circuit layer 11 and the first chip 2. The first chip 2 is connected to the first circuit layer 11 via the first pad 4. The first chip 2 may include a first bump 20, which is connected to the first pad 4, allowing the first chip 2 to be connected to the circuitry of the first circuit layer 11 in the first redistribution structure 1 via the first bump 20 and the first pad 4. The material of the first pad 4 may include metals such as copper.

[0051] In some embodiments, such as Figure 3 As shown, the chip package structure also includes a second redistribution structure 5 and a second chip 6. The second redistribution structure 5 is located on the first chip 2 and is connected to the first circuit layer 11. The second chip 2 is located on the second redistribution structure 5 and is connected to the second redistribution structure 5. The second packaging layer 32 covers the second chip 6 and the second redistribution structure 5.

[0052] The second redistribution structure 5 is located on the side of the first packaging layer 31 opposite to the first redistribution structure 1, and the second redistribution structure 5 is connected to the lines of the first circuit layer 11. The second chip 6 is located on the side of the second redistribution structure 5 opposite to the first chip 2, and the second chip 6 is connected to the second redistribution structure 5. There can be one or more second chips 6. When the chip packaging structure includes multiple second chips 6, the multiple second chips 6 are respectively located on the second redistribution structure 5 and respectively connected to the second redistribution structure 5. The second chip 6 may include radio frequency chips, or other functional chips, which are not specifically limited here.

[0053] In some embodiments, such as Figure 3 and Figure 4 As shown, the chip package structure also includes a second pad 7, which is located between the second redistribution structure 5 and the second chip 6. The second chip 6 is connected to the second redistribution structure 5 via the second pad 7. The second chip 6 may include a second bump 60, which is connected to the second pad 7, thus connecting the second chip 6 to the second redistribution structure 5 via the second bump 60 and the second pad 7. The material of the second pad 7 may include a metal such as copper.

[0054] In some embodiments, the second redistribution structure 5 includes a second redistribution layer 50, which includes a second dielectric layer 16 and a third line layer 13 penetrating the second dielectric layer 16. The third line layer 13 may include a plurality of lines spaced apart, and the plurality of lines of the third line layer 13 respectively penetrate the second dielectric layer 16.

[0055] The third circuit layer 13 is connected to the first circuit layer 11 and the second chip 6. Multiple lines in the third circuit layer 13 are correspondingly connected to multiple lines in the first circuit layer 11, and the second chip 6 can be connected to multiple lines in the third circuit layer 13. The material of the third circuit layer 13 may include metals such as copper.

[0056] During the fabrication of the second redistribution layer 50, a third circuit layer 13 can be formed first, followed by the formation of a second dielectric layer 16 covering the third circuit layer 13, with the second dielectric layer 16 filling the spaces between multiple circuits in the third circuit layer 13. Then, the second dielectric layer 16 and the third circuit layer 13 are thinned by grinding to expose the third circuit layer 13. By controlling the degree of grinding of the second dielectric layer 16 and the third circuit layer 13, the thickness of the third circuit layer 13 can be controlled. Maintaining a suitable thickness for the third circuit layer 13 helps improve the stability and reliability of the chip packaging structure.

[0057] In some embodiments, the second dielectric layer 16 comprises resin. In this embodiment, the second dielectric layer 16 may be made of resin material, which reduces the risk of abnormal problems such as delamination, peeling, and warping in the chip packaging structure, improves the reliability and yield of the chip packaging structure, and the resin material has a low cost, further reducing the cost of the chip packaging structure.

[0058] In some embodiments, the second encapsulation layer 32 comprises resin. The second encapsulation layer 32 may also comprise other materials, which are not limited herein.

[0059] In this embodiment, the second dielectric layer 16 and the second encapsulation layer 32 can be made of the same material, such as resin, to reduce the types of main materials used in the chip packaging structure, improve the chip packaging structure's control over stress, and further enhance the reliability of the chip packaging structure.

[0060] The materials of the first dielectric layer 15, the first encapsulation layer 31, the second dielectric layer 16, and the second encapsulation layer 32 can be the same, such as resin, to further reduce the types of main materials used in the chip packaging structure, further improve the chip packaging structure's control over stress, and further enhance the reliability of the chip packaging structure.

[0061] In some embodiments, the second rerouting structure 5 includes a plurality of stacked second rerouting layers 50, with the second line layers 12 of the plurality of second rerouting layers 50 sequentially connected. The second rerouting structure 5 may include N second rerouting layers 50, which are stacked and connected sequentially, where N > 1. Each second rerouting layer 50 may include a second dielectric layer 16 and a third line layer 13 penetrating the second dielectric layer 16, and each third line layer 13 may include a plurality of lines spaced apart. The lines of the third line layers 13 in adjacent second rerouting layers 50 are connected, such that the third line layers 13 in the N second rerouting layers 50 are sequentially connected.

[0062] In some embodiments, such as Figure 3 As shown, the second redistribution structure 5 further includes a fourth circuit layer 14, which is located between the second redistribution layer 50 and the second chip 6. The second chip 6 is connected to the third circuit layer 13 through the fourth circuit layer 14. The fourth circuit layer 14 includes a plurality of lines spaced apart, and the second packaging layer 32 is also filled between the plurality of lines in the fourth circuit layer 14.

[0063] The fourth circuit layer 14 is located on the top second redistribution layer among the plurality of second redistribution layers 50, and the circuits of the fourth circuit layer 14 are connected to the circuits of the third circuit layer 13 in the top second redistribution layer. The second packaging layer 32 covers the second chip 6, covers the upper surface of the second redistribution structure 5, and fills the spaces between the plurality of circuits in the fourth circuit layer 14.

[0064] During the fabrication of the fourth circuit layer 14, a second mask layer with a second mask opening is first formed on the second redistribution layer 50, and then the fourth circuit layer 14 is formed in the second mask opening. After removing the second mask layer, there is no need to cover the fourth circuit layer 14 with a dielectric layer, which simplifies the process flow and simplifies the second redistribution structure 5.

[0065] In the case where the second redistribution structure 5 includes a second redistribution layer 50 (including a second dielectric layer 16 and a third line layer 13) and a fourth line layer 14, such as Figure 3 As shown, the second pad 7 is located between the fourth circuit layer 14 and the second chip 6, and the second chip 6 is connected to the fourth circuit layer 14 through the second pad 7. The second bump 60 of the second chip 6 is connected to the second pad 7, so that the second chip 6 is connected to the circuit of the fourth circuit layer 14 in the second redistribution structure 5 through the second bump 60 and the second pad 7.

[0066] In some embodiments, such as Figure 4 As shown, the second redistribution structure 5 includes a plurality of stacked and connected fifth circuit layers 17, which are respectively connected to the first circuit layer 11 and the second chip 6. Each fifth circuit layer 17 includes a plurality of lines spaced apart, and the second encapsulation layer 32 is further filled between the plurality of lines in each fifth circuit layer 17.

[0067] Multiple lines in adjacent fifth circuit layers 17 are connected accordingly. The lines of the bottom fifth circuit layer in the multiple fifth circuit layers 17 are connected to the lines of the first circuit layer 11, and the lines of the top fifth circuit layer in the multiple fifth circuit layers 17 are connected to the second chip 6. The second packaging layer 32 covers the second chip 6, covers the upper surface of the second redistribution structure 5, and fills the spaces between the multiple lines in each fifth circuit layer 17.

[0068] In the fabrication process of the second rewiring structure 5, taking the second rewiring structure 5 including two fifth circuit layers 17 as an example, a third mask layer is first formed on the first packaging layer 31. The third mask layer has a third opening, and the bottom fifth circuit layer is formed in the third opening. Then, a fourth mask layer is formed on the third mask layer. The fourth mask layer has a fourth opening, and the top fifth circuit layer is formed in the fourth opening. After forming the bottom fifth circuit layer and the top fifth circuit layer (i.e., forming the second rewiring structure 5), the third mask layer and the fourth mask layer are removed by a single adhesive removal process. After mounting the second chip 6, the second packaging layer 32 encapsulates the second chip 6 while filling the spaces between multiple lines in each fifth circuit layer 17. There is no need to form an additional dielectric layer between the multiple lines in the fifth circuit layer 17, simplifying the process flow, simplifying the second rewiring structure 5, and further simplifying the chip packaging structure.

[0069] In the case where the second rewiring structure 5 includes multiple fifth line layers 17, such as Figure 4 As shown, the second pad 7 is located between the bottom fifth circuit layer and the second chip 6, and the second chip 6 is connected to the bottom fifth circuit layer through the second pad 7. The second bump 60 of the second chip 6 is connected to the second pad 7, so that the second chip 6 is connected to the circuit of the bottom fifth circuit layer in the second redistribution structure 5 through the second bump 60 and the second pad 7.

[0070] In some embodiments, the chip packaging structure further includes conductive pillars 8, which are disposed between the first chip 2 and the first redistribution structure 1 and the second redistribution structure 5, and are respectively connected to the first circuit layer 11 and the second redistribution structure 5. The first packaging layer 31 is also disposed around the conductive pillars 8.

[0071] There can be multiple conductive posts 8. For example... Figure 3 and Figure 4 As shown, multiple conductive pillars 8 can be located in the first encapsulation layer 31 between the first redistribution structure 1 and the second redistribution structure 5, spaced apart from the first chip 2. The conductive pillars 8 can be copper pillars, etc.

[0072] In the case where the second redistribution structure 5 includes a second redistribution layer 50 (including a second dielectric layer 16 and a third line layer 13) and a fourth line layer 14, such as Figure 3 As shown, the bottom of the conductive post 8 is connected to the line of the first line layer 11 in the first redistribution structure 1, and the top of the conductive post 8 is connected to the line of the third line layer 13 in the second redistribution structure 5, so that the third line layer 13 of the second redistribution structure 5 and the first line layer 11 of the first redistribution structure 1 are connected through the conductive post 8.

[0073] In the case where the second rewiring structure 5 includes multiple fifth line layers 17, such as Figure 4 As shown, the bottom of the conductive post 8 is connected to the line of the first line layer 11 in the first redistribution structure 1, and the top of the conductive post 8 is connected to the line of the bottom fifth line layer in the second redistribution structure 5, so that the fifth line layer 17 of the second redistribution structure 5 and the first line layer 11 of the first redistribution structure 1 are connected through the conductive post 8.

[0074] In some embodiments, the chip packaging structure further includes a protective layer 9, which is located on the side of the first redistribution structure 1 opposite to the first chip 2 and covers the second circuit layer 12.

[0075] The protective layer 9 can be a single-layer structure or a multilayer structure. For example, the protective layer 9 may include a multilayered nickel layer, a multilayered palladium layer, and a multilayered gold layer, or a multilayered copper layer and a tin-silver mixed layer.

[0076] In this embodiment, the protective layer 9 protects the second circuit layer 12, improving the reliability of the chip packaging structure. Additionally, the protective layer 9 can also serve as a soldering layer. The side of the protective layer 9 facing away from the first redistribution structure 1 can be connected to external devices, allowing the first chip 2 to be connected to external devices via the first redistribution structure 1 and the protective layer 9.

[0077] In summary, according to the chip packaging structure provided in the embodiments of this application, the second circuit layer 12 in the first redistribution layer 10 penetrates the first dielectric layer 15, and the second circuit layer 12 is directly connected to the first circuit layer 11. That is, the second circuit layer 12 and the first circuit layer 11 do not need to be connected by a connection structure, and the first circuit layer 11 does not need to be covered by a dielectric layer, nor does it need to have openings in the dielectric layer. The first circuit layer 11 is directly connected to the first chip 2, and there is no need to set a dielectric layer between the multiple lines of the first circuit layer 11. Instead, they are directly filled by the first packaging layer 31, which simplifies the chip packaging structure, reduces the cost of the chip packaging structure, and also improves the chip packaging structure by simplifying the first redistribution layer 10. The thickness control of 0 allows for control over the thickness of the second circuit layer 12, improving structural flexibility. By controlling the thickness of the second circuit layer 12 to a suitable level, the stability and reliability of the chip packaging structure can be improved. Furthermore, both the first dielectric layer 15 and the first encapsulation layer 31 can be made of resin, reducing the types of main materials used in the chip packaging structure, improving stress control, and further enhancing the reliability of the chip packaging structure. At the same time, using resin instead of PI glue further reduces costs and lowers the risk of abnormal problems such as delamination, peeling, and warping in the chip packaging structure, improving the yield and reliability of the chip packaging structure.

[0078] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0079] In the description of this application, "multiple" means two or more.

[0080] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0081] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that, include: The first redistribution structure includes a first redistribution layer and a first line layer. The first redistribution layer includes a first dielectric layer and a second line layer that penetrates the first dielectric layer. The first line layer is located on the first redistribution layer and is connected to the second line layer. The first line layer includes a plurality of lines spaced apart. The first chip is located on the first redistribution structure and is connected to the first circuit layer; A first packaging layer covers the first chip and the first redistribution structure, and fills the spaces between multiple lines in the first circuit layer.

2. The chip packaging structure according to claim 1, characterized in that, The first rerouting structure includes a plurality of first rerouting layers stacked together, wherein the second line layers in the plurality of first rerouting layers are connected in sequence; The first routing layer is located on the plurality of first redistribution layers.

3. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes: The pads are located between the first circuit layer and the first chip, and the first chip is connected to the first circuit layer through the pads.

4. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes: The second rewiring structure is located on the first chip and is connected to the first circuit layer; The second chip is located on the second redistribution structure and is connected to the second redistribution structure; The second packaging layer covers the second chip and the second redistribution structure.

5. The chip packaging structure according to claim 4, characterized in that, The second rerouting structure includes a second rerouting layer, the second rerouting layer including a second dielectric layer and a third line layer penetrating the second dielectric layer; The third circuit layer is connected to the first circuit layer and the second chip, respectively.

6. The chip packaging structure according to claim 5, characterized in that, The second redistribution structure further includes a fourth circuit layer, which is located between the second redistribution layer and the second chip, and the second chip is connected to the third circuit layer through the fourth circuit layer; The fourth circuit layer includes a plurality of lines spaced apart, and the second encapsulation layer is further filled between the plurality of lines in the fourth circuit layer.

7. The chip packaging structure according to claim 4, characterized in that, The second rerouting structure includes a plurality of stacked and connected fifth line layers, which are respectively connected to the first line layer and the second chip; Each of the fifth line layers includes a plurality of lines spaced apart, and the second encapsulation layer further fills the spaces between the plurality of lines in each of the fifth line layers.

8. The chip packaging structure according to claim 4, characterized in that, The chip packaging structure also includes: The conductive pillars are disposed between the first rewiring structure and the second rewiring structure, spaced apart from the first chip, and are respectively connected to the first circuit layer and the second rewiring structure; The first encapsulation layer is also disposed around the conductive pillar.

9. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes: A protective layer is located on the side of the first rewiring structure opposite to the first chip and covers the second circuit layer.

10. The chip packaging structure according to any one of claims 1-9, characterized in that, The first dielectric layer comprises resin; and / or, The first encapsulation layer comprises resin.

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