Peak shaving current source for biasing circuit
By designing a peak-shaving current source using a linear current mirror circuit, a trim resistor adjustment array, and a current peak-shaving branch, the problem of traditional bias current sources being sensitive to power supply voltage fluctuations and affected by manufacturing processes is solved, achieving current stability and low power consumption.
Patent Information
- Application Number
- CN202520286257.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-02-21
AI Technical Summary
Traditional bias current sources are sensitive to power supply voltage fluctuations, affecting current stability. They are also susceptible to manufacturing process variations, leading to inconsistent performance and potentially increasing circuit noise and power consumption.
By employing a linear current mirror circuit, a trim resistor adjustment array, and a current peak-shaving branch, combined with a switching logic circuit, a peak-shaving current source is designed. Through resistor fine-tuning and transistor branches, current stability and low power consumption are achieved over a wide range.
It achieves current stability over a wide voltage and temperature range, reduces power consumption, and improves the fault tolerance of the current source and the stability of the circuit.
Smart Images
Figure CN223857626U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to integrated circuit design technical field, concretely relates to a peak regulating current source for bias circuit. BACKGROUND
[0002] With the continuous development of science and technology, DCDC converter as the key technology in the field of power management has made remarkable progress, and it has higher requirements for the power consumption and stability of internal circuit. Bias circuit plays a key role in improving stability and reducing power consumption in DCDC converter. When the bias circuit cannot provide stable voltage or current, the working point of each device cannot be determined, which will directly affect the performance of DCDC converter.
[0003] The traditional bias current source is sensitive to the fluctuation of power supply voltage, which affects the stability of current. If an operational amplifier is used, it may increase the noise and power consumption of the circuit, and an additional power supply voltage is needed. From the perspective of manufacturing, the traditional current source is also prone to inconsistent performance due to manufacturing process, and the bias circuit may not be turned off in time after the circuit is started, resulting in increased power consumption. UTILITY MODEL CONTENT
[0004] The utility model provides a peak regulating current source for bias circuit for above problems.
[0005] In order to achieve the above purpose, the utility model adopts the following technical scheme:
[0006] A peak regulating current source for bias circuit, comprising a linear current mirror circuit, a trim resistance adjustment array and a current peak regulating branch, the end 2 of the linear current mirror circuit is connected with the end 5 of the trim resistance adjustment array, the end 3 of the linear current mirror circuit is connected with the end 7 of the current peak regulating branch, the end 4 of the linear current mirror circuit is an output bias current, the end 6 of the trim resistance adjustment array is connected with the end 9 of the current peak regulating branch, and the end 8 of the current peak regulating branch is connected with the end 2 of the linear current mirror circuit and the end 5 of the trim resistance adjustment array.
[0007] Further, the linear current mirror circuit comprises a transistor MP1, a transistor MP2, a transistor MP3 and a switch logic circuit, the gate of the transistor MP1 is connected with one end of the switch logic circuit, the drain of the transistor MP1 is connected with the end 2, the gate of the transistor MP2 is connected with the other end of the switch logic circuit and the end 3, the drain of the transistor MP2 is connected with the end 3, the gate of the transistor MP3 is connected with the end 3, the drain of the transistor MP3 is connected with the end 4, and the substrates of the transistor MP1, the transistor MP2 and the transistor MP3 are connected with the VDD power supply.
[0008] Further, the switch logic circuit comprises a transmission gate TG4, a transmission gate TG5, an inverter INV and a buffer Buffer, a control end I of the transmission gate TG4 is connected with an output end of the buffer Buffer and a control end II of the transmission gate TG5, a control end II of the transmission gate TG4 is connected with an output end of the inverter INV and a control end I of the transmission gate TG5, an input end of the transmission gate TG4 is connected with a gate of the transistor MP1, an output end of the transmission gate TG4 is connected with a gate of the transistor MP2, an input end of the transmission gate TG5 is connected with a VDD power supply, an output end of the transmission gate TG5 is connected with the gate of the transistor MP2, and an input end of the buffer Buffer and an input end of the inverter INV are used for receiving a control signal.
[0009] Further, the trim resistance adjustment array comprises four groups of same trim resistance modules, the trim resistance module comprises an inverter INV0, a transmission gate TG0, a buffer Buffer0 and a resistance R0, a control end I of the transmission gate TG0 is connected with an output end of the buffer Buffer0, a control end II of the transmission gate TG0 is connected with an output end of the inverter INV, an input end and an output end of the transmission gate TG0 are connected at two ends of the resistance R0 respectively, an input end of the buffer Buffer0 and an input end of the inverter INV0 are used for connecting a VDD power supply or a GND power supply, the resistances R0 of the four groups of trim resistance modules are connected in series, an outer side end of one resistance R0 at an end is connected with the end head 5, an outer side end of another resistance R0 at the end is connected with one end of a resistance R1, and the other end of the resistance R1 is connected with the end head 6.
[0010] Further, the current peak regulation branch comprises a transistor MN1, a transistor MN2, a transistor MN3 and a resistance R5, a gate of the transistor MN1 is connected with the end head 8, a drain of the transistor MN1 is connected with one end of the resistance R5 and a gate of the transistor MN2, a drain of the transistor MN2 is connected with the end head 7 and a drain of the transistor MN3, a gate of the transistor MN3 is connected with the other end of the resistance R5 and the end head 9, and the source of the transistor MN1, the source of the transistor MN2 and the source of the transistor MN3 are all connected with a GND power supply.
[0011] Further, the transistor MP1, the transistor MP2 and the transistor MP3 are all P-type MOS transistors.
[0012] Further, the transistor MN1, the transistor MN2 and the transistor MN3 are all N-type MOS transistors.
[0013] Compared with the prior art, the utility model has the following advantages:
[0014] The utility model discloses adopt linear current mirror circuit, trim resistance regulation array and current peak regulation branch constitute the peak regulation current source, linear current mirror circuit design has the current mirror circuit and switch logic circuit, join switch introduction enable function, be used for the control circuit's opening and closing, trim resistance regulation array carries out resistance fine adjustment, improves the fault tolerance of current source, current peak regulation branch design has transistor MN2 and transistor MN3 two branches, realizes respective current peak value in different voltage range, makes the current in wide range be relatively smooth, under the condition that all level signals are high level, realize the current steady in 13-16nA in voltage 0~3V range, in temperature -50~150 DEG C range, the current is in 15-20nA small amplitude change, and simultaneously this circuit complexity is low, can reduce the power consumption. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 It is internal frame diagram of the utility model;
[0016] Figure 2 It is the circuit diagram of linear current mirror circuit of the utility model;
[0017] Figure 3 It is the circuit diagram of switch logic circuit of the utility model;
[0018] Figure 4 It is the circuit diagram of trim resistance regulation array of the utility model;
[0019] Figure 5 It is the circuit diagram of current peak regulation branch of the utility model;
[0020] Figure 6 It is the circuit diagram of the utility model. DETAILED DESCRIPTION
[0021] In order to further illustrate the technical scheme of the utility model, the utility model is further illustrated by the embodiment below.
[0022] As Figures 1 to 6 Shown, a kind of for biasing circuit's peak regulation current source, including linear current mirror circuit, trim resistance regulation array and current peak regulation branch, the end 2 of the linear current mirror circuit is connected with the end 5 of trim resistance regulation array, the end 3 of the linear current mirror circuit is connected with the end 7 of current peak regulation branch, the end 4 of the linear current mirror circuit is output biasing current, the end 6 of trim resistance regulation array is connected with the end 9 of current peak regulation branch, the end 8 of current peak regulation branch is connected with the end 2 of linear current mirror circuit and the end 5 of trim resistance regulation array.
[0023] The linear current mirror circuit comprises a transistor MP1, a transistor MP2, a transistor MP3 and a switch logic circuit, a gate of the transistor MP1 is connected with one end of the switch logic circuit, a drain of the transistor MP1 is connected with the terminal 2, a gate of the transistor MP2 is connected with the other end of the switch logic circuit and the terminal 3, a drain of the transistor MP2 is connected with the terminal 3, a gate of the transistor MP3 is connected with the terminal 3, a drain of the transistor MP3 is connected with the terminal 4, the substrate of the transistor MP1, the transistor MP2 and the transistor MP3 are connected with the VDD power supply, and the transistor MP1, the transistor MP2 and the transistor MP3 are P-type MOS transistors.
[0024] The switch logic circuit comprises a transmission gate TG4, a transmission gate TG5, an inverter INV and a buffer Buffer, a control end I of the transmission gate TG4 is connected with the output end of the buffer Buffer and a control end II of the transmission gate TG5, a control end II of the transmission gate TG4 is connected with the output end of the inverter INV and the control end I of the transmission gate TG5, an input end of the transmission gate TG4 is connected with the gate of the transistor MP1, an output end of the transmission gate TG4 is connected with the gate of the transistor MP2, an input end of the transmission gate TG5 is connected with the VDD power supply, an output end of the transmission gate TG5 is connected with the gate of the transistor MP2, and the input end of the buffer Buffer and the input end of the inverter INV are used for receiving a control signal.
[0025] The trim resistance adjustment array comprises four groups of same trim resistance modules, the trim resistance module comprises an inverter INV0, a transmission gate TG0, a buffer Buffer0 and a resistance R0, a control end I of the transmission gate TG0 is connected with the output end of the buffer Buffer0, a control end II of the transmission gate TG0 is connected with the output end of the inverter INV, an input end and an output end of the transmission gate TG0 are connected at two ends of the resistance R0 respectively, and the input end of the buffer Buffer0 and the input end of the inverter INV0 are used for connecting the VDD power supply or the GND power supply, the resistances R0 of the four groups of trim resistance modules are connected in series with each other, an outer side end of one resistance R0 at an end is connected with the terminal 5, an outer side end of the other resistance R0 at the end is connected with one end of a resistance R1, and the other end of the resistance R1 is connected with the terminal 6.
[0026] The current peak regulating branch comprises a transistor MN1, a transistor MN2, a transistor MN3 and a resistor R5, the gate of the transistor MN1 is connected with the terminal 8, the drain of the transistor MN1 is connected with one end of the resistor R5 and the gate of the transistor MN2, the drain of the transistor MN2 is connected with the terminal 7 and the drain of the transistor MN3, the gate of the transistor MN3 is connected with the other end of the resistor R5 and the terminal 9, the source of the transistor MN1, the transistor MN2 and the transistor MN3 are connected with the GND power supply, and the transistor MN1, the transistor MN2 and the transistor MN3 are N-type MOS transistors.
[0027] The working principle is as follows:
[0028] The peak regulating current source comprises a linear current mirror circuit, a trim resistance regulating array and a current peak regulating branch. In the current peak regulating branch, I1 is the current of the branch in which the transistor MN1 is located, the gate of the transistor MN2 is connected with the gate of the transistor MN3, and the gate of the transistor MN3 is connected with the other end of the resistor R5, so that there is a voltage difference Δv between the gate voltage of the transistor MN3 and the gate voltage of the transistor MN2. The width-length ratios of the transistors MN2 and MN3 are different, and when the circuit is powered on, the transistor MN3 is turned on first and the transistor MN2 is turned on later. According to Ohm's law, the voltage difference Δv between the gate voltage of the transistor MN3 and the gate voltage of the transistor MN2 is formula (1).
[0029] Δv = I1 × R5 (1)
[0030] In the formula, I1 is the current of the branch in which the transistor MN1 is located, and according to formula (1), the linear relationship between them is small and is not affected by temperature. For example, Figure 6 Because of the existence of the trim resistance regulating array and the resistor R5, the two output currents can be set to different peak current points, and the sum is obtained through the transistor MP2.
[0031] IB = IB1 + IB2 (2)
[0032] In the formula, IB is the current of the transistor MP2, IB1 is the current of the branch in which the transistor MN2 is located, and IB2 is the current of the branch in which the transistor MN3 is located.
[0033] The transistor MP3 and the transistor MP2 form a linear current mirror, the transistor MP3 copies the current of the transistor MP2 in proportion, and finally the stable output bias current I OUT is obtained.
[0034] The trim resistance adjustment array realizes discrete adjustment through a logic circuit, when the inverter INV0 and the buffer Buffer0 input high level, the transmission gate TG0 is turned on, the resistance R0 is short-circuited, finally resistance R1 works alone is shown, when the inverter INV0 and the buffer Buffer0 input low level, the transmission gate TG0 is turned off, the resistance R0 is connected in series to the circuit, finally resistance R0 and resistance R1 in series work are shown, fine adjustment is realized, and the on resistance of the transmission gate TG0 is much larger than the resistance R0, so the trim resistance adjustment array does not affect the turn-off and turn-on characteristics of the transmission gate TG0.
[0035] The linear current mirror circuit includes the transistor MP1, the transistor MP2, the transistor MP3 and the switch logic circuit, the switch logic circuit introduces the enable function, when the inverter INV and the buffer Buffer input high level, the transmission gate TG4 is turned on, the transmission gate TG5 is turned off, the transistor MP1, the transistor MP2 and the transistor MP3 normally work, when the inverter INV and the buffer Buffer input low level, the transmission gate TG4 is turned off, the transmission gate TG5 is turned on, the gate voltage of the transistor MP1, the transistor MP2 and the transistor MP3 is pulled up, the transistor MP1, the transistor MP2 and the transistor MP3 are completely turned off, and power consumption is reduced.
[0036] The main features and advantages of the present application are shown and described above, for those skilled in the art, it is obvious that the present application is not limited to the details of the above exemplary embodiments, and can be realized in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, the scope of the present application is defined by the appended claims rather than the above description, therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application.
[0037] In addition, it should be understood that, although the present application is described in the form of embodiments, not every embodiment contains only one independent technical solution, the description of the specification is only for the sake of clarity, those skilled in the art should regard the specification as a whole, the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.
Claims
1. A peak regulating current source for a biasing circuit, characterized by: The linear current mirror circuit, the trim resistance adjustment array and the current peak regulation branch are connected, the end 2 of the linear current mirror circuit is connected with the end 5 of the trim resistance adjustment array, the end 3 of the linear current mirror circuit is connected with the end 7 of the current peak regulation branch, the end 4 of the linear current mirror circuit is an output bias current, the end 6 of the trim resistance adjustment array is connected with the end 9 of the current peak regulation branch, and the end 8 of the current peak regulation branch is connected with the end 2 of the linear current mirror circuit and the end 5 of the trim resistance adjustment array.
2. A peak regulating current source for a biasing circuit as claimed in claim 1, characterized in that: The linear current mirror circuit comprises a transistor MP1, a transistor MP2, a transistor MP3 and a switch logic circuit, the gate of the transistor MP1 is connected with one end of the switch logic circuit, the drain of the transistor MP1 is connected with the end 2, the gate of the transistor MP2 is connected with the other end of the switch logic circuit and the end 3, the drain of the transistor MP2 is connected with the end 3, the gate of the transistor MP3 is connected with the end 3, the drain of the transistor MP3 is connected with the end 4, and the substrates of the transistor MP1, the transistor MP2 and the transistor MP3 are connected with a VDD power supply.
3. A peak regulating current source for a biasing circuit according to claim 2, wherein: The switch logic circuit comprises a transmission gate TG4, a transmission gate TG5, an inverter INV and a buffer Buffer, the control end I of the transmission gate TG4 is connected with the output end of the buffer Buffer and the control end II of the transmission gate TG5, the control end II of the transmission gate TG4 is connected with the output end of the inverter INV and the control end I of the transmission gate TG5, the input end of the transmission gate TG4 is connected with the gate of the transistor MP1, the output end of the transmission gate TG4 is connected with the gate of the transistor MP2, the input end of the transmission gate TG5 is connected with the VDD power supply, the output end of the transmission gate TG5 is connected with the gate of the transistor MP2, and the input end of the buffer Buffer and the input end of the inverter INV are used for receiving a control signal.
4. A peak-boosting current source for a biasing circuit according to claim 3, wherein: The trim resistance adjustment array comprises four groups of same trim resistance modules, the trim resistance module comprises an inverter INV0, a transmission gate TG0, a buffer Buffer0 and a resistance R0, the control end I of the transmission gate TG0 is connected with the output end of the buffer Buffer0, the control end II of the transmission gate TG0 is connected with the output end of the inverter INV, the input end and the output end of the transmission gate TG0 are connected at both ends of the resistance R0, the input end of the buffer Buffer0 and the input end of the inverter INV0 are used for connecting the VDD power supply or the GND power supply, the resistances R0 of the four groups of trim resistance modules are connected in series, the outer side end of one resistance R0 at one end is connected with the end 5, the outer side end of the other resistance R0 at the other end is connected with one end of a resistance R1, and the other end of the resistance R1 is connected with the end 6.
5. A peak-boosting current source for a biasing circuit according to claim 4, wherein: The current peak regulating branch comprises a transistor MN1, a transistor MN2, a transistor MN3 and a resistor R5, the gate of the transistor MN1 is connected with the terminal 8, the drain of the transistor MN1 is connected with one end of the resistor R5 and the gate of the transistor MN2, the drain of the transistor MN2 is connected with the terminal 7 and the drain of the transistor MN3, the gate of the transistor MN3 is connected with the other end of the resistor R5 and the terminal 9, and the source of the transistor MN1, the transistor MN2 and the transistor MN3 are all connected with the GND power supply.
6. A peak-boosting current source for a biasing circuit according to claim 2, wherein: The transistor MP1, the transistor MP2 and the transistor MP3 are all P-type MOS transistors.
7. A peak-boosting current source for a biasing circuit according to claim 5, wherein: The transistor MN1, the transistor MN2 and the transistor MN3 are all N-type MOS transistors.