Battery management system, battery pack and electric tool

Abstract

The utility model discloses a battery management system, a battery pack and an electric tool. The battery management system comprises a charging NMOS (N-channel Metal Oxide Semiconductor) tube, a discharging NMOS tube, a high-side driving circuit and a micro-processing unit, the high-side driving circuit comprises a high-side driving chip, a threshold setting circuit and a bleeder circuit; and the micro-processing unit is connected with the high-side driving circuit and is used for controlling the on-off of the charging NMOS tube and the discharging NMOS tube through the high-side driving circuit. The threshold setting circuit is used for setting a threshold voltage, and the bleeder circuit is used for providing a gate-source bleeder path and a gate-source voltage clamp for the NMOS tube, so that the misconduction of the discharge NMOS tube is avoided, the accurate control of the discharge NMOS tube is realized, and the safety, the stability and the anti-interference capability of the battery management system and the electric tool are improved; and meanwhile, the high-voltage protection circuit is arranged in the COM communication circuit, so that the signal receiving circuit can be protected when the access voltage of the COM communication terminal is greater than an overload threshold value, and the safety and stability of the battery management system and the electric tool are further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of battery charging and discharging, and particularly relates to a battery management system, a battery pack and a power tool. BACKGROUND

[0002] The battery management system (BMS) of the battery pack is a key component in the battery pack, including an analog front-end (AFE) circuit, a high-side drive circuit, a micro control unit (MCU), a COM communication circuit, a control panel circuit, a Bluetooth transceiver circuit, a fan control circuit and the like, and the main responsibility is to monitor, control and protect the battery pack to ensure its safe, efficient and long-life operation.

[0003] In the high-side drive circuit, a high-side drive chip, for example, a TI BQ76200 high-side drive chip, is used to control the on-off of the charging NMOS tube and the discharging NMOS tube to realize the charging and discharging control of the battery pack. There are the following problems: in the battery management system shutdown state, the charger is connected, the discharging NMOS in the positive charging terminal CH+ loop of the battery management system is misdirected, the conduction state is not controlled, and thus uncontrolled external discharging is caused, the misdirected conduction state of the discharging NMOS changes due to the voltage fluctuation of the misdirected gate-source voltage of the discharging NMOS caused by the voltage fluctuation of the positive charging terminal CH+, and thus the temperature rise of the discharging NMOS is high; the driving capacity of the high-side drive chip is limited, the turn-off speed of the discharging NMOS is slow, and the risk of damage of the discharging NMOS is caused when the load is cut off.

[0004] The COM communication circuit includes a signal sending circuit and a signal receiving circuit, the signal sending circuit usually adopts an open drain output or an open set output circuit, which will be damaged due to overload when the COM communication terminal is connected to high voltage, and the switch tube in the circuit will be damaged due to the reverse voltage when the COM communication terminal is connected to lower than ground voltage. UTILITY MODEL CONTENT

[0005] In view of the above-mentioned defects of the prior art, the purpose of the present application is to provide a battery management system, a battery pack and a power tool to improve the safety, stability and anti-interference ability of the battery management system and the power tool.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a battery management system, comprising:

[0007] a positive charging terminal, a negative terminal, a first NMOS tube, a second NMOS tube, a high-side drive circuit and a micro processing unit;

[0008] a source of the first NMOS transistor is connected with a positive electrode of a battery of a battery pack, a drain of the first NMOS transistor is connected with a drain of the second NMOS transistor, a source of the second NMOS transistor is connected with the positive charging terminal, and a negative terminal is connected with a negative electrode of the battery of the battery pack;

[0009] The high-side drive circuit comprises a high-side drive chip and a threshold setting circuit, a charging control pin of the high-side drive chip is connected with a gate of the first NMOS transistor, and a discharging control pin of the high-side drive chip is connected with a gate of the second NMOS transistor through the threshold setting circuit;

[0010] The micro processing unit is connected with the high-side drive circuit, and is used for controlling on-off of the first NMOS transistor and the second NMOS transistor through the high-side drive circuit;

[0011] The threshold setting circuit is used for setting a threshold voltage, limiting a driving voltage threshold loaded by the charging control pin of the high-side drive chip, and filtering out a ripple lower than the threshold voltage, so as to avoid that the second NMOS transistor is caused to be mis-conducted or half-conducted due to voltage fluctuation of the positive charging terminal.

[0012] In an optional embodiment of the present application, the battery management system further comprises a third NMOS transistor;

[0013] A source of the third NMOS transistor is connected with a drain of the first NMOS transistor, a drain of the third NMOS transistor is connected with a drain of the second NMOS transistor, and a gate of the third NMOS transistor is connected with the charging control pin of the high-side drive chip;

[0014] The first NMOS transistor and the third NMOS transistor are mutually redundant, and are synchronously controlled by the high-side drive chip according to a control signal of the micro processing unit.

[0015] In an optional embodiment of the present application, the threshold setting circuit comprises a switch tube Q4, a resistor R7 and a resistor R6;

[0016] An input end of the switch tube Q4 is connected with one end of the resistor R7 and the discharging control pin of the high-side drive chip respectively, an output end is connected with the gate of the second NMOS transistor, and a control end is connected with the other end of the resistor R7 and one end of the resistor R6 respectively;

[0017] The other end of the resistor R6 is connected with a reference voltage pin of the high-side drive chip.

[0018] In an optional embodiment of the present application, the high-side drive circuit further comprises a discharge circuit, the threshold setting circuit is connected with the gate of the second NMOS transistor through the discharge circuit, and the discharge circuit is further connected with the source of the second NMOS transistor;

[0019] The discharge circuit is configured to

[0020] When the second NMOS transistor is turned off, a discharge path is formed between the gate and the source of the second NMOS transistor to accelerate the turn-off speed of the second NMOS transistor.

[0021] When the threshold setting circuit has no input drive signal, the gate-source voltage of the second NMOS transistor is clamped.

[0022] In an optional embodiment of the present application, the discharge circuit comprises a diode D1, a switch Q5, a resistor R2 and a resistor R3.

[0023] The anode of the diode D1 is connected with the output of the threshold setting circuit, the control end of the switch Q5 and one end of the resistor R3 respectively, and the cathode of the diode D1 is connected with the gate of the second NMOS transistor and the input end of the switch Q5 respectively.

[0024] The output end of the switch Q5 is connected with one end of the resistor R2.

[0025] The other end of the resistor R2 and the other end of the resistor R3 are connected with the source of the second NMOS transistor.

[0026] In an optional embodiment of the present application, the high-side drive circuit further comprises a resistor R5 for current limiting, and the resistor R5 is connected in series between the discharge circuit and the output of the threshold setting circuit.

[0027] In an optional embodiment of the present application, the high-side drive circuit further comprises a clamping circuit connected in series between the discharge control pin and the reference voltage pin of the high-side drive chip.

[0028] The clamping circuit is used for clamping the voltage between the discharge control pin and the reference voltage pin of the high-side drive chip, so as to avoid the damage of the high-side drive chip caused by the excessively low voltage of the reference voltage pin of the high-side drive chip.

[0029] In an optional embodiment of the present application, the clamping circuit comprises a zener diode DZ1 and a resistor R8, the cathode of the zener diode DZ1 is connected with the discharge control pin of the high-side drive chip, and the anode of the zener diode DZ1 is connected with the reference voltage pin of the high-side drive chip through the resistor R8.

[0030] In an optional embodiment of the present application, the high-side drive circuit further comprises a filter circuit composed of a resistor R4 and a capacitor C2;

[0031] One end of the resistor R4 is connected to the positive charging terminal, and the other end is connected to one end of the capacitor C2 and a reference voltage pin of the high-side drive chip, respectively;

[0032] The other end of the capacitor C2 is grounded.

[0033] In an optional embodiment of the present application, the battery management system further comprises a COM communication terminal and a COM communication circuit;

[0034] The COM communication circuit comprises a signal receiving circuit, a signal sending circuit, and a high-voltage protection circuit;

[0035] The input end of the signal receiving circuit is connected to the COM communication terminal, and the output end is connected to the data input pin of the micro processing unit;

[0036] The input end of the signal sending circuit is connected to the data output pin of the micro processing unit, and the output end is connected to the COM communication terminal, and the signal sending circuit is an open-drain output circuit or an open-collector output circuit;

[0037] The first end of the high-voltage protection circuit is connected to the COM communication terminal, and the second end is connected to the signal sending circuit;

[0038] The high-voltage protection circuit is configured to keep the switch tube connected to the COM communication terminal in the signal sending circuit off through its own hardware circuit when the access voltage of the COM communication terminal is greater than an overload threshold, so as to avoid damage to the switch tube connected to the COM communication terminal in the signal sending circuit due to overload.

[0039] In an optional embodiment of the present application, the signal sending circuit comprises a switch tube Q8, a resistor R16, and a resistor R17, wherein the switch tube Q8 is an NMOS tube or an NPN triode;

[0040] The input end of the switch tube Q8 serves as the output end of the signal sending circuit, and is connected to the first end of the high-voltage protection circuit and the COM communication terminal, respectively, and the output end of the switch tube Q8 is grounded, and the control end of the switch tube Q8 is connected to one end of the resistor R16, one end of the resistor R17, and the second end of the high-voltage protection circuit, respectively;

[0041] The other end of the resistor R16 is connected to the data output pin of the micro processing unit;

[0042] The other end of the resistor R17 is grounded.

[0043] In an optional embodiment of the present application, the signal sending circuit comprises a switch tube Q8, a resistor R16, a resistor R17, a resistor R14, a resistor R15 and a switch tube Q9, wherein the switch tube Q8 is an NMOS tube or an NPN transistor.

[0044] The input end of the switch tube Q8 is connected with the first end of the high-voltage protection circuit and the COM communication terminal as the output end of the signal sending circuit, the output end of the switch tube Q8 is grounded, and the control end of the switch tube Q8 is connected with one end of the resistor R16, one end of the resistor R17 and the second end of the high-voltage protection circuit.

[0045] The other end of the resistor R16 is connected with the output end of the switch tube Q9.

[0046] The input end of the switch tube is connected with one end of the resistor R15 and a power supply voltage, the control end is connected with the other end of the resistor R15 and one end of the resistor R14.

[0047] The other end of the resistor R14 is connected with the data output pin of the micro processing unit.

[0048] In an optional embodiment of the present application, the high-voltage protection circuit comprises a switch tube Q10, a voltage stabilizing diode DZ3, a resistor R18 and a resistor R19, and the switch tube Q10 is an NMOS tube or an NPN transistor.

[0049] The cathode of the voltage stabilizing diode is connected with the COM communication terminal and the input end of the switch tube Q8 as the first end of the high-voltage protection circuit, and the anode is connected with one end of the resistor R18.

[0050] The other end of the resistor R18 is connected with one end of the resistor R19 and the control end of the switch tube Q10.

[0051] The other end of the resistor R19 is grounded together with the output end of the switch tube Q10.

[0052] The input end of the switch tube Q10 is connected with the control end of the switch tube Q8 as the second end of the high-voltage protection circuit.

[0053] In an optional embodiment of the present application, the COM communication circuit further comprises a resistor R13, one end of the resistor R13 is connected with the COM communication terminal and the first end of the high-voltage protection circuit, and the other end is connected with the output end of the signal sending circuit and the input end of the signal receiving circuit.

[0054] In an optional embodiment of the present application, the COM communication circuit further comprises a diode D2.

[0055] The anode of the diode D2 is connected with the COM communication terminal, and the cathode is connected with the first end of the high-voltage protection circuit.

[0056] In an optional embodiment of the present application, the signal receiving circuit comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch tube Q6 and a switch tube Q7.

[0057] One end of the resistor R9 is connected with a power supply voltage, and the other end is connected with a data input pin of the micro processing unit and an input end of the switch tube Q6 respectively.

[0058] The output end of the switch tube Q6 is grounded, and the control end is connected with one end of the resistor R10 and an input end of the switch tube Q7 respectively.

[0059] The output end of the switch tube Q7 is grounded together with one end of the resistor R11, and the control end of the switch tube Q7 is connected with the other end of the resistor R11 and one end of the resistor R12 respectively.

[0060] The other end of the resistor R10 is connected with a power supply voltage.

[0061] The other end of the resistor R12 is connected with the COM communication terminal as an input end of the signal receiving circuit.

[0062] In an optional embodiment of the present application, the signal receiving circuit comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R20, a diode D3, a switch tube Q6 and a switch tube Q7.

[0063] One end of the resistor R9 is grounded, and the other end is connected with a data input pin of the micro processing unit and an output end of the switch tube Q6 respectively.

[0064] The input end of the switch tube Q6 is connected with a power supply voltage and one end of the resistor R10 respectively, and the control end of the switch tube Q6 is connected with the other end of the resistor R10 and one end of the resistor R20 respectively.

[0065] The other end of the resistor R20 is connected with the anode of the diode D3, and the cathode of the diode D3 is connected with the input end of the switch tube Q7.

[0066] The output end of the switch tube Q7 is grounded together with one end of the resistor R11, and the control end of the switch tube Q7 is connected with the other end of the resistor R11 and one end of the resistor R12 respectively.

[0067] The other end of the resistor R12 is connected with the COM communication terminal as an input terminal of the signal receiving circuit.

[0068] In an optional embodiment of the present application, the signal receiving circuit comprises a resistor R10, a resistor R11, a resistor R12, a resistor R21, a capacitor C3 and a switch tube Q7.

[0069] One end of the resistor R21 is connected with the capacitor C3 and a data input pin of the micro processing unit respectively, and the other end of the resistor R21 is connected with one end of the resistor R10 and an input terminal of the switch tube Q7 respectively.

[0070] The other end of the resistor R10 is connected with a power supply voltage.

[0071] The output terminal of the switch tube Q7, the other end of the capacitor C3 and one end of the resistor R11 are commonly grounded, and the control terminal of the switch tube Q7 is connected with the other end of the resistor R11 and one end of the resistor R12 respectively.

[0072] The other end of the resistor R12 is connected with the COM communication terminal as an input terminal of the signal receiving circuit.

[0073] To achieve the above object and other related objects, the present application further provides a battery pack, comprising:

[0074] a shell;

[0075] a battery pack installed in the shell; and

[0076] the above battery management system installed in the shell.

[0077] To achieve the above object and other related objects, the present application further provides an electric tool, comprising:

[0078] a tool body;

[0079] the above battery pack assembled on the tool body.

[0080] The battery management system of the present application sets the threshold voltage through the threshold setting circuit in the high-side driving circuit, limits the driving voltage threshold loaded by the charging control pin of the high-side driving chip, filters out the ripple lower than the threshold voltage, realizes the effectiveness of the driving signal of the discharge NMOS tube after it is greater than the threshold voltage, thereby avoiding the mis-conduction or semi-conduction of the discharge NMOS tube caused by the voltage fluctuation of the positive charging terminal, eliminating the mis-conduction caused by the signal line crosstalk, improving the anti-interference ability, and also avoiding the damage caused by the excessive heat generated by the excessive source-drain resistance when the discharge NMOS tube is turned on at a lower gate-source voltage, improving the safety, stability and anti-interference ability of the battery management system and the electric tool.

[0081] The battery management system of the present application can form a discharge path between the gate and the source of the discharging NMOS tube through the discharge circuit in the high-side drive circuit when the discharging NMOS tube is turned off, so as to accelerate the turn-off speed of the discharging NMOS tube, and clamp the gate-source voltage of the discharging NMOS tube when the threshold setting circuit has no input drive signal, so as to resist the conduction interference of the power line.

[0082] The battery management system of the present application can clamp the voltage between the discharging control pin and the reference voltage pin of the high-side drive chip through the clamping circuit in the high-side drive circuit, so as to avoid the damage of the high-side drive chip caused by the too low voltage of the reference voltage pin.

[0083] The COM communication circuit of the present application can keep the switch tube connected with the COM communication terminal in the signal sending circuit turned off through the high-voltage protection circuit itself when the access voltage of the COM communication terminal is greater than the overload threshold, so as to avoid the damage of the switch tube Q8 and the current limiting resistor R13 connected with the COM communication terminal in the signal sending circuit caused by overload, and improve the safety and stability of the battery management system and the electric tool.

[0084] The COM communication circuit of the present application can keep the switch tube connected with the COM communication terminal in the signal sending circuit turned off through the high-voltage protection circuit itself when the access voltage of the COM communication terminal is greater than the overload threshold, so as to avoid the damage of the switch tube Q8 and the current limiting resistor R13 connected with the COM communication terminal in the signal sending circuit caused by overload, and improve the safety and stability of the battery management system and the electric tool. BRIEF DESCRIPTION OF DRAWINGS

[0085] Figure 1 The architecture diagram of the battery management system of the present application is shown;

[0086] Figure 2 The circuit diagram of the high-side drive circuit of the present application is shown;

[0087] Figure 3 The function block diagram of the COM communication circuit of the present application is shown;

[0088] Figure 4 The circuit diagram of the COM communication circuit of the present application is shown;

[0089] Figure 5 An alternative circuit diagram of the signal receiving circuit of the present application is shown;

[0090] Figure 6 Another alternative circuit diagram of the signal receiving circuit of the present application is shown;

[0091] Figure 7 Another alternative circuit diagram of the signal sending circuit of the present application is shown.

[0092] Label Explanation

[0093] Micro-processing unit 10; high-side driving circuit 20; threshold setting circuit 21; bleeder circuit 22; MOS protection circuit 23; clamping circuit 24; analog front-end circuit 30; COM communication circuit 40; signal receiving circuit 41; signal sending circuit 42; high-voltage protection circuit 43; control panel circuit 50; Bluetooth transceiver circuit 60; fan control circuit 70; battery pack 80. DETAILED DESCRIPTION

[0094] The implementation of the present application is described below by specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied by other different embodiments, and various modifications or changes can be made to the details in the present specification without departing from the spirit of the present application.

[0095] Reference is made to Figures 1-7 It should be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concept of the present application, and the diagrams only show the components related to the present application, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be randomly changed in terms of shape, number and ratio, and the layout pattern of the components can be more complex.

[0096] The present application provides a battery pack, which includes a housing, a battery pack and a battery management system. The battery pack can be used as a power source of a power tool, and is assembled on a tool body of the power tool to supply power to the power tool. The power tool can be a grass trimmer, a brush cutter, a blower, a jigsaw, a sander, a lawn mower, a cleaning machine, a vacuum cleaner, a drill, an electric hammer, a mower, an electric wrench, a cleaning device, etc. It can be understood that the battery management system can also be applied to electric bicycles, household storage, base station UPS, etc. NMOS is used to realize the battery management system scheme of high-side control.

[0097] Reference is made to Figure 1 In the present embodiment, the battery management system includes a positive charging terminal CH+, a positive terminal P+, a negative terminal P- / CH-, an NMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a high-side driving circuit 20 and a micro-processing unit 10, wherein the NMOS tube Q1 is used as a first NMOS tube, the NMOS tube Q2 is used as a third NMOS tube, and the NMOS tube Q3 is used as a second NMOS tube.

[0098] In the present embodiment, for the convenience of description, in the following, the gate G of the NMOS transistor is defined as the control terminal, the drain D is defined as the input terminal, and the source S is defined as the output terminal; the gate G of the PMOS transistor is defined as the control terminal, the source S is defined as the input terminal, and the drain D is defined as the output terminal; the base B of the NPN transistor is defined as the control terminal, the collector C is defined as the input terminal, and the emitter E is defined as the output terminal; the base B of the PNP transistor is defined as the control terminal, the emitter E is defined as the input terminal, and the collector C is defined as the output terminal.

[0099] The output terminal of the NMOS transistor Q1 is connected to the positive electrode BAT+ of the battery pack 80, the input terminal of the NMOS transistor Q1 is connected to the output terminal of the NMOS transistor Q2, the input terminal of the NMOS transistor Q2 is connected to the input terminal of the NMOS transistor Q3, the output terminal of the NMOS transistor Q3 is connected to the positive charging terminal CH+, and the negative terminal P- is connected to the negative electrode BAT- of the battery pack 80; the high-side drive circuit 20 is connected to the control terminal of the NMOS transistor Q1, the control terminal of the NMOS transistor Q2, and the control terminal of the NMOS transistor Q3, and the high-side drive circuit 20 is also connected to the positive charging terminal CH+ of the battery pack 80; the micro-processing unit 10 is connected to the high-side drive circuit 20, and is used to control the on-off of the NMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q1 through the high-side drive circuit 20, so as to execute the charging control logic and the discharging control logic.

[0100] The NMOS transistor Q1 and the NMOS transistor Q2 are redundant to each other, and are synchronously controlled according to the control signal of the micro-processing unit 10 by the high-side drive module, that is, the NMOS transistor Q1 and the NMOS transistor Q2 are synchronously turned on or turned off. The NMOS transistor Q1 and the NMOS transistor Q2 are connected in series in order to meet the safety standards of the household charging battery system. If any one of the NMOS transistor Q1 and the NMOS transistor Q2 has a short-circuit or open-circuit fault, the system should be able to continue to operate safely or be automatically disconnected to prevent dangerous situations such as overheat and overcharge. By connecting the two NMOS transistors in series, the failure of a single NMOS transistor can be avoided, which leads to the failure of the entire charging circuit. The two NMOS transistors connected in series can share the current, reduce the current stress of a single NMOS transistor, and thus reduce the risk of overheating and failure. The series configuration can improve the reliability of the circuit, and ensure that even if one NMOS transistor fails, the other NMOS transistor can still control the current to prevent overcharge or overdischarge. It can be understood that in other embodiments, only the NMOS transistor Q1 or the NMOS transistor Q2 can be provided.

[0101] Please refer to Figure 1 and 2In the embodiment, the high-side drive circuit 20 includes a high-side drive chip U1 and a threshold setting circuit 21. The high-side drive chip U1 is, for example, a BQ76200 drive chip of TI. A charging control pin DSG of the high-side drive chip U1, i.e., a 12 pin, is connected with a gate of the NMOS Q1. A discharging control pin PACK of the high-side drive chip U1, i.e., an 11 pin, is connected with a gate of the NMOS Q3 through the threshold setting circuit 21. The threshold setting circuit 21 is used to set a threshold voltage, limit a drive voltage threshold loaded by the charging control pin DSG of the high-side drive chip U1, filter out a ripple lower than the threshold voltage, and realize that the drive signal of the NMOS Q3 is effective after being greater than the threshold voltage, thereby avoiding that the NMOS Q3 is mis-conducted or half-conducted due to voltage fluctuation of the positive charging terminal CH+, eliminating mis-conduction caused by signal line crosstalk, improving anti-interference capability, and avoiding damage of the NMOS Q3 due to excessive source-drain resistance and large heat when the NMOS Q3 is conducted at a lower gate-source voltage.

[0102] Please refer to Figure 2 In an embodiment, the threshold setting circuit 21 includes a switch tube Q4, a resistor R7, and a resistor R6. The switch tube Q4 is a PNP triode. An input end of the switch tube Q4 is connected with one end of the resistor R7 and the discharging control pin DSG of the high-side drive chip U1. An output end of the switch tube Q4 is connected with the gate of the NMOS Q3 through a diode D1 of a bleeder circuit 22 as an output end of the threshold setting circuit 21. Control ends of the switch tube Q4 are connected with the other end of the resistor R7 and one end of the resistor R6. The other end of the resistor R6 is connected with a reference voltage pin PACK of the high-side drive chip U1. In an initial state, the discharging control pin DSG of the high-side drive chip U1 has no output, the switch tube Q4 is off, and the second NMOS is off due to the existence of a pull-down resistor R1. When the discharging control pin DSG of the high-side drive chip U1 outputs a high level, the switch tube Q4 is on, the drive signal passes through the switch tube Q4, the resistor R5, and the diode D1 to drive the second NMOS, the second NMOS is on, and the switch tube Q5 is off. It can be understood that the switch tube Q4 can also be a PMOS tube.

[0103] As an example, when the resistor R7=47KΩ and the resistor R6=470KΩ, it is measured that the switch tube Q4 is in a near-saturation conduction state when the output voltage of the discharging control pin DSG of the high-side drive chip U1≥5.8V, and the switch tube Q4 is in a saturation conduction state when the output voltage of the discharging control pin DSG of the high-side drive chip U1≥6V. It can be known that the threshold setting circuit 21 can limit the drive voltage threshold loaded by the discharging control pin DSG of the high-side drive chip U1 on the switch tube Q4, filter out the ripple lower than the threshold voltage, and improve the anti-interference capability.

[0104] Please refer toFigure 2 In the embodiment, the high-side drive circuit 20 further comprises a discharge circuit 22, the threshold setting circuit 21 is connected with the gate of the NMOS Q3 through the discharge circuit 22, and the discharge circuit 22 is further connected with the source of the NMOS Q3; the discharge circuit 22 is configured to form a discharge path between the gate and the source of the NMOS Q3 when the NMOS Q3 is turned off, so as to accelerate the turn-off speed of the NMOS Q3, and clamp the gate-source voltage of the NMOS Q3 when the threshold setting circuit 21 has no input drive signal, so as to resist the conduction interference of the power line. It can be understood that in some embodiments, the discharge circuit 22 can also not be provided.

[0105] Please refer to Figure 2 In a specific embodiment, the discharge circuit 22 comprises a diode D1, a switch Q5, a resistor R2 and a resistor R3, and the switch Q5 is a PNP triode; the anode of the diode D1 is connected with the output of the threshold setting circuit 21, the control end of the switch Q5 and one end of the resistor R3 respectively, the cathode of the diode D1 is connected with the gate of the NMOS Q3 and the input end of the switch Q5 respectively; the output end of the switch Q5 is connected with one end of the resistor R2; the other end of the resistor R2 and the other end of the resistor R3 are connected with the source of the NMOS Q3. It can be understood that the switch Q5 can also be a PMOS.

[0106] Please refer to Figure 2 In the embodiment, the high-side drive circuit 20 further comprises a resistor R5 for current limiting, and the resistor R5 is connected in series between the discharge circuit 22 and the output of the threshold setting circuit 21, specifically, the resistor R5 is connected in series between the output of the switch Q4 and the anode of the diode D1. It should be noted that the turn-on speed of the switch Q3 can be adjusted by adjusting the resistance value of the resistor R5, and the turn-off speed of the switch Q3 can be adjusted by adjusting the resistance value of the resistor R2, so that different MOS types can be adapted more conveniently and the circuit can be adjusted quickly.

[0107] Please refer to Figure 2 In the embodiment, the high-side drive circuit 20 further comprises a clamping circuit 24, and the clamping circuit 24 is connected in series between the discharge control pin DSG and the reference voltage pin PACK of the high-side drive chip U1; the clamping circuit 24 is used for clamping the voltage between the discharge control pin DSG and the reference voltage pin PACK of the high-side drive chip U1, so as to avoid the damage of the high-side drive chip U1 caused by the too low voltage of the reference voltage pin PACK of the high-side drive chip U1.

[0108] Please refer to Figure 2In a specific embodiment, the clamping circuit 24 includes a zener diode DZ1 and a resistor R8, the cathode of the zener diode DZ1 is connected to the discharge control pin DSG of the high-side drive chip U1, and the anode of the zener diode DZ1 is connected to the reference voltage pin PACK of the high-side drive chip U1 through the resistor R8.

[0109] Referring to Figure 2 In the embodiment, the high-side drive circuit 20 further includes a filter circuit composed of a resistor R4 and a capacitor C2, which is used to provide a reference voltage for the high-side drive chip U1; one end of the resistor R4 is connected to the positive charging terminal CH+, and the other end is connected to one end of the capacitor C2 and the reference voltage pin PACK of the high-side drive chip U1, respectively; the other end of the capacitor C2 is grounded.

[0110] Referring to Figure 2 In the embodiment, the high-side drive circuit 20 further includes a MOS protection circuit 23 connected between the gate and the source of the NMOS tube Q3. Specifically, the MOS protection circuit 23 includes a capacitor C1, a zener diode DZ2 and a resistor R1; wherein the capacitor C1 is connected between the gate and the source of the NMOS tube Q3 as a bypass capacitor, which can increase the gate capacitance of the NMOS tube Q3, avoid the occurrence of jittering false opening when the positive charging terminal is short-circuited, and make the state of the second NMOS tube more stable; the anode of the zener diode DZ2 is connected to the source of the NMOS tube Q3, and the cathode is connected to the gate of the NMOS tube Q3, which can clamp the gate-source voltage of the NMOS tube Q3; the resistor R1 is connected between the gate and the source of the NMOS tube Q3, which plays a role of current limiting.

[0111] Referring to Figure 1 As shown in the figure, in the embodiment, the battery management system further includes a COM communication circuit and a COM communication terminal, one end of the COM communication circuit is connected to the micro-processing unit 10, and the other end is connected to the COM communication terminal, the micro-processing unit 10 can interact with the charger and the power tool through the COM communication circuit and the COM communication terminal, upload the battery pack data to the charger and the power tool, and realize the linkage control between cross components.

[0112] Referring to Figure 3In the embodiment, the COM communication circuit 40 includes a signal receiving circuit 41, a signal sending circuit 42, and a high-voltage protection circuit 43. The input end of the signal receiving circuit 41 is connected with the COM communication terminal, and the output end thereof is connected with the data input pin of the micro processing unit 10 as a receiving end RX. The input end of the signal sending circuit 42 is connected with the data output pin of the micro processing unit 10, and the output end thereof is connected with the COM communication terminal. The signal sending circuit 42 is an open-drain output circuit or an open-collector output circuit. The first end of the high-voltage protection circuit 43 is connected with the COM communication terminal, and the second end thereof is connected with the signal sending circuit 42. The high-voltage protection circuit 43 is configured to keep the switch tube Q8 connected with the COM communication terminal in the signal sending circuit 42 off when the access voltage of the COM communication terminal is greater than an overload threshold, so as to avoid the switch tube Q8 connected with the COM communication terminal in the signal sending circuit 42 from being damaged due to overload.

[0113] Please refer to Figure 4 In a specific embodiment, the signal receiving circuit 41 includes a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch tube Q6, and a switch tube Q7. The switch tube Q6 and the switch tube Q7 are NPN triodes. One end of the resistor R9 is connected with a 3.3V power supply voltage, and the other end thereof is connected with the data input pin of the micro processing unit 10 and the input end of the switch tube Q6 as a receiving end RX. The output end of the switch tube Q6 is grounded, and the control end thereof is connected with one end of the resistor R10 and the input end of the switch tube Q7. The output end of the switch tube Q7 is connected with one end of the resistor R11 and grounded, and the control end of the switch tube Q7 is connected with the other end of the resistor R11 and one end of the resistor R12. The other end of the resistor R10 is connected with a 3.3V power supply voltage. The other end of the resistor R12 is connected with the COM communication terminal through a node M as the input end of the signal receiving circuit 41. It can be understood that, in other embodiments, the switch tube Q6 and the switch tube Q7 can also be NMOS tubes.

[0114] Figure 4 The sending principle of the signal receiving circuit 41 is as follows:

[0115] When the COM communication terminal is high, the switch tube Q7 is turned on, the switch tube Q6 is turned off, and the data input pin of the micro processing unit 10 is pulled up to the 3.3V power supply voltage by the resistor R9, which is high. Conversely, when the COM communication terminal is low, the switch tube Q7 is turned off, the switch tube Q6 is turned on, and the data input pin of the micro processing unit 10 is pulled down to low by the switch tube Q6.

[0116] Figure 5 An alternative circuit of the signal receiving circuit 41 is given. Please refer to Figure 5The signal receiving circuit 41 comprises a resistor R10, a resistor R11, a resistor R12, a resistor R21, a capacitor C3 and a switch tube Q7, wherein the switch tube Q7 is an NMOS tube. One end of the resistor R21 is connected to a receiving end RX and a data input pin of the micro processing unit 10, and the other end of the resistor R21 is connected to one end of the resistor R10 and an input end of the switch tube Q7; the other end of the resistor R10 is connected to a 5V power supply; an output end of the switch tube Q7, the other end of the capacitor C3 and one end of the resistor R11 are grounded; a control end of the switch tube Q7 is connected to the other end of the resistor R11 and one end of the resistor R12; the other end of the resistor R12 is connected to the COM communication terminal through a node M. It can be understood that in other embodiments, the switch tube Q7 can also be an NPN transistor.

[0117] Figure 5 The sending principle of the signal receiving circuit 41 is as follows:

[0118] When the COM communication terminal is at a high level, the switch tube Q7 is turned on, and the data input pin of the micro processing unit 10 is pulled down to the ground by the switch tube Q7 and is at a low level; on the contrary, when the COM communication terminal is at a low level, the switch tube Q7 is turned off, and the data input pin of the micro processing unit 10 is pulled up to the 5V power supply by the resistor R10 and is at a high level.

[0119] Figure 6 Another alternative circuit of the signal receiving circuit 41 is given. Please refer to Figure 6 The signal receiving circuit 41 comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R20, a diode D3, a switch tube Q6 and a switch tube Q7, wherein the switch tube Q6 is a PNP transistor, and the switch tube Q7 is an NPN transistor; one end of the resistor R9 is grounded, and the other end of the resistor R9 is connected to a data input pin of the micro processing unit 10 and an output end of the switch tube Q6 as a receiving end RX; an input end of the switch tube Q6 is connected to a 3.3V power supply and one end of the resistor R10; a control end of the switch tube Q6 is connected to the other end of the resistor R10 and one end of the resistor R20; the other end of the resistor R20 is connected to an anode of the diode D3, and a cathode of the diode D3 is connected to an input end of the switch tube Q7; an output end of the switch tube Q7 and one end of the resistor R11 are grounded, and a control end of the switch tube Q7 is connected to the other end of the resistor R11 and one end of the resistor R12; the other end of the resistor R12 is connected to the COM communication terminal through a node M as an input end of the signal receiving circuit 41. It can be understood that in other embodiments, the switch tube Q6 can also be a PMOS tube, and the switch tube Q7 can also be an NMOS tube.

[0120] Figure 6The sending principle of the signal receiving circuit 41 is as follows:

[0121] When the COM communication terminal is high, the switch tube Q7 is turned on, the switch tube Q6 is turned on, the data input pin of the micro processing unit 10 is connected with the 3.3V power supply voltage and is high; on the contrary, when the COM communication terminal is low, the switch tube Q7 is turned off, the switch tube Q6 is turned off, the data input pin of the micro processing unit 10 is pulled down to the ground by the resistor R9 and is low.

[0122] Please refer to Figure 4 In a specific embodiment, the above-mentioned signal sending circuit 42 includes the switch tube Q8, the resistor R16, the resistor R17, the resistor R14, the resistor R15 and the switch tube Q9, wherein the switch tube Q8 is an NPN triode; the input end of the switch tube Q8 is connected with the first end of the high voltage protection circuit 43 and the COM communication terminal through the node M as the output end of the signal sending circuit 42, the output end of the switch tube Q8 is grounded, the control end of the switch tube Q8 is connected with one end of the resistor R16 and one end of the resistor R17 at the node N, the node N is connected with the second end of the high voltage protection circuit 43; the other end of the resistor R16 is connected with the output end of the switch tube Q9; the input end of the switch tube is connected with one end of the resistor R15 and the 3.3V power supply voltage, the control end is connected with the other end of the resistor R15 and one end of the resistor R14; the other end of the resistor R14 is connected with the data output pin of the micro processing unit 10. It can be understood that the switch tube Q8 can also be an NMOS tube.

[0123] Figure 4 The sending principle of the signal sending circuit 42 is as follows:

[0124] When the data output pin of the micro processing unit 10 is high, the switch tube Q9 is turned off, the switch tube Q8 is turned off, the COM communication terminal is pulled high by the pull-up resistor on the external other transceiver circuit of the electric tool, the charger and the like and is high; when the data output pin of the micro processing unit 10 is low, the switch tube Q9 is turned on, the switch tube Q8 is turned on, the COM communication terminal is pulled low by the switch tube Q8 and outputs low.

[0125] Figure 7 An alternative circuit of the signal sending circuit 42 is given. Please refer to Figure 7The signal sending circuit 42 comprises a switch tube Q8, a resistor R16 and a resistor R17, wherein the switch tube Q8 is an NMOS tube; an input end of the switch tube Q8 is connected with the output end of the signal sending circuit 42, and is connected with a first end of the high voltage protection circuit 43 and a COM communication terminal through a node M respectively, an output end of the switch tube Q8 is grounded, and a control end of the switch tube Q8 is connected with one end of the resistor R16 and one end of the resistor R17 at a node N, the node N is connected with a second end of the high voltage protection circuit 43; the other end of the resistor R16 is connected with a data output pin of the micro processing unit 10; and the other end of the resistor R17 is grounded. It can be understood that the switch tube Q8 can also be an NPN triode.

[0126] Figure 7 The sending principle of the signal sending circuit 42 is as follows:

[0127] When the data output pin TX of the micro processing unit 10 is high, the switch tube Q8 is turned on, the COM communication terminal is pulled low by the switch tube Q8, and a low level is output; when the data output pin TX of the micro processing unit 10 is low, the switch tube Q8 is turned off, and the COM communication terminal is pulled high to high level by a pull-up resistor on other transceiving circuits of the electric tool, the charger and the like.

[0128] Please refer to Figure 4 In the embodiment, the COM communication circuit 40 further comprises a resistor R13 for current limiting, one end of the resistor R13 is connected with the COM communication terminal and the first end of the high voltage protection circuit 43 through the node M respectively, and the other end of the resistor R13 is connected with the output end of the signal sending circuit 42 and the input end of the signal receiving circuit 41 respectively.

[0129] Please refer to Figure 4 In the embodiment, the COM communication circuit 40 further comprises a diode D2 for reverse voltage protection; an anode of the diode D2 is connected with the COM communication terminal, and a cathode of the diode D2 is connected with the first end of the high voltage protection circuit 43. By setting the diode D2, when the COM communication terminal is connected with a voltage lower than the ground, the diode D2 is in a cut-off state, so that the collector and the emitter of the switch tube Q8 and the base and the emitter of the switch tube Q10 in the high voltage protection circuit 43 are not affected by the reverse voltage. It can be understood that when the battery pack and the electric tool or the charger are grounded, the diode D2 can also not be set.

[0130] Please refer to Figure 4In the embodiment, the high-voltage protection circuit 43 includes a switch tube Q10, a voltage stabilizing diode DZ3, a resistor R18, and a resistor R19. The switch tube Q10 is an NPN triode. The cathode of the voltage stabilizing diode DZ3 is connected to the COM communication terminal and the input end of the switch tube Q8 as the first end of the high-voltage protection circuit 43, and the anode is connected to one end of the resistor R18. The other end of the resistor R18 is connected to the other end of the resistor R19 and the control end of the switch tube Q10. The other end of the resistor R19 is connected to the output end of the switch tube Q10 and the ground. The input end of the switch tube Q10 is connected to the control end of the switch tube Q8 through a node N as the second end of the high-voltage protection circuit 43. The node N is the connection point of the resistor R16, the resistor R17, and the control end of the switch tube Q8. Specifically, the cathode of the voltage stabilizing diode DZ3 is connected to the input end of the switch tube Q8 through the resistor R13 and a node M, and is connected to the COM communication terminal through the reverse diode D2. It can be understood that the switch tube Q10 can also be an NMOS tube.

[0131] The working principle of the high-voltage protection circuit 43 is as follows:

[0132] When the voltage of the COM communication terminal is greater than the overload threshold, the voltage stabilizing diode DZ3 is reversely conducted, the switch tube Q10 is kept on through the voltage division circuit of the resistor R18 and the resistor R19, and the switch tube Q8 is forcibly turned off, thereby protecting the switch tube Q8 and the resistor R13.

[0133] As an example, when the voltage of the COM communication terminal is greater than 19.47V, the voltage stabilizing diode DZ3 is reversely conducted, and the switch tube Q10 is turned on, thereby forcibly turning off the switch tube Q8. For example, when the voltage of the COM communication terminal is 20V, the voltage between the resistor R18 and the voltage stabilizing diode DZ3 is 1.3V, the voltage of the resistor R18 and the resistor R19 is divided, the Vbe voltage of the switch tube Q10 is greater than 0.7V, the switch tube Q10 is saturated and turned on, thereby pulling down the Vbe voltage of the switch tube Q8 to be less than the turn-on voltage, thereby protecting the switch tube Q8 and the resistor R13.

[0134] It should be noted that the signal receiving circuit 41 of the present application is not limited to Figures 4-6 the circuit structure shown in the signal sending circuit 42 is not limited to Figure 4 and Figure 7 the circuit structure shown in the signal sending circuit 42 is not limited to

[0135] Please refer to Figure 1As shown, the battery management system further comprises an analog front-end (AFE) circuit 30, a control panel circuit 50, a Bluetooth transceiver circuit 60, a fan control circuit 70, a sampling resistor RS and the like, wherein the micro-processing unit 10 is connected with the analog front-end circuit 30, the control panel circuit 50, the Bluetooth transceiver circuit 60, the fan control circuit 70 and the like respectively.

[0136] In summary, the battery management system of the present application sets the threshold voltage through the threshold setting circuit 21 in the high-side drive circuit 20, limits the drive voltage threshold loaded by the charging control pin DSG of the high-side drive chip U1, filters out the ripple below the threshold voltage, and enables the driving signal of the NMOS tube Q3 to be greater than the threshold voltage, thereby avoiding the mis-conduction or half-conduction of the NMOS tube Q3 caused by the voltage fluctuation of the positive charging terminal, eliminating the mis-conduction caused by signal line crosstalk, improving the anti-interference ability, and also avoiding the damage caused by the excessive heat generated by the excessive source-drain resistance when the NMOS tube Q3 is turned on at a lower gate-source voltage, thereby improving the safety, stability and anti-interference ability of the battery management system and the electric tool.

[0137] The battery management system of the present application can form a discharge path between the gate and the source of the NMOS tube Q3 when the NMOS tube Q3 is turned off through the discharge circuit 22 in the high-side drive circuit 20, so as to accelerate the turn-off speed of the second NMOS tube, and clamp the gate-source voltage of the NMOS tube Q3 when there is no input driving signal of the threshold setting circuit 21, so as to resist the conduction interference of the power line.

[0138] The battery management system of the present application can clamp the voltage between the discharge control pin and the reference voltage pin of the high-side drive chip U1 through the clamping circuit 24 in the high-side drive circuit 20, so as to avoid the damage of the high-side drive chip U1 caused by the excessively low voltage of the reference voltage pin of the high-side drive chip U1.

[0139] The COM communication circuit 40 of the present application can keep the switch tube connected with the COM communication terminal in the signal sending circuit 42 turned off through the high-voltage protection circuit 43 itself when the access voltage of the COM communication terminal is greater than the overload threshold, thereby avoiding the damage of the switch tube Q8 and the current limiting resistor R13 connected with the COM communication terminal in the signal sending circuit 42 caused by overload, and improving the safety and stability of the battery management system and the electric tool.

[0140] The COM communication circuit 40 of the present application, by setting the diode D2 for reverse voltage protection between the current limiting resistor R8 and the COM communication terminal, can make the diode D2 in the cut-off state when the COM communication terminal is connected to the voltage lower than the ground, so that the collector and emitter of the switch tube Q8 and the base and emitter of the switch tube Q10 in the high voltage protection circuit 43 are not affected by the reverse voltage, further improving the safety and stability of the battery management system and the electric tool.

[0141] The above description of the illustrated embodiments of the application (including what is in the Abstract) is not intended to be exhaustive or to limit the application to the precise forms disclosed. While specific embodiments of, and examples for, the application are described herein for illustrative purposes, various equivalent modifications are possible within the spirit and scope of the application, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications can be made to the above described embodiments of the application in light of the detailed description of the application

[0142] The systems and methods have been described generally herein to facilitate an understanding of the details of the application. Moreover, various specific details have been given for providing an overall understanding of the embodiments of the application. One skilled in the relevant art will recognize and appreciate that the embodiments of the application can be practiced without one or more of the specific details, or with other

[0143] Thus, although the application has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosure, and it will be appreciated that in some instances some features of the application can be employed without a corresponding use of other features, without departing from the scope of the application as set forth in the appended claims. Therefore, many modifications can be made to the application without departing from the spirit and scope of the application as set forth in the appended claims. The application is not limited to the described embodiments for carrying out the application and the application is intended to cover any and all adaptations or variations of the various embodiments of the application. Therefore, it is manifestly intended that this application be limited only by the following claims and equivalents thereof.

Claims

1. A battery management system, characterized by, The application relates to a battery management system. The battery management system comprises a positive charging terminal, a negative terminal, a first NMOS tube, a second NMOS tube, a high-side drive circuit and a micro processing unit. The source of the first NMOS tube is connected with a positive electrode of a battery of a battery pack, the drain of the first NMOS tube is connected with the drain of the second NMOS tube, the source of the second NMOS tube is connected with the positive charging terminal, the negative terminal is connected with a negative electrode of the battery of the battery pack. The high-side drive circuit comprises a high-side drive chip and a threshold setting circuit, the charging control pin of the high-side drive chip is connected with the gate of the first NMOS tube, the discharging control pin of the high-side drive chip is connected with the gate of the second NMOS tube through the threshold setting circuit. The micro processing unit is connected with the high-side drive circuit, and is used for controlling the on-off of the first NMOS tube and the second NMOS tube through the high-side drive circuit. The threshold setting circuit is used for setting a threshold voltage, limiting the drive voltage threshold loaded by the charging control pin of the high-side drive chip, filtering out the ripples lower than the threshold voltage, so as to avoid the second NMOS tube from being mis-conducted or half-conducted due to the voltage fluctuation of the positive charging terminal.

2. The battery management system of claim 1, wherein, The battery management system further comprises a third NMOS tube. The source of the third NMOS tube is connected with the drain of the first NMOS tube, the drain of the third NMOS tube is connected with the drain of the second NMOS tube, and the gate of the third NMOS tube is connected with the charging control pin of the high-side drive chip. The first NMOS tube and the third NMOS tube are mutually redundant, and are synchronously controlled by the high-side drive chip according to the control signal of the micro processing unit.

3. The battery management system of claim 1, wherein, The threshold setting circuit comprises a switch tube Q4, a resistor R7 and a resistor R6. The input ends of the switch tube Q4 are respectively connected with one end of the resistor R7 and the discharging control pin of the high-side drive chip, the output end is connected with the gate of the second NMOS tube, and the control end is respectively connected with the other end of the resistor R7 and one end of the resistor R6. The other end of the resistor R6 is connected with the reference voltage pin of the high-side drive chip.

4. The battery management system of claim 1, wherein, The high-side drive circuit further comprises a bleeder circuit, the threshold setting circuit is connected with the gate of the second NMOS tube through the bleeder circuit, and the bleeder circuit is further connected with the source of the second NMOS tube. The bleeder circuit is configured to form a bleeder path between the gate and the source of the second NMOS tube when the second NMOS tube is turned off, so as to accelerate the turn-off speed of the second NMOS tube. The gate-source voltage of the second NMOS tube is clamped when there is no input drive signal in the threshold setting circuit.

5. The battery management system of claim 4, wherein, The bleeder circuit comprises a diode D1, a switch tube Q5, a resistor R2 and a resistor R3. The anode of the diode D1 is respectively connected with the output end of the threshold setting circuit, the control end of the switch tube Q5 and one end of the resistor R3, and the cathode of the diode D1 is respectively connected with the gate of the second NMOS tube Q3 and the input end of the switch tube Q5. An output terminal of the switch tube Q5 is connected with one end of the resistor R2; The other end of the resistor R2 and the other end of the resistor R3 are connected with the source of the second NMOS tube.

6. The battery management system of claim 4, wherein, The high-side drive circuit further comprises a resistor R5 for current limiting, which is connected in series between the discharge circuit and the output terminal of the threshold setting circuit.

7. The battery management system of claim 1, wherein, The high-side drive circuit further comprises a clamping circuit connected in series between the discharge control pin and the reference voltage pin of the high-side drive chip; The clamping circuit is used for clamping the voltage between the discharge control pin and the reference voltage pin of the high-side drive chip, so as to avoid the damage of the high-side drive chip caused by the too low voltage of the reference voltage pin.

8. The battery management system of claim 7, wherein, The clamping circuit comprises a zener diode DZ1 and a resistor R8, the cathode of the zener diode DZ1 is connected with the discharge control pin of the high-side drive chip, and the anode of the zener diode DZ1 is connected with the reference voltage pin of the high-side drive chip through the resistor R8.

9. The battery management system of claim 1, wherein, The high-side drive circuit further comprises a filter circuit composed of a resistor R4 and a capacitor C2; One end of the resistor R4 is connected with the positive charging terminal, and the other end is connected with one end of the capacitor C2 and the reference voltage pin of the high-side drive chip respectively; The other end of the capacitor C2 is grounded.

10. The battery management system of claim 1, wherein, Further comprising a COM communication terminal and a COM communication circuit; The COM communication circuit comprises a signal receiving circuit, a signal sending circuit and a high-voltage protection circuit; The input terminal of the signal receiving circuit is connected with the COM communication terminal, and the output terminal is connected with the data input pin of the micro processing unit; The input terminal of the signal sending circuit is connected with the data output pin of the micro processing unit, and the output terminal is connected with the COM communication terminal, and the signal sending circuit is an open-drain output circuit or an open-collector output circuit; The first end of the high-voltage protection circuit is connected with the COM communication terminal, and the second end is connected with the signal sending circuit; The high-voltage protection circuit is configured to keep the switch tube connected with the COM communication terminal in the signal sending circuit off through its own hardware circuit when the access voltage of the COM communication terminal is greater than the overload threshold, so as to avoid the damage of the switch tube connected with the COM communication terminal in the signal sending circuit caused by overload.

11. The battery management system of claim 10, wherein, The signal sending circuit comprises a switch tube Q8, a resistor R16 and a resistor R17, wherein the switch tube Q8 is an NMOS tube or an NPN transistor; The input terminal of the switch tube Q8 is used as the output terminal of the signal sending circuit, and is connected with the first end of the high-voltage protection circuit and the COM communication terminal respectively, the output terminal of the switch tube Q8 is grounded, and the control terminal of the switch tube Q8 is connected with one end of the resistor R16, one end of the resistor R17 and the second end of the high-voltage protection circuit respectively; The other end of the resistor R16 is connected with the data output pin of the micro processing unit; The other end of the resistor R17 is grounded.

12. The battery management system of claim 10, wherein, The signal sending circuit comprises a switch tube Q8, a resistor R16, a resistor R17, a resistor R14, a resistor R15 and a switch tube Q9, wherein the switch tube Q8 is an NMOS tube or an NPN transistor; The input end of the switch tube Q8 is connected with the first end of the high voltage protection circuit and the COM communication terminal as the output end of the signal sending circuit, the output end of the switch tube Q8 is grounded, and the control end of the switch tube Q8 is connected with one end of the resistor R16, one end of the resistor R17 and the second end of the high voltage protection circuit; The other end of the resistor R16 is connected with the output end of the switch tube Q9; The input end of the switch tube is connected with one end of the resistor R15 and a power supply voltage, and the control end of the switch tube is connected with the other end of the resistor R15 and one end of the resistor R14; The other end of the resistor R14 is connected with the data output pin of the micro processing unit.

13. The battery management system of claim 11 or 12, wherein, The high voltage protection circuit comprises a switch tube Q10, a voltage stabilizing diode DZ3, a resistor R18 and a resistor R19, and the switch tube Q10 is an NMOS tube or an NPN transistor; The cathode of the voltage stabilizing diode is connected with the COM communication terminal and the input end of the switch tube Q8 as the first end of the high voltage protection circuit, and the anode of the voltage stabilizing diode is connected with one end of the resistor R18; The other end of the resistor R18 is connected with one end of the resistor R19 and the control end of the switch tube Q10; The other end of the resistor R19 is grounded together with the output end of the switch tube Q10; The input end of the switch tube Q10 is connected with the control end of the switch tube Q8 as the second end of the high voltage protection circuit.

14. The battery management system of claim 10, wherein, The COM communication circuit further comprises a resistor R13, one end of the resistor R13 is connected with the COM communication terminal and the first end of the high voltage protection circuit, and the other end of the resistor R13 is connected with the output end of the signal sending circuit and the input end of the signal receiving circuit.

15. The battery management system of claim 14, wherein, The COM communication circuit further comprises a diode D2; The anode of the diode D2 is connected with the COM communication terminal, and the cathode of the diode D2 is connected with the first end of the high voltage protection circuit.

16. The battery management system of claim 10, wherein, The signal receiving circuit comprises a resistor R9, a resistor R10, a resistor R11, a resistor R12, a switch tube Q6 and a switch tube Q7; One end of the resistor R9 is connected with a power supply voltage, and the other end of the resistor R9 is connected with the data input pin of the micro processing unit and the input end of the switch tube Q6; The output end of the switch tube Q6 is grounded, and the control end of the switch tube Q6 is connected with one end of the resistor R10 and the input end of the switch tube Q7; The output end of the switch tube Q7 is grounded together with one end of the resistor R11, and the control end of the switch tube Q7 is connected with the other end of the resistor R11 and one end of the resistor R12; The other end of the resistor R10 is connected with a power supply voltage; The other end of the resistor R12 is connected with the COM communication terminal as the input end of the signal receiving circuit.

17. The battery management system of claim 10, wherein, The signal receiving circuit comprises resistors R9, R10, R11, R12, R20, a diode D3, a switch Q6 and a switch Q7. One end of the resistor R9 is grounded, and the other end is connected with a data input pin of the micro processing unit and an output terminal of the switch Q6 respectively. An input terminal of the switch Q6 is connected with a power supply voltage and one end of the resistor R10 respectively, and a control terminal of the switch Q6 is connected with the other end of the resistor R10 and one end of the resistor R20 respectively. The other end of the resistor R20 is connected with an anode of the diode D3, and a cathode of the diode D3 is connected with an input terminal of the switch Q7. An output terminal of the switch Q7 is grounded together with one end of the resistor R11, and a control terminal of the switch Q7 is connected with the other end of the resistor R11 and one end of the resistor R12 respectively. The other end of the resistor R12 is connected with the COM communication terminal as an input terminal of the signal receiving circuit.

18. The battery management system of claim 10, wherein, The signal receiving circuit comprises resistors R10, R11, R12, R21, a capacitor C3 and a switch Q7. One end of the resistor R21 is connected with the capacitor C3 and a data input pin of the micro processing unit respectively, and the other end of the resistor R21 is connected with one end of the resistor R10 and an input terminal of the switch Q7 respectively. The other end of the resistor R10 is connected with a power supply voltage. An output terminal of the switch Q7, the other end of the capacitor C3 and one end of the resistor R11 are grounded together, and a control terminal of the switch Q7 is connected with the other end of the resistor R11 and one end of the resistor R12 respectively. The other end of the resistor R12 is connected with the COM communication terminal as an input terminal of the signal receiving circuit.

19. A battery pack, characterized by It comprises: a housing; a battery pack installed in the housing; and a battery management system as claimed in claim 1 installed in the housing.

20. A power tool, comprising: a tool body; a battery pack as claimed in claim 19 assembled on the tool body. ​

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