Active short-circuit protection circuit, motor and automobile
By combining hardware logic gates and buffers, the problem of slow response speed when the motor control system fails is solved, enabling rapid entry into a safe state, improving the response speed and reliability of the motor control system, and meeting the functional safety requirements of new energy vehicles.
Patent Information
- Application Number
- CN202520063188.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-01-10
AI Technical Summary
In existing technologies, motor control systems have slow response times when faults occur and cannot quickly enter a safe state of active short circuit, especially when the MCU fails, which poses a safety hazard.
By employing a combination of hardware logic gates and buffers, a fault status confirmation module is used to achieve safe mode switching of the motor, thereby improving response speed and reliability.
It enables rapid entry into a safe state when the motor control system fails, improving response speed and reliability, and meeting the functional safety requirements of new energy vehicles.
Smart Images
Figure CN223858829U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of new energy vehicles, and in particular to an active short-circuit protection circuit, a motor and a vehicle. BACKGROUND
[0002] The motor is the main power source of the electric vehicle. When the motor control system fails, it needs to enter a safe state to ensure that the vehicle is controlled and does not cause harm to the driver and passengers. When the motor controller fails in hardware or software, the motor output is abnormal, and it is very dangerous whether it is output braking torque or driving torque. In the related art, software is used for logical judgment, which has a certain delay in response speed due to the influence of the operation speed of the MCU. In addition, when the MCU fails, the motor will not be able to enter the active short-circuit safe state.
[0003] It should be noted that the statements herein only provide background information related to the present application and do not necessarily constitute the prior art. CONTENT OF THE UTILITY MODEL
[0004] In view of the above problems, the present application proposes an active short-circuit protection circuit, a motor and a vehicle which overcome the above problems or at least partially solve the above problems.
[0005] The embodiments of the present application adopt the following technical solutions:
[0006] In a first aspect, the embodiments of the present application provide an active short-circuit protection circuit, which comprises a motor controller, a lower bridge arm fault state confirmation module and an upper bridge arm fault state confirmation module. The motor controller is configured to confirm at least one fault module in the lower bridge arm fault state confirmation module and the upper bridge arm fault state confirmation module according to the triggered fault type, and control a motor connected with the motor controller to enter a corresponding safe mode according to the fault module.
[0007] Preferably, the lower bridge arm fault state confirmation module comprises a first OR logic gate, a second OR logic gate, a third OR logic gate, a first NAND logic gate and a second NAND logic gate. The outputs of the first OR logic gate and the second OR logic gate are connected with the input of the first NAND logic gate. The output of the first NAND logic gate is connected with the second input of the third OR logic gate. The output of the third OR logic gate is connected with the first input of the second NAND logic gate. The first inputs of the first OR logic gate, the second OR logic gate and the third OR logic gate are connected with a first fault pin, a second fault pin and a third fault pin respectively. The second inputs of the first OR logic gate and the second OR logic gate are connected with a fourth fault pin.
[0008] Preferably, the upper arm fault state confirmation module comprises a fourth OR logic gate, a fifth OR logic gate, a first AND logic gate, and a second AND logic gate, the outputs of the fourth OR logic gate and the fifth OR logic gate are connected with the input of the first AND logic gate, the output of the first AND logic gate is connected with the second input of the second AND logic gate and the second input of the second NAND logic gate respectively, the first inputs of the fourth OR logic gate and the fifth OR logic gate are connected with a fifth fault pin and a sixth fault pin respectively, the second inputs of the fourth OR logic gate and the fifth OR logic gate are connected with the fourth fault pin, and the first input of the second AND logic gate is connected with the output of the first NAND logic gate.
[0009] Preferably, the protection circuit further comprises a first buffer and a second buffer, the outputs of the second NAND logic gate and the second AND logic gate are connected with the corresponding pins of the first buffer and the second buffer respectively. The protection circuit further comprises a flip-flop, the outputs of the second NAND logic gate and the second AND logic gate are connected with the corresponding pins of the flip-flop respectively.
[0010] Preferably, the protection circuit further comprises a third AND logic gate, a third NAND logic gate, and a third buffer, the two inputs of the third AND logic gate are connected with the corresponding pins of the flip-flop respectively, the output of the third AND logic gate is connected with the first input of the third NAND logic gate, and the output of the third NAND logic gate is connected with the corresponding pin of the third buffer.
[0011] In a second aspect, the embodiments of the present application further provide an electric machine comprising the protection circuit according to any one of the first aspect.
[0012] In a third aspect, the embodiments of the present application further provide an electronic device comprising the electric machine according to the second aspect.
[0013] The above at least one technical scheme adopted by the embodiments of the present application can achieve the following beneficial effects:
[0014] The present application uses the combination of hardware logic gates and buffers, does not rely on the control of software, sets the switching dead zone in the switching process, realizes the control of fault logic, and improves the response speed.
[0015] The above description of the technical scheme of the present application is only a summary of the technical scheme of the present application, in order to enable the technical means of the present application to be more clearly understood, and to be implemented according to the content of the specification, and in order to enable the above and other purposes, features and advantages of the present application to be more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS
[0016] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0017] Figure 1 This is a block diagram of the active short-circuit protection circuit in the embodiments of this application;
[0018] Figure 2 This is a circuit diagram of the active short-circuit protection circuit in an embodiment of this application;
[0019] Figure 3 This is a schematic diagram of the active short-circuit protection method in the embodiments of this application. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0021] The technical terms used in this application are as follows:
[0022] The concept of this application is to address the current situation where the application software-based active short circuit implementation suffers from large delays and low efficiency. The proposed solution is to design an automated and universally applicable active short circuit protection circuit that uses simple hardware logic gates to achieve the active short circuit state, thereby improving response speed and reliability.
[0023] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.
[0024] This application provides an active short-circuit protection circuit, such as... Figure 1 The diagram shows a block diagram of an active short-circuit protection circuit in an embodiment of this application. The protection circuit includes a motor controller 110, a lower arm fault status confirmation module 120, and an upper arm fault status confirmation module 130. The motor controller includes a controller fault detection module. The motor controller is used to confirm at least one fault module among the lower arm and upper arm fault status confirmation modules based on the triggered fault type, and to control the motor 140 connected to the motor controller to enter the corresponding safety mode based on the fault module.
[0025] like Figure 3As shown, the fault types include, upper bridge arm open circuit and fault of the power module, upper bridge arm under voltage fault of the power module, lower bridge arm open circuit and fault of the power module, lower bridge arm under voltage fault of the power module, MCU fault and over voltage fault. When the upper and lower bridge arm related faults occur, it is judged whether to enter the active short circuit safety mode according to the vehicle speed at the fault time, if the speed is in the mode needing to enter the active short circuit, the three-phase short circuit state of the lower bridge arm is entered preferentially, if the power module of the lower bridge arm appears fault, the three-phase active short circuit state of the upper bridge arm is automatically switched to, in the process of switching the upper and lower bridge arms, a dead zone is added to prevent the shoot-through of the upper and lower bridge arms. If the upper and lower bridge arms are both in the fault state, the six-phase open circuit state is entered.
[0026] It can be understood that the fault processing of the active protection circuit meets the functional safety requirements of the new energy vehicle at the fault time of the motor driver, does not need software participation, and has good real-time performance and reliability.
[0027] In some embodiments, the lower bridge arm fault state confirmation module includes a first OR logic gate U1, a second OR logic gate U2, a third OR logic gate U3, a first NAND logic gate A1 and a second NAND logic gate A2, the outputs of the first OR logic gate U1 and the second OR logic gate U2 are connected with the inputs of the first NAND logic gate A1 respectively, the output of the first NAND logic gate A1 is connected with the second input of the third OR logic gate U3, the output of the third OR logic gate U3 is connected with the first input of the second NAND logic gate A2, the first inputs of the first OR logic gate U1, the second OR logic gate U2 and the third OR logic gate U3 are connected with a first fault pin F_DS_BOT, a second fault pin and a third fault pin F_UN_BOT respectively, the second inputs of the first OR logic gate U1 and the second OR logic gate U2 are connected with the fourth fault pin SPD_SW.
[0028] As shown in the figure, Figure 2 F_DS_BOT is a lower bridge arm open circuit and fault pin, F_UN_BOT is a lower bridge arm under voltage fault pin, SPD_SW is a speed input pin, the third fault pin of the third OR logic gate U3 includes two fault types, MCU fault ACTIVE SHORT and over voltage fault F_HV_OV.
[0029] In some embodiments, the upper arm fault state confirmation module comprises a fourth OR gate U4, a fifth OR gate U5, a first AND gate B1, and a second AND gate B2, the outputs of the fourth OR gate U4 and the fifth OR gate U5 are connected with the inputs of the first AND gate B1 respectively, the output of the first AND gate B1 is connected with the second input of the second AND gate B2 and the second input of the second NAND gate A2 respectively, the first inputs of the fourth OR gate U4 and the fifth OR gate U5 are connected with the fifth fault pin F_DS_TOP and the sixth fault pin F_UV_TOP respectively, the second inputs of the fourth OR gate U4 and the fifth OR gate U5 are connected with the fourth fault pin SPD_SW, and the first input of the second AND gate B2 is connected with the output of the first NAND gate A1.
[0030] As shown in Figure 2 F_DS_TOP is the upper arm dropout and fault pin, and F_UN_TOP is the upper arm undervoltage fault pin.
[0031] It can be understood that through the operation of the logic gates in the lower arm fault state confirmation module and the upper arm fault state confirmation module, the six faults and three states can be combined to realize the execution of the fault logic.
[0032] In some embodiments, the protection circuit further comprises a first buffer D1 and a second buffer D2, the outputs of the second NAND gate A2 and the second AND gate B2 are connected with the corresponding pins (Force_Uppers_ON, Force_Lowers_ON) of the first buffer D1, the corresponding pins (Force_Lowers_ON, Force_Uppers_ON) of the second buffer D2, and the corresponding pins of a third buffer D3 respectively.
[0033] The protection circuit further comprises a flip-flop T1, the outputs of the second NAND gate A2 and the second AND gate B2 are connected with the corresponding pins of the flip-flop T1 respectively. The flip-flop T1 is used to add a dead zone in the process of switching the upper and lower arms to prevent the straight-through of the upper and lower arms.
[0034] In some embodiments, the protection circuit further comprises a third AND gate B3, a third NAND gate A3, and a third buffer D3, the two inputs of the third AND gate B3 are connected with the corresponding pins (3, 10) of the flip-flop respectively, the output of the third AND gate B3 is connected with the first input of the third NAND gate A3, and the output of the third NAND gate A3 is connected with the corresponding pins (1, 19) of the third buffer D3. Among them, the third AND gate B3 and the third NAND gate A3 are used to enable the active protection circuit.
[0035] It can be understood that the active short circuit protection circuit of the present disclosure is composed of five OR gates, three AND gates, three NAND gates, three buffers and a flip-flop. By the operation of the logic gates, six faults and three states are combined, and the dead zone circuit of the flip-flop is matched, so as to ensure the shoot-through problem of the upper and lower bridge arms during the switching process of the upper and lower bridge arms.
[0036] The disclosed embodiment also provides an active short circuit protection method, which comprises the active short circuit protection circuit as described above, and the method comprises: a motor controller monitoring a lower bridge arm combined fault state and an upper bridge arm combined fault state of a power module, wherein the lower bridge arm combined fault comprises a lower bridge arm overcurrent and fault and a lower bridge arm undervoltage fault, and the upper bridge arm combined fault comprises an upper bridge arm overcurrent and fault and an upper bridge arm undervoltage fault; when one of the lower bridge arm overcurrent and fault and the lower bridge arm undervoltage fault is low, according to a motor speed at a fault time and an upper bridge arm fault state, a first safety mode into which the motor enters is determined; when one of the upper bridge arm overcurrent and fault and the upper bridge arm undervoltage fault is low, according to a motor speed at a fault time and a lower bridge arm fault state, a second safety mode into which the motor enters is determined.
[0037] The first safety mode comprises a three-phase open circuit safety mode and an upper bridge arm active short circuit safety mode, and the second safety mode comprises a three-phase open circuit safety mode and a lower bridge arm active short circuit safety mode; when one of the lower bridge arm overcurrent and fault and the lower bridge arm undervoltage fault is low, according to a motor speed at a fault time and an upper bridge arm fault state, a first safety mode into which the motor enters is determined, which comprises: when the motor speed exceeds a threshold value and the upper bridge arm is fault-free, the motor enters the upper bridge arm active short circuit safety mode; when the motor speed exceeds the threshold value and the upper bridge arm is faulty, the motor enters the three-phase open circuit safety mode; when one of the upper bridge arm overcurrent and fault and the upper bridge arm undervoltage fault is low, according to a motor speed at a fault time and a lower bridge arm fault state, a second safety mode into which the motor enters is determined, which comprises: when the motor speed exceeds the threshold value and the lower bridge arm is fault-free, the motor enters the lower bridge arm active short circuit safety mode; when the motor speed exceeds the threshold value and the lower bridge arm is faulty, the motor enters the three-phase open circuit safety mode.
[0038] The active short circuit protection method further comprises: the motor controller monitoring an MCU fault and an overvoltage fault; when one of the MCU fault and the overvoltage fault is low: if the lower bridge arm is fault-free, the motor enters the lower bridge arm active short circuit safety mode; if the lower bridge arm is faulty and the upper bridge arm is faulty, the motor enters the three-phase open circuit safety mode; if the lower bridge arm is faulty and the upper bridge arm is fault-free, the motor enters the upper bridge arm active short circuit safety mode.
[0039] It can be understood that the motor controller monitors the related faults in real time, combines six fault modes of the power module's over-protection and fault, the power module's under-voltage fault, the MCU's and over-voltage fault, and judges whether to enter the active short-circuit safety mode according to the vehicle speed at the fault moment, if the speed needs to enter the active short-circuit mode, the three-phase short-circuit state of the lower bridge arm is entered preferentially, if the power module of the lower bridge arm appears a fault, the three-phase active short-circuit state of the upper bridge arm is automatically switched to, and a dead zone is added in the process of switching the upper and lower bridge arms to prevent the upper and lower bridge arms from being short-circuited. If the upper and lower bridge arms are both in the fault state, the six-phase open-circuit state is entered, the fault logic meets the functional safety requirements of the new energy vehicle at the moment of the motor driver fault, does not need software participation, and has high real-time and reliability.
[0040] The embodiment of the present application also provides a motor comprising the protection circuit as described above. For other parts of the motor, refer to the prior art, which will not be repeated here.
[0041] The embodiment of the present application also provides an automobile comprising the motor as described above. For other parts of the automobile, refer to the prior art, which will not be repeated here.
[0042] It should be noted that, in the description of the present application, the terms "first", "second" and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified and limited, the meaning of "a plurality of" is two or more.
[0043] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection or communication with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0044] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.
[0045] Any procedural or methodological descriptions in flow charts or otherwise described herein can be understood to represent modules, segments, or portions of code that include executable instructions for implementing the logic functions or procedures described, and the scope of preferred embodiments of the present application includes additional implementations in which the functions can be performed in an order different from that shown or discussed, including substantially simultaneously, or in reverse order, as will be understood by those having ordinary skill in the art to which embodiments of the present application pertain.
[0046] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner.
[0047] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be construed as limiting the present application, and those of ordinary skill in the art can make changes, modifications, replacements, and variations to the above-described embodiments within the scope of the present application.
Claims
1. An active short circuit protection circuit, characterized by The protection circuit comprises: a motor controller, a lower bridge arm fault state confirmation module and an upper bridge arm fault state confirmation module, the motor controller is used for According to the triggered fault type, confirming at least one fault module of the lower bridge arm fault state confirmation module and the upper bridge arm fault state confirmation module, According to the fault module, controlling a motor connected with the motor controller to enter a corresponding safety mode.
2. The protection circuit of claim 1, wherein, The lower bridge arm fault state confirmation module comprises a first OR logic gate, a second OR logic gate, a third OR logic gate, a first NAND logic gate and a second NAND logic gate, The outputs of the first OR logic gate and the second OR logic gate are connected with the input of the first NAND logic gate, The output of the first NAND logic gate is connected with the second input of the third OR logic gate, The output of the third OR logic gate is connected with the first input of the second NAND logic gate, The first inputs of the first OR logic gate, the second OR logic gate and the third OR logic gate are connected with a first fault pin, a second fault pin and a third fault pin respectively, The second inputs of the first OR logic gate and the second OR logic gate are connected with a fourth fault pin.
3. The protection circuit of claim 2, wherein, The upper bridge arm fault state confirmation module comprises a fourth OR logic gate, a fifth OR logic gate, a first AND logic gate and a second AND logic gate, The outputs of the fourth OR logic gate and the fifth OR logic gate are connected with the input of the first AND logic gate, The output of the first AND logic gate is connected with the second input of the second AND logic gate and the second input of the second NAND logic gate respectively, The first inputs of the fourth OR logic gate and the fifth OR logic gate are connected with a fifth fault pin and a sixth fault pin respectively, The second inputs of the fourth OR logic gate and the fifth OR logic gate are connected with the fourth fault pin, The first input of the second AND logic gate is connected with the output of the first NAND logic gate.
4. The protection circuit of claim 3, wherein, The protection circuit further comprises a first buffer and a second buffer, The outputs of the second NAND logic gate and the second AND logic gate are connected with corresponding pins of the first buffer and the second buffer respectively.
5. The protection circuit of claim 4, wherein, The protection circuit further comprises a flip-flop, The outputs of the second NAND logic gate and the second AND logic gate are connected with corresponding pins of the flip-flop respectively.
6. The protection circuit of claim 5, wherein, The protection circuit further comprises a third AND logic gate, a third NAND logic gate and a third buffer, Two inputs of the third AND logic gate are connected with corresponding pins of the flip-flop respectively, The output of the third AND logic gate is connected with the first input of the third NAND logic gate, The output of the third NAND logic gate is connected with a corresponding pin of the third buffer.
7. An electric machine characterized by The protection circuit comprises the protection circuit according to any one of claims 1-6.
8. An automobile characterized by comprising: The motor comprises the motor according to claim 7.