Ultra-narrow mesa groove IGBT (Insulated Gate Bipolar Translator) device and power module
By introducing an ultra-narrow mesa structure into IGBT devices and setting conductive contact areas and doped areas, the contradiction between power density improvement and device reliability is resolved, realizing IGBT devices and modules with high power density and high reliability.
Patent Information
- Application Number
- CN202520348954.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-02-28
AI Technical Summary
When increasing the power density of existing IGBT devices, the reliability of the devices decreases, especially in high-performance applications. The reduction in cell size leads to poor threshold voltage consistency, which affects the reliability of the devices and modules.
Introducing an ultra-narrow mesa structure into IGBT devices, by setting a first trench gate and a second trench gate, and setting a conductive contact area and a doped area in between, reduces parasitic capacitance and improves switching speed. At the same time, it ensures the consistency and reliability of threshold voltage without reducing the width of electrode contact holes.
It achieves a reduction in mesa width and cell pitch without decreasing electrode contact hole width and distance, thereby improving device power density and reliability. It is suitable for medium and high frequency applications, and the internal thermal imbalance phenomenon of parallel connected power modules is suppressed.
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Figure CN223859529U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the field of semiconductor devices, and relates to a super-narrow mesa trench IGBT device and power module. BACKGROUND
[0002] Semiconductor power devices are the core components of power electronics technology, and are mainly used for controlling, converting and transmitting electric energy to realize efficient transmission and distribution of electric energy. Among many power devices, insulated gate bipolar transistors (IGBT) as a composite device voltage drive type power semiconductor device, which combines the low on-state voltage drop of bipolar junction transistors (BJT) and the fast switching speed of metal oxide semiconductor field effect transistors (MOSFET), is widely used in technical fields such as home appliances, industrial control, photovoltaic and wind power generation, and new energy vehicles.
[0003] At present, IGBT chip technology has developed to the seventh generation, and the mesa width between the gate trenches of the IGBT device has approached sub-micron level, which has significantly increased the power density of the IGBT. However, with the rapid development of application fields, the performance requirements (such as power density) of IGBT are still increasing, and the power density of IGBT can be further increased by reducing the on-state voltage drop of IGBT, but the reliability of IGBT chips and IGBT modules will decrease in actual application.
[0004] Therefore, how to provide a super-narrow mesa trench IGBT device to improve the power density while ensuring the reliability of the device has become an important technical problem to be solved by those skilled in the art.
[0005] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. CONTENT OF THE UTILITY MODEL
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the utility model is to provide a super-narrow mesa trench IGBT device and power module to improve the problem that the reliability of the device is affected when the power density of the trench IGBT device is improved in the prior art.
[0007] To achieve the above object and other related objects, in a first aspect, there is provided an ultra-narrow mesa trench IGBT device, comprising:
[0008] a semiconductor layer comprising a first conductivity type doped layer;
[0009] an active region in the semiconductor layer, the active region comprising at least one cell, the cell comprising at least one first trench gate and at least one second trench gate, the first trench gate and the second trench gate both penetrating the first conductivity type doped layer, and a second conductivity type doped region and a first conductivity type contact region being between adjacent first trench gate and second trench gate, the second conductivity type doped region being adjacent to the first trench gate, and the first conductivity type contact region being adjacent to the second trench gate;
[0010] a contact hole unit comprising a plurality of first electrode contact holes, the first electrode contact holes penetrating a portion of the first conductivity type doped layer, and the first conductivity type contact region being at the bottom of the first electrode contact holes.
[0011] Optionally, at least one side of each first trench gate has the second trench gate.
[0012] Optionally, the cell pitch of the trench IGBT device is less than or equal to 1.5 μm.
[0013] Optionally, the width of the second conductivity type doped region ranges from 0.4 μm to 0.6 μm, and the width of the first electrode contact hole ranges from 0.2 μm to 0.4 μm.
[0014] Optionally, the trench IGBT device further comprises a first electrode layer above the semiconductor layer, and the first electrode layer also fills into the plurality of first electrode contact holes.
[0015] Optionally, the first electrode layer also abuts the sidewall of the first trench gate adjacent to the second trench gate.
[0016] Optionally, the first trench gate comprises a first trench and a first gate electrode filled in the first trench, and the trench IGBT device further comprises a second electrode layer, and the first gate electrode is electrically connected to the second electrode layer.
[0017] Optionally, the second trench gate comprises a second trench and a second gate electrode filled in the second trench, and the second gate electrode is electrically connected to one of the first electrode layer and the second electrode layer.
[0018] Optionally, the second trench gate comprises a second gate dielectric covering the inner wall of the second trench and coating the second gate electrode.
[0019] In a second aspect, a power module is provided, comprising a plurality of the ultra-narrow mesa trench IGBT devices as described above, and the plurality of the ultra-narrow mesa trench IGBT devices are connected in parallel.
[0020] As described above, the ultra-narrow mesa trench IGBT device has the following beneficial effects:
[0021] 1) By setting the first trench gate and the second trench gate in the cell, and setting the first conductive type contact region and the second conductive type doped region in the region between the first trench gate and the second trench gate, the first conductive type contact region is adjacent to the second trench gate, and the second conductive type doped region is adjacent to the first trench gate, which can reduce the parasitic capacitance of the chip based on the setting of the second trench gate, improve the switching speed of the device, so that the device is well applied in the medium and high frequency field, while reducing the mesa width and the cell pitch, enhancing the carrier storage effect in the chip cell close to the emitter region, so that the conductivity of the drift region is significantly increased, thereby reducing the on-voltage drop of the IGBT and increasing the power density;
[0022] 2) Further setting the first electrode layer adjacent to the side wall of the second trench gate close to the first trench gate, so that the threshold voltage consistency of the device and the reliability of the device are ensured without reducing the first electrode contact hole width and the distance between the first electrode contact hole and the first trench gate, while the mesa width and the cell pitch can be further reduced;
[0023] 3) The IGBT device structure is relatively simple and easy to realize, has good compatibility with the manufacturing process of the existing IGBT device, and can be obtained without increasing additional process steps and process difficulty, and is suitable for large-scale production.
[0024] The power module of the utility model has the threshold voltage consistency of the internal IGBT device effectively guaranteed, the thermal imbalance phenomenon in the power module is effectively inhibited, the reliability is effectively improved, and therefore has high power density and high reliability. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 The structure schematic diagram of a trench IGBT device is shown.
[0026] Figure 2 The first structure schematic diagram of the ultra-narrow mesa trench IGBT device provided by the embodiment of the application is shown.
[0027] Figure 3 The second structure schematic diagram of the ultra-narrow mesa trench IGBT device provided by the embodiment of the application is shown.
[0028] Figure 4Fig. 3 shows a third structure of the super-narrow mesa trench IGBT device provided in the embodiments of the present application.
[0029] Legend of reference numerals:
[0030] 1-drift region, 2-base region, 3-trench gate, 301-trench, 302-gate dielectric, 303-gate electrode, 4-dielectric layer, 5-emitter metal, 6-emitter contact hole, 7-emitter region, 8-contact region;
[0031] 10-semiconductor layer, 11-first conductive type doped layer, 12-second conductive type drift layer;
[0032] 21-first trench gate, 211-first trench, 212-first gate electrode, 213-first gate dielectric, 22-second trench gate, 221-second trench, 222-second gate electrode, 223-second gate dielectric, 23-second conductive type doped region, 24-first conductive type contact region;
[0033] 30-first electrode contact hole; 40-first electrode layer; 50-interlayer dielectric. DETAILED DESCRIPTION
[0034] The above embodiments of the present application are only used to illustrate the principles of the present application and explain the advantages thereof, but are not used to limit the scope of the present application. According to the present application, other advantages can be easily understood by those skilled in the art. The present application can be implemented or applied in other different embodiments, and the details in the present application can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.
[0035] Please refer to Figures 1 to 4 It is to be noted that the drawings provided in the embodiments of the present application only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, but the drawings are not drawn according to the number, shape and size of the components in the actual implementation, and the shape, number and proportion of the components in the actual implementation can be randomly changed, and the layout pattern of the components can be more complex.
[0036] Please refer to Figure 1This diagram illustrates the structure of an IGBT device, which mainly includes a drift region 1, a base region 2, multiple trench gates 3 (each trench gate 3 includes a trench 301, a gate dielectric 302, and a gate electrode 303), a dielectric layer 4, and an emitter metal 5. An emitter region 7 is provided in the base region 2 between adjacent trench gates 3. The emitter metal 5 extends to the base region 2 through emitter contact holes 6 and is adjacent to the emitter region 7. The emitter contact holes 6 maintain a certain distance from the trench gates 3 on both sides (e.g., the width c1 of the emitter region 7). Furthermore, to reduce ohmic contact resistance, a contact region 8 is formed at the bottom of the emitter contact hole 6 through ion implantation (primarily determined by the position of the emitter contact hole 6). In current processes, by strictly controlling the ion implantation and annealing processes during the formation of the contact region 8, the diffusion of implanted impurities into the vicinity of the trench region (unmarked) of the trench gate 3 can be avoided, thereby maintaining the consistency of the threshold voltage Vth of the IGBT device. Otherwise, the impurities injected into the contact region 8 will diffuse to the channel region at the sidewall of the trench gate 3 during the injection and annealing process, affecting the doping concentration of the channel region and the interface state charge status at the interface between the gate dielectric 302 of the trench gate 3 and the semiconductor layer where the base region 2 is located.
[0037] An IGBT device has a gate (electrically connected to the trench gate), an emitter (electrically connected to the emitter metal), and a collector (not shown). When the voltage Vge applied between the gate and emitter of the IGBT device is greater than the threshold voltage Vth, an inversion layer is formed in the base region 2 at the sidewall of the trench gate 3 as a channel (i.e., the threshold voltage is the minimum voltage required for channel formation). When a certain positive voltage Vce is applied to the collector relative to the emitter, holes are injected into the drift region 1 from the collector region (not shown), and electrons are injected into the drift region 1 through the channel from the emitter region 7, thereby forming a conductive path and turning on the IGBT device. During the conduction process of the IGBT device, if Vge is reduced below the threshold voltage, the channel is turned off, the current gradually decreases to zero, and the IGBT device is turned off.
[0038] To meet high-performance requirements, the cell pitch of IGBT devices can be further reduced. Figure 1 (as shown in a1) and the width of the table ( Figure 1 As shown in b1), this design enhances carrier storage near the emitter metal 5, increases the conductivity of the drift region 1, and reduces the on-state voltage drop, ultimately achieving higher power density. However, limitations in photolithography precision restrict the width of the emitter contact hole 6 (as shown in b1). Figure 1The adjustment space of the mesa width (as shown in d1) is limited, and the reduction of the mesa width will inevitably shorten the distance between the emitter contact hole 6 and the trench gate 3. At this time, relying solely on process control cannot completely avoid the diffusion of impurities in the contact area 8 to the vicinity of the trench gate 3, thereby causing threshold voltage drift and affecting the threshold voltage consistency of the chip. In addition, IGBT modules are generally used in new energy automobile main drive, high-power photovoltaic and industrial control application fields, and a plurality of IGBT devices are generally connected in parallel in the internal structure design of the IGBT module. If the threshold voltage consistency of the plurality of IGBT devices is poor, dynamic uneven current will occur when connected in parallel, and dynamic uneven current will cause some IGBT devices (for example, devices that are turned on first and turned off later) to bear overcurrent at the switching moment, causing thermal imbalance of the devices and the power module, and in severe cases, causing damage to the devices or the power module, thereby affecting reliability.
[0039] Currently, in the seventh generation IGBT technology, the cell pitch has been reduced to about 1.5 μm. If the cell size continues to be reduced to pursue higher power density, the distance between the emitter contact hole 6 and the trench gate 3 will be further reduced, and the threshold voltage consistency will be deteriorated, which will eventually affect the reliability of the device and the module (i.e., the technical problem mentioned in the background technology section). Therefore, how to continue to reduce the cell size to improve the power density while effectively inhibiting the negative impact of the reduction of the cell size on the threshold voltage consistency of the device, and thereby ensuring the reliability of the IGBT device and the power module, is a technical problem that the technical solution described in the present application is expected to solve.
[0040] The present embodiment provides an ultra-narrow mesa trench IGBT device (hereinafter referred to as "device"). Please refer to Figure 2 , which shows a first structure schematic diagram of the device. The device includes a semiconductor layer 10, an active region and a contact hole unit.
[0041] Specifically, the semiconductor layer 10 comprises a first conductive type doped layer 11. The active region is located in the semiconductor layer 10. The active region comprises at least one cell. The cell comprises at least one first trench gate 21 and at least one second trench gate 22. The first trench gate 21 and the second trench gate 22 both penetrate the first conductive type doped layer 11. The second conductive type doped region 23 and the first conductive type contact region 24 are located between the adjacent first trench gate 21 and the second trench gate 22. The second conductive type doped region 23 is adjacent to the first trench gate 21, and the first conductive type contact region 24 is adjacent to the second trench gate 22. The contact hole unit comprises a plurality of first electrode contact holes 30, the first electrode contact holes 30 penetrate a part of the first conductive type doped layer 11, and the first conductive type contact region 24 is located at the bottom of the first electrode contact hole 30. Wherein, the region between two adjacent trench gates (including the first trench gate 21 or the second trench gate 22) of the first conductive type doped layer 11 is the base region of the device, the second conductive type doped region 23 is the emitter region, and the first conductive type contact region 24 is the emitter metal contact region.
[0042] In an optional embodiment, the first conductive type is P type or N type, the second conductive type is N type or P type, and the first conductive type is different from the second conductive type. In the embodiment of the application, the first conductive type is P type, and the second conductive type is N type, which are taken as examples for illustration. That is, the device comprises a P type base region, an N type emitter region, and a P type contact region.
[0043] In the embodiment of the application, the first trench gate 21 and the second trench gate 22 are arranged in the cell, and the second conductive type doped region 23 and the first conductive type contact region 24 are arranged in the region between the adjacent first trench gate 21 and the second trench gate 22, and the second conductive type doped region 23 is adjacent to the first trench gate 21, and the first conductive type contact region 24 is adjacent to the second trench gate 22. Wherein, the first conductive type contact region 24 is adjacent to the second trench gate 22, so that the second conductive type doped region 23 is no longer arranged on both sides of the top of the second trench gate 22, the mesa width and the cell pitch are reduced. Moreover, the second trench gate 22 does not participate in the channel formation and modulation of the device, so that the impurity elements in the first conductive type contact region 24 can be prevented from diffusing to the sidewall region of the second trench gate 22 to reduce the probability of threshold voltage drift caused thereby, and the threshold voltage consistency of the device can be ensured.
[0044] In optional embodiments, the cell pitch a2 of the device is less than or equal to 1.5 μm, which can be 1.0 μm, 1.2 μm or even less than 1.0 μm. In particular, as the cell pitch is reduced, the effect of the scheme of the embodiments of the present application on the threshold voltage consistency of the device is more obvious, and the process applicability is better. That is, the scheme provided by the embodiments of the present application is particularly suitable for the reliability guarantee of the device structure with a small cell pitch.
[0045] In optional embodiments, the width (range of c2) of the second conductive type doped region 23 is 0.4 μm to 0.6 μm (including the end point value), for example, the width c2 of the second conductive type doped region 23 can be 0.45 μm, 0.50 μm or 0.55 μm. The width (range of d2) of the first electrode contact hole 30 is 0.2 μm to 0.4 μm (including the end point value), for example, the width d2 of the first electrode contact hole 30 can be 0.25 μm, 0.30 μm or 0.35 μm. It should be noted that the above-mentioned width range of the first electrode contact hole 30 is based on the accuracy of the current photolithography equipment and the accuracy of the etching process. If the accuracy of the future photolithography equipment and the technical scheme of the etching process can realize the production of a first electrode contact hole 30 with a smaller width, the lower limit of the width of the first electrode contact hole 30 can be further reduced. In addition, without causing ambiguity, when the active region includes a plurality of cells, the width direction herein refers to the arrangement direction of the plurality of cells.
[0046] In optional embodiments, the device further includes a first electrode layer 40, which is located above the semiconductor layer 10, and the first electrode layer 40 also fills into a plurality of the first electrode contact holes 30. In the embodiments of the present application, the first electrode layer 40 is an emitter metal layer, and correspondingly, the first electrode contact hole 30 is an emitter contact hole.
[0047] In optional embodiments, as shown in Figure 2 , the first electrode layer 40 also abuts the sidewall of the second trench gate 22 close to the first trench gate 21, that is, the first electrode contact hole 30 exposes the sidewall of the second trench gate 22 close to the first trench gate 21. Under the premise that the width of the first electrode contact hole 30 and the width of the second conductive type doped region 23 are not adjusted (that is, c1 in Figure 1 is equal to c2 in Figure 2 , Figure 1 d1 in Figure 2(d2 is equal in the original text), the first electrode layer 40 and the second trench gate 22 are adjacent to the sidewall of the first trench gate 21, which means that there is no longer a mesa region between the first electrode contact hole 30 and the second trench gate 22, thus further reducing the cell pitch (a2) and mesa width (b2) of the device. (Comparison) Figure 1 and Figure 2 It is understood that in the embodiments of this application, both the cell pitch and the mesa width are reduced by c1. Furthermore, with the same structure and distribution of the first trench gate 21 and the second trench gate 22 in the cell structure, the power density of the device can be further improved.
[0048] In an optional embodiment, the first trench gate 21 includes a first trench 211 and a first gate electrode 212 filled within the first trench 211. The device further includes a second electrode layer (not shown), and the first gate electrode 212 is electrically connected to the second electrode layer. In this embodiment, the second electrode layer is a gate metal layer, the first trench gate 21 is an effective trench gate that can enable channel opening, and the second trench gate 22 is a virtual trench gate. The material of the first gate electrode 212 includes polysilicon (including doped polysilicon). The first trench gate 21 also includes a first gate dielectric 213 covering the inner wall of the first trench 211, and the material of the first gate dielectric 213 includes silicon dioxide.
[0049] In an optional embodiment, the second trench gate 22 includes a second trench 221 and a second gate electrode 222 filled within the second trench 221. The second gate electrode 222 is electrically connected to one of the first electrode layer 40 and the second electrode layer. For example, the second gate electrode 222 is electrically connected to the first electrode layer 40, or the second gate electrode 222 is electrically connected to the second electrode layer. Different electrical connections of the second gate electrode 222 will cause changes in the device's performance parameters.
[0050] In the embodiments of the present application, the second gate electrode 222 is preferably electrically connected with the first electrode layer 40 for the purpose of ensuring the consistency of the threshold voltage. If the second gate electrode 222 is electrically connected with the second electrode layer, although the second gate electrode 222 does not participate in the formation and modulation process of the channel, the additional gate connection can couple the electric field of the second trench gate 22 with the electric field of the first trench gate 21 through the coupling effect, thereby affecting the consistency of the threshold voltage of the first trench gate 21. Moreover, it will also increase the gate-emitter capacitance Cge, and slight process fluctuations (for example, the thickness of the first gate dielectric 213 / second gate dielectric 223) will significantly change the capacitance value, thereby amplifying the threshold voltage drift. If the second gate electrode 222 is electrically connected with the first electrode layer 40, the second trench gate 22 is clamped by the emitter potential (usually grounded or fixed potential), the electric field distribution of the second trench gate 22 is more stable, and it will not interfere with the electric field of the first trench gate 21 through capacitive coupling, thereby avoiding the threshold voltage drift caused by capacitive coupling. That is, the connection of the second gate electrode 222 with the first electrode layer 40 can significantly reduce the threshold voltage dispersion of the device. At this time, the second trench gate 22 can act as a field plate to reduce the electric field concentration phenomenon at the bottom corner of the first trench gate 21, indirectly reduce the electric field stress of the gate dielectric layer, thereby reducing the generation probability of interface state charges at the interface between the gate dielectric layer and the semiconductor layer 10, reducing the accumulation of interface state charges, thereby suppressing the long-term drift of the threshold voltage.
[0051] In addition, in the case that the first electrode layer 40 also abuts against the sidewall of the second trench gate, i.e. in the case that the first electrode contact hole 30 exposes a part of the sidewall of the second trench gate 22, due to the limited accuracy of photolithography alignment and etching process control, in the etching process of the first electrode contact hole 30, a part of the second gate dielectric 223 covered by the sidewall of the second trench gate 22 can be etched, and the thickness of the dielectric material between the first electrode layer 40 filled in the first electrode contact hole 30 and the second gate electrode 222 filled in the second trench 221 becomes thin, which can affect the withstand voltage between the emitter and the gate in the case that the second gate electrode 222 is connected to the second electrode layer. In the extreme case, if the dielectric layer of the sidewall of the second trench gate 22 is completely etched (i.e. etched through) in the etching process of the first electrode contact hole 30, the first electrode layer 40 filled in the first electrode contact hole 30 will be short-circuited with the second gate electrode 222, which means that the emitter and the gate are short-circuited, resulting in the failure of the device. Therefore, considering the photolithography alignment drift and the control accuracy of the etching process in actual production, the second gate dielectric 223 of the second trench gate 22 can be lost or even etched through in the etching process of the contact hole 30, and in order to ensure the reliability of the device, the second gate electrode 222 is preferably electrically connected to the first electrode layer 40. Of course, if the above factors are excluded and other performance considerations are taken into account, the second gate electrode 222 can also be electrically connected to the second electrode layer.
[0052] In an optional embodiment, the second trench gate 22 comprises a second gate dielectric 223 covering the inner wall of the second trench 221 and covering the second gate electrode 222. Compared with the conventional structure, the second gate dielectric 223 of the second trench gate 22 is not completely covered by the second gate electrode 222, but the second gate electrode 222 is filled in the second trench 221, and the top surface of the second gate electrode 222 is lower than the top surface of the semiconductor layer 10, leaving a space for further filling of the dielectric layer. Figure 1 With the above structure, the second gate electrode 222 is not completely covered by the second gate dielectric 223, and the top surface of the second gate electrode 222 is lower than the top surface of the semiconductor layer 10, leaving a space for further filling of the dielectric layer. Figure 2 It can be seen that, in general, the gate dielectric of the trench gate only covers the inner wall of the trench, the gate electrode is located above the gate dielectric layer and fills the entire trench, the top surface of the gate electrode is flush with the top surface of the semiconductor layer 10, and the gate dielectric layer does not completely cover the gate electrode. In the embodiment of the present application, considering that the etching process of the first electrode contact hole 30 can cause process errors and deviate towards the sidewall of the second trench gate 22, and thus there is a possibility of etching through the second gate dielectric 223, causing the first electrode layer 40 to be short-circuited with the second gate electrode 222. Therefore, when the second gate electrode 222 is filled in the second trench 221, the material of the second gate electrode 222 does not fill the second trench 221 (i.e. the top surface of the second gate electrode 222 is lower than the top surface of the semiconductor layer 10), leaving a space for further filling of the dielectric layer, so that compared with the conventional structure (for example, the gate dielectric of the trench gate completely covers the gate electrode, and the top surface of the gate electrode is flush with the top surface of the semiconductor layer 10), the dielectric layer between the first electrode layer 40 and the second gate electrode 222 is thicker, which can improve the withstand voltage between the emitter and the gate. Figure 1In the embodiment shown in FIG. 2, the thickness of the dielectric layer above the second gate electrode 222 is increased, which ensures that the thickness of the second gate dielectric 223 is sufficient to withstand the loss of the etching process of the first electrode contact hole 30, and reduces the probability of etching through the second gate dielectric 223, so that the electrical connection object of the second gate electrode 222 is not limited to the first electrode layer 40, to meet the implementation of other performance parameters of the device.
[0053] In an optional embodiment, the device further comprises an interlayer dielectric 50 above the semiconductor layer 10, and the first electrode contact hole 30 penetrates the interlayer dielectric 50. In the case where the second gate dielectric 223 covers the second gate electrode 222, the part of the second gate electrode 223 covering the top surface of the second gate electrode 222 can be filled into the part of the second trench 221 by the interlayer dielectric 50, or the part is formed separately from the interlayer dielectric 50 (for example, after filling the second gate electrode 223, a thermal oxidation process is performed to oxidize the top surface of the second gate electrode 223 into an oxide layer).
[0054] In an optional embodiment, at least one side of each first trench gate 21 has the second trench gate 22. In the case where the cell includes a plurality of first trench gates 21 and / or a plurality of second trench gates 22, the positions of the first trench gates 21 and the second trench gates 22 included therein need to be reasonably arranged, so that at least one side of each first trench gate 21 has the second trench gate 22 (i.e., the cell structure includes adjacent first trench gates 21 and second trench gates 22), and then the first conductive type contact region 24 and the second conductive type doped region 23 between the adjacent first trench gate 21 and the second trench gate 22 are arranged, and the position of the first electrode contact hole 30 extending into the region is set, to realize the reduction of the cell pitch and the mesa width, and at the same time ensure the reliability of the device.
[0055] In an optional embodiment, the cell includes two first trench gates 21 and at least one second trench gate 22, wherein the second trench gate 22 can be one, two, three or more than three. For example, the cell includes one second trench gate 22, and two first trench gates 21 are arranged on the two sides of the second trench gate 22 (as shown in FIG. 3). Figure 2 For example, the cell includes two second trench gates, and two first trench gates 21 and two second trench gates 22 are alternately arranged (as shown in FIG. 4). Figure 3 For example, the cell includes two second trench gates, and two first trench gates 21 and two second trench gates 22 are alternately arranged (as shown in FIG. 4). Figure 4For example, as shown in FIG. 1, the cell includes one second trench gate 22, and the arrangement of the second trench gate 22 and the first trench gate 21 can be AD (where A represents the first trench gate 21 and D represents the second trench gate 22). As another example, as shown in FIG. 2, the cell includes two second trench gates 22, and the arrangement of the three second trench gates 22 and the two first trench gates 21 can be ADDDA, ADDAD, ADADD, DADAD, DADDA, or DDADA (where A represents the first trench gate 21 and D represents the second trench gate 22). In the case where more than one second trench gate 22 is included in the cell, there can be a case where two second trench gates 22 are arranged adjacently, in which case a contact region is also formed in a region between the two second trench gates 22 in the first-conductivity-type doped layer 11.
[0056] For the avoidance of doubt, the mesa width refers to the distance between two trench gates (the first trench gate 21 or the second trench gate 22) that are adjacent. For example, as shown in FIG. 1, the mesa width is the distance between the side wall of the first trench gate 21 that is close to the second trench gate 22 and the side wall of the second trench gate 22 that is close to the first trench gate 21. The cell pitch refers to the distance between the same side walls of two trench gates that are adjacent. For example, as shown in FIG. 1, the cell pitch is the distance between the side wall of the second trench gate 22 that is away from the first trench gate 21 (for example, the left side wall of the second trench gate 22) and the side wall of the first trench gate 21 that is close to the second trench gate 22 (for example, the left side wall of the first trench gate 21). Figure 2 Figure 2 For the avoidance of doubt, the mesa width refers to the distance between two trench gates (the first trench gate 21 or the second trench gate 22) that are adjacent. For example, as shown in FIG. 1, the mesa width is the distance between the side wall of the first trench gate 21 that is close to the second trench gate 22 and the side wall of the second trench gate 22 that is close to the first trench gate 21. The cell pitch refers to the distance between the same side walls of two trench gates that are adjacent. For example, as shown in FIG. 1, the cell pitch is the distance between the side wall of the second trench gate 22 that is away from the first trench gate 21 (for example, the left side wall of the second trench gate 22) and the side wall of the first trench gate 21 that is close to the second trench gate 22 (for example, the left side wall of the first trench gate 21).
[0057] In the embodiments of the present application, the cell includes the first trench gate and the second trench gate. The emitter region is formed on the periphery of the sidewall of the first trench gate, and the contact region is formed on the periphery of the second trench gate without forming the emitter region, so that the channel formation and modulation can be realized only through the second trench gate. In addition, when the second trench gate is connected with different electrodes (the first electrode layer 40 and the second electrode layer), the different performances of the device are affected. Therefore, the electrical connection relationship of the second trench gate, the number (or proportion) of the second trench gate in a single cell, and the arrangement mode between the second trench gate and the first trench gate affect the channel number, channel density, and parasitic capacitance of the device, thereby affecting the performance parameters such as the on-state voltage drop, switching loss, and short-circuit resistance during the period. For example, the electrical connection between the first trench gate and the first electrode layer increases the parasitic capacitance between the gate and the drift region / base region, which may slow down the switching speed and cause the switching loss to rise. Therefore, the trade-off relationship between the performance parameters of the chip can be realized by reasonably setting the structure parameters in the cell.
[0058] In an optional embodiment, the semiconductor layer 10 further includes a second-conductivity-type drift region 12 (N-type drift region in the embodiments of the present application), and the first-conductivity-type doped layer 11 is located above the second-conductivity-type drift region 12.
[0059] In an optional embodiment, the semiconductor layer 10 further includes a second-conductivity-type substrate (not shown), and the second-conductivity-type substrate is located above the second-conductivity-type drift region 12. The device further includes a third electrode layer (not shown), and the third electrode layer is located below the second-conductivity-type substrate. The second-conductivity-type substrate can be used as the collector region of the device, and the third electrode layer can be used as the collector metal of the device.
[0060] The embodiments of the present application also provide a power module, which includes a plurality of the ultra-narrow mesa IGBT devices as described above, and the plurality of the ultra-narrow mesa IGBT devices are connected in parallel.
[0061] In summary, the ultra-narrow mesa IGBT device of the utility model, through setting first trench gate and second trench gate in cell structure, and setting first conductive type contact area and second conductive type doped area in the area between first trench gate and second trench gate, so that first conductive type contact area and second trench gate are adjacent, and second conductive type doped area and first trench gate are adjacent, can reduce the parasitic capacitance of chip based on the setting of second trench gate, improve the switching speed of device, so that the device is well applied in the medium and high frequency field, reduce the mesa width and cell pitch at the same time, enhance the carrier storage effect of chip cell close to the emitter area, so that the conductivity of drift region increases significantly, so that the on-voltage drop of IGBT device is reduced, and the power density is increased. Further set first electrode layer and second trench gate close to the side wall of first trench gate, so that the threshold voltage consistency of device and the reliability of device are ensured without reducing the width of first electrode contact hole and the distance between first electrode contact hole and first trench gate, and the mesa width and cell pitch can be further reduced. And, the device structure is relatively simple and easy to realize, and has good compatibility with the manufacturing process of the existing IGBT device, and can be obtained without increasing additional process steps and process difficulty, and is suitable for large-scale production. The power module of the utility model effectively guarantees the threshold voltage consistency of the internal IGBT device, effectively suppresses the thermal imbalance phenomenon in the power module, effectively improves the reliability, has high power density and high reliability. Therefore, the utility model effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.
[0062] The above embodiments only exemplarily illustrate the principles and effects of the utility model, and are not used to limit the utility model. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the utility model. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the utility model should be covered by the claims of the utility model.
Claims
1. An ultra-narrow mesa trench IGBT device, characterized by, The trench IGBT device comprises: a semiconductor layer comprising a first conductivity type doped layer; an active region in the semiconductor layer, the active region comprising at least one cell, the cell comprising at least one first trench gate and at least one second trench gate, the first trench gate and the second trench gate both penetrating the first conductivity type doped layer, and a second conductivity type doped region and a first conductivity type contact region between adjacent first trench gate and second trench gate, the second conductivity type doped region being adjacent to the first trench gate, and the first conductivity type contact region being adjacent to the second trench gate; a contact hole unit comprising a plurality of first electrode contact holes, the first electrode contact holes penetrating a portion of the first conductivity type doped layer, and the first conductivity type contact region being at the bottom of the first electrode contact holes.
2. The ultra-narrow mesa trench IGBT device of claim 1, wherein: At least one side of each of the first trench gate has the second trench gate.
3. The ultra-narrow mesa trench IGBT device of claim 1, wherein: The cell pitch of the trench IGBT device is less than or equal to 1.5 μm.
4. The ultra-narrow mesa trench IGBT device of claim 1, wherein: The width of the second conductivity type doped region ranges from 0.4 μm to 0.6 μm, and the width of the first electrode contact hole ranges from 0.2 μm to 0.4 μm.
5. The ultra-narrow mesa trench IGBT device of claim 1, wherein: The trench IGBT device further comprises a first electrode layer above the semiconductor layer, the first electrode layer also filling into the plurality of first electrode contact holes.
6. The ultra-narrow mesa trench IGBT device of claim 5, wherein: The first electrode layer also abuts the sidewall of the first trench gate adjacent to the second trench gate.
7. The ultra-narrow mesa trench IGBT device of claim 5, wherein: The first trench gate comprises a first trench and a first gate electrode filled in the first trench, and the trench IGBT device further comprises a second electrode layer, the first gate electrode being electrically connected to the second electrode layer.
8. The ultra-narrow mesa trench IGBT device of claim 7, wherein: The second trench gate comprises a second trench and a second gate electrode filled in the second trench, the second gate electrode being electrically connected to one of the first electrode layer and the second electrode layer.
9. The ultra-narrow mesa trench IGBT device of claim 8, wherein: The second trench gate comprises a second gate dielectric covering the inner wall of the second trench and covering the second gate electrode.
10. A power module, characterized by: A plurality of the super-narrow mesa trench IGBT devices as claimed in any one of claims 1-9 are connected in parallel.