Array substrate and display panel

Abstract

The utility model provides an array substrate and a display panel. According to the array substrate, the hydrogen blocking layer is arranged on the surface of the side, facing the substrate, of the first passivation layer, and the hydrogen blocking layer can effectively block hydrogen atoms in hydrogen-containing gas used in the forming process of the passivation layer from diffusing to the thin film transistor. According to the thin film transistor and the manufacturing method thereof, the barrier of the hydrogen blocking layer is arranged on the diffusion path of the hydrogen atoms, so that the bad influence of the hydrogen atoms on the electrical performance of the thin film transistor, especially the active layer in the thin film transistor, is avoided, the stable threshold voltage of the thin film transistor is maintained, and the performance degradation caused by hydrogen diffusion is prevented.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] In the field of display, an array substrate includes a passivation layer formed by a silicon nitride layer or a silicon oxide layer, which can be located on a thin film transistor. The passivation layer can be formed by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD), in which process, a gas containing a large amount of hydrogen, such as SiH4 and NH3, is required to be used. The hydrogen contained in the gas can diffuse into the active layer of the thin film transistor, thereby reducing the threshold voltage of the thin film transistor, and finally leading to the performance degradation of the thin film transistor. SUMMARY

[0003] Therefore, the present application provides an array substrate and a display panel to solve the problem of hydrogen diffusion into the thin film transistor due to the deposition process of the passivation layer, which degrades the performance of the thin film transistor.

[0004] The technical scheme adopted by the present application to solve the above technical problem is as follows:

[0005] In a first aspect, the embodiments of the present application provide an array substrate, comprising:

[0006] a substrate;

[0007] a thin film transistor arranged on one side of the substrate;

[0008] a common electrode arranged on a side of the thin film transistor away from the substrate;

[0009] a first passivation layer arranged on a side of the thin film transistor away from the substrate and covering the common electrode;

[0010] a hydrogen barrier layer arranged on a surface of the first passivation layer facing the substrate and wrapping the common electrode.

[0011] In some embodiments of the present application, the array substrate further comprises:

[0012] a second passivation layer arranged on a side of the thin film transistor away from the substrate;

[0013] a planarization layer arranged on a side of the second passivation layer away from the thin film transistor;

[0014] The first passivation layer is arranged on a side of the flat layer away from the thin film transistor and covers the common electrode, and the hydrogen barrier layer is located between the first passivation layer and the common electrode and also between the first passivation layer and the flat layer, so that the hydrogen barrier layer wraps the common electrode.

[0015] In some embodiments of the present application, the thickness of the hydrogen barrier layer ranges from 1 nm to 100 nm.

[0016] In some embodiments of the present application, the thickness of the hydrogen barrier layer is 10 nm.

[0017] In some embodiments of the present application, the etching rate of the hydrogen barrier layer is less than the etching rate of the first passivation layer.

[0018] In some embodiments of the present application, the hydrogen barrier layer is a metal oxide film.

[0019] In some embodiments of the present application, the hydrogen barrier layer is a silicon dioxide film.

[0020] In some embodiments of the present application, the hydrogen barrier layer comprises a metal oxide film and a silicon dioxide film, and the metal oxide film and the silicon dioxide film are stacked in sequence on a side surface of the first passivation layer facing the substrate.

[0021] In some embodiments of the present application, the hydrogen barrier layer comprises two metal oxide films and a silicon dioxide film, and both of the two metal oxide films are arranged between the thin film transistor and the first passivation layer, and the silicon dioxide film is arranged between the two metal oxide films.

[0022] In a second aspect, embodiments of the present application provide a display panel comprising the array substrate as described in the first aspect.

[0023] In summary, due to the adoption of the above technical solutions, the present application at least has the following beneficial effects:

[0024] Embodiments of the present application provide an array substrate and a display panel. By arranging a hydrogen barrier layer on a side surface of a first passivation layer facing a substrate, the hydrogen barrier layer can effectively block hydrogen atoms in a hydrogen-containing gas used in the formation of the passivation layer from diffusing to a thin film transistor, and the hydrogen barrier layer wraps the common electrode and can also protect the common electrode to a certain extent to avoid the formation process of the first passivation layer affecting the common electrode. By arranging the hydrogen barrier layer as a barrier on the diffusion path of the hydrogen atoms, the adverse effects of the hydrogen atoms on the electrical properties of the thin film transistor, especially the active layer in the thin film transistor, are avoided, so that the threshold voltage of the thin film transistor is maintained stable, and performance degradation caused by hydrogen diffusion is prevented. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A schematic diagram of a structure of an array substrate provided by an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a structure of another array substrate provided by an embodiment of the present application.

[0027] BRIEF DESCRIPTION OF DRAWINGS

[0028] 1, substrate; 2, thin film transistor; 21, first metal layer; 211, gate; 22, insulating layer; 221, gate insulating layer; 23, active layer; 24, second metal layer; 241, source; 242, drain; 25, interlayer dielectric layer; 3, first passivation layer; 4, hydrogen barrier layer; 5, second passivation layer; 6, planarization layer; 7, common electrode; 8, pixel electrode; 9, buffer layer; 10, light shielding layer. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0030] In the description of the present application, it should be understood that the words "first", "second", "third" and the like are used only to describe purposes and cannot be understood as indicating or implying relative importance or indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0031] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration". Any embodiment described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other embodiments.

[0032] Please refer to Figure 1 or Figure 2 The embodiment of the present application provides an array substrate 100, which comprises a substrate 1, a thin film transistor 2, a first passivation layer 3 and a hydrogen barrier layer 4. The thin film transistor 2 is arranged on one side of the substrate 1, the first passivation layer 3 is arranged on the side of the thin film transistor 2 away from the substrate 1, and the hydrogen barrier layer 4 is arranged on the surface of the first passivation layer 3 facing the substrate 1.

[0033] The technical solution provided by the present application sets the hydrogen barrier layer 4 on the side surface of the first passivation layer 3 facing the substrate 1. The hydrogen barrier layer 4 can effectively block the diffusion of hydrogen atoms in the hydrogen-containing gas used in the passivation layer forming process to the thin film transistor 2. The hydrogen barrier layer 4 also wraps the common electrode 7 and can protect the good electrical properties of the common electrode 7 to a certain extent, avoiding the influence of the formation process of the first passivation layer 3 on the common electrode 7. By setting the hydrogen barrier layer 4 on the hydrogen atom diffusion path, the adverse effects of hydrogen atoms on the electrical properties of the thin film transistor 2, especially the active layer 23 in the thin film transistor 2, are avoided, thereby maintaining the stable threshold voltage of the thin film transistor 2 and preventing performance degradation caused by hydrogen diffusion.

[0034] In some embodiments, the array substrate further comprises a second passivation layer 5 and a planar layer 6. The second passivation layer 5 is arranged on the side of the thin film transistor 2 away from the substrate 1. The second passivation layer 5 further enhances the protection of the thin film transistor 2, preventing damage to the thin film transistor 2 from external impurities and moisture. The planar layer 6 is arranged on the side of the second passivation layer 5 away from the thin film transistor 2. The common electrode 7 is arranged on the side of the planar layer 6 away from the thin film transistor 2. The planar layer 6 provides a flat surface basis for the common electrode 7, which is conducive to the uniform deposition and good electrical contact of the common electrode 7. The common electrode 7 plays a role in providing a stable electric field during display. The first passivation layer 3 is arranged on the side of the planar layer 6 away from the thin film transistor 2 and covers the common electrode 7. The hydrogen barrier layer 4 is located between the first passivation layer 3 and the common electrode 7 and also between the first passivation layer 3 and the planar layer 6. The hydrogen barrier layer 4 is located between the first passivation layer 3 and the common electrode 7 and between the first passivation layer 3 and the planar layer 6, which can effectively block the diffusion of hydrogen atoms to the active layer 23 of the thin film transistor 2 without affecting the normal function of other functional layers, further improving the stability and reliability of the array substrate, and ensuring the display quality and service life of the display panel.

[0035] In some embodiments, the thickness of the hydrogen barrier layer 4 ranges from 1 nm to 100 nm. The thickness of the hydrogen barrier layer 4 is limited to 1 nm to 100 nm. The thickness of the hydrogen barrier layer 4 is limited to 1 nm to 100 nm. The thickness of the hydrogen barrier layer 4 is limited to 1 nm to 100 nm.

[0036] In some embodiments, the hydrogen barrier layer 4 is a metal oxide film. The metal oxide film is used as the hydrogen barrier layer 4 because the metal oxide has good chemical stability and a dense crystal structure. The chemical stability prevents the hydrogen barrier layer 4 from reacting with other substances and losing the hydrogen barrier property in a complex process environment and during long-term use. The dense crystal structure effectively blocks the diffusion of hydrogen atoms because it is difficult for hydrogen atoms to penetrate the tightly arranged atomic structure, thereby providing reliable hydrogen atom barrier protection for the active layer 23 of the thin film transistor 2 and maintaining the performance stability of the array substrate. The metal oxide can be aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like, and the metal oxide can be formed by an atomic layer deposition process.

[0037] In some embodiments, the hydrogen barrier layer 4 is a silicon dioxide film formed by a chemical vapor deposition process. The silicon dioxide film is used as the hydrogen barrier layer 4 because it has good process compatibility. The use of silicon dioxide as the hydrogen barrier layer 4 allows the hydrogen barrier layer 4 to be prepared using existing equipment and process parameters without the need for additional complex process equipment or process steps, thereby reducing production costs and process development difficulty. At the same time, silicon dioxide also has a certain hydrogen barrier property and can block the diffusion of hydrogen atoms to some extent, thereby protecting the electrical properties of the active layer 23 of the thin film transistor 2.

[0038] In some embodiments, the etching rate of the hydrogen barrier layer 4 is less than the etching rate of the first passivation layer 3, so that the hydrogen barrier layer 4 remains relatively intact when the first passivation layer 3 is patterned and etched, thereby protecting the structure and properties of the hydrogen barrier layer 4 and ensuring that the hydrogen barrier layer 4 continuously and effectively blocks the diffusion of hydrogen atoms during the entire manufacturing process and product use process. This improves the reliability and stability of the array substrate, reduces the risk of hydrogen atom leakage caused by damage to the hydrogen barrier layer 4 due to the etching process, and thereby protects the performance stability of the thin film transistor 2 and the display quality of the display panel. For example, when the first passivation layer 3 is etched, if the etching rate of the hydrogen barrier layer 4 is greater than or equal to the etching rate of the first passivation layer 3, the hydrogen barrier layer 4 will be etched at the same time as the first passivation layer 3 during the etching process, resulting in the destruction of the integrity of the hydrogen barrier layer 4 and the diffusion of hydrogen atoms to the active layer 23 of the thin film transistor 2 through the channels generated by the etching. When the etching rate of the hydrogen barrier layer 4 is less than the etching rate of the first passivation layer 3, the hydrogen barrier layer 4 will only be slightly etched or not etched at all during the etching of the first passivation layer 3, and the structure and hydrogen barrier property of the hydrogen barrier layer 4 are preserved. For example, when a wet etching process is used, the difference in etching rates of the hydrogen barrier layer 4 and the first passivation layer 3 can be achieved by selecting a suitable etchant and controlling the etching time, temperature, and other parameters, thereby protecting the integrity of the hydrogen barrier layer 4 during etching and providing reliable protection for the subsequent hydrogen atom barrier.

[0039] In some embodiments, the hydrogen barrier layer 4 includes a metal oxide thin film and a silicon dioxide thin film, which are stacked in sequence on the side surface of the first passivation layer 3 facing the substrate 1. By setting the hydrogen barrier layer 4 as a mixed layer of two different materials, and each layer of material has a hydrogen barrier effect, the hydrogen barrier ability of the hydrogen barrier layer 4 is further improved. It should be noted that a metal oxide thin film and a silicon dioxide thin film are stacked to form a mixed layer group, and in other embodiments, the hydrogen barrier layer 4 can include a plurality of mixed layer groups stacked.

[0040] In some embodiments, the hydrogen barrier layer 4 includes two metal oxide thin films and a silicon dioxide thin film, the two metal oxide thin films are arranged between the thin film transistor 2 and the first passivation layer 3, and the silicon dioxide thin film is arranged between the two metal oxide thin films. The hydrogen barrier layer 4 is formed by stacking two metal oxide layers and a silicon dioxide layer, which is conducive to improving the hydrogen barrier ability of the hydrogen barrier layer 4, and by arranging the silicon dioxide thin film between the two metal oxide thin films, it is also conducive to improving the strength of the hydrogen barrier layer 4 and maintaining a certain toughness. It should be noted that in addition to including two metal oxide thin films and a silicon dioxide thin film, the hydrogen barrier layer 4 can also continue to stack the three-layer mixed layer structure on the basis of the three-layer mixed layer, that is, the hydrogen barrier layer 4 can form a mixed layer group by two metal oxide thin films and a silicon dioxide thin film, and a plurality of mixed layer groups are stacked.

[0041] In some embodiments, please refer to Figure 1 , the array substrate includes a first metal layer 21, a gate insulating layer 221, an active layer 23, and a second metal layer 24. The first metal layer 21 is arranged on the substrate 1, the gate insulating layer 221 is arranged on the first metal layer 21, the active layer 23 is arranged on the gate insulating layer 221, and the second metal layer 24 is arranged on the gate insulating layer 221 and covers the active layer 23. The second passivation layer 5 covers the second metal layer 24. The first metal layer 21, the second metal layer 24, and the active layer 23 are all patterned after forming, the first metal layer 21 is patterned to form a gate 211, the second metal layer 24 is patterned to form a source 241 and a drain 242, and the active layer 23 is patterned to be arranged in position with the patterned gate 211.

[0042] Further, the thin film transistor 2 includes a gate electrode 211, a gate insulating layer 221, an active layer 23, a source electrode 241 and a drain electrode 242. The gate electrode 211 is disposed on the substrate 1, the gate insulating layer 221 is disposed on the substrate 1 and covers the gate electrode 211, the active layer 23 is disposed on the gate insulating layer 221 and is opposite to the gate electrode 211, and the source electrode 241 and the drain electrode 242 are both disposed on the active layer 23. The gate electrode 211 forms a capacitor structure with the active layer 23 through the gate insulating layer 221, which can effectively control the carrier transmission in the active layer 23 and realize the switching function of the transistor. The source electrode 241 and the drain electrode 242 have good ohmic contact with the active layer 23, which ensures the efficient transmission of electrons between the source electrode 241, the drain electrode 242 and the active layer 23, so that the thin film transistor 2 can quickly and accurately respond to external electrical signals, accurately drive the pixels in the array substrate, and ensure the display effect and response speed of the display panel. The hydrogen barrier layer 4 is above the thin film transistor 2, which can protect the thin film transistor 2 from the influence of hydrogen atom diffusion. Illustratively, if the hydrogen atom diffuses into the active layer 23, it will change the electrical properties of the active layer 23, such as carrier concentration, mobility, etc., which will further affect the control ability of the gate electrode 211 on the active layer 23 and the electron transmission efficiency between the source electrode 241, the drain electrode 242 and the active layer 23, resulting in the performance degradation of the thin film transistor 2. The existence of the hydrogen barrier layer 4 prevents the diffusion of hydrogen atoms, so that the thin film transistor 2 can continue to operate stably, ensuring the accuracy and reliability of the pixel driving in the array substrate.

[0043] Further, the array substrate further includes a pixel electrode 8 disposed on the side of the first passivation layer 3 away from the substrate 1. The first passivation layer 3, the hydrogen barrier layer 4, the planarization layer 6 and the second passivation layer 5 are sequentially provided with through holes which are in communication with each other to expose the source electrode 241 or the drain electrode 242. The pixel electrode 8 extends to the source electrode 241 or the drain electrode 242 through the through holes sequentially provided in the first passivation layer 3, the hydrogen barrier layer 4, the planarization layer 6 and the second passivation layer 5, and is overlapped with the source electrode 241 or the drain electrode 242.

[0044] In some embodiments, please refer to Figure 2The array substrate includes a light shielding layer 10, a buffer layer 9, an active layer 23, an insulating layer 22, a first metal layer 21, an interlayer dielectric layer 25, and a second metal layer 24. The light shielding layer 10 is disposed on the substrate 1, and the buffer layer 9 is also disposed on the substrate 1 and covers the light shielding layer 10. The active layer 23 is disposed on the buffer layer 9, and the insulating layer 22 is disposed on the buffer layer 9 and the active layer 23 and is patterned so that a part of the insulating layer 22 is located on the active layer 23 and a part of the insulating layer 22 is located on the buffer layer 9. The insulating layer 22 located on the active layer 23 is a gate insulating layer 221. The first metal layer 21 is disposed on the buffer layer 9 and covers the active layer 23 and the insulating layer 22, and then the first metal layer 21 is patterned to form a gate 211, which is located on the gate insulating layer 221 and is disposed in alignment with the active layer 23. The interlayer dielectric layer 25 is disposed on the buffer layer 9 and covers the active layer 23, the gate insulating layer 221, and the gate 211. The interlayer dielectric layer 25 is patterned to form a via hole in the interlayer dielectric layer 25, so as to expose a part of the active layer 23. The second metal layer 24 is disposed on the interlayer dielectric layer 25 and is patterned to form a source 241 and a drain 242, which are respectively connected to the active layer 23 through the via hole in the interlayer dielectric layer 25. In summary, in this embodiment, the thin film transistor 2 includes the active layer 23, the gate insulating layer 221, the gate 211, the interlayer dielectric layer 25, the source 241, and the drain 242. The active layer 23 is disposed on a side of the substrate 1 facing the first passivation layer 3, the gate insulating layer 221 is disposed on the active layer 23, the gate 211 is disposed on the gate insulating layer 221 and is opposite to the active layer 23, the interlayer dielectric layer 25 is disposed on a side of the substrate 1 facing the first passivation layer 3 and covers the active layer 23, the gate insulating layer 221, and the gate 211, and the source 241 and the drain 242 are both disposed on the interlayer dielectric layer 25 and are connected to the active layer 23 through the interlayer dielectric layer 25.

[0045] Further, the array substrate further includes a pixel electrode 8 disposed on a side of the first passivation layer 3 away from the substrate 1. The first passivation layer 3, the hydrogen blocking layer 4, the planarization layer 6, and the second passivation layer 5 are sequentially provided with through holes in communication with each other to expose the source 241 or the drain 242. The pixel electrode 8 extends to the source 241 or the drain 242 through the through holes sequentially provided in the first passivation layer 3, the hydrogen blocking layer 4, the planarization layer 6, and the second passivation layer 5 and is connected to the source 241 or the drain 242.

[0046] Embodiments of the present application also provide a display panel including the array substrate described in any of the above embodiments, which has the same beneficial effects as the array substrate, and details are not described herein.

[0047] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0048] Similarly, it should be noted that, in order to simplify the description of the embodiments of this application and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of this application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; a thin film transistor provided on one side of the substrate; a common electrode provided on a side of the thin film transistor away from the substrate; a first passivation layer provided on a side of the thin film transistor away from the substrate and covering the common electrode; a hydrogen barrier layer provided on a surface of the first passivation layer toward the substrate and wrapping the common electrode.

2. The array substrate of claim 1, wherein, The array substrate further comprises: a second passivation layer provided on a side of the thin film transistor away from the substrate; a planarization layer provided on a side of the second passivation layer away from the thin film transistor; wherein the first passivation layer is provided on a side of the planarization layer away from the thin film transistor and covers the common electrode, and the hydrogen barrier layer is located between the first passivation layer and the common electrode and also between the first passivation layer and the planarization layer, so that the hydrogen barrier layer wraps the common electrode.

3. The array substrate of claim 1, wherein, The thickness of the hydrogen barrier layer ranges from 0.1 to 10 microns 4. The array substrate of claim 3, wherein, The thickness of the hydrogen barrier layer is 5. The array substrate of claim 1, wherein, The etching rate of the hydrogen barrier layer is less than the etching rate of the first passivation layer.

6. The array substrate according to any one of claims 1 to 5, wherein, The hydrogen barrier layer is a metal oxide film.

7. The array substrate according to any one of claims 1 to 5, wherein, The hydrogen barrier layer is a silicon dioxide film.

8. The array substrate according to any one of claims 1 to 5, wherein, The hydrogen barrier layer comprises a metal oxide film and a silicon dioxide film, and the metal oxide film and the silicon dioxide film are sequentially stacked on a surface of the first passivation layer toward the substrate.

9. The array substrate according to any one of claims 1 to 5, wherein, The hydrogen barrier layer comprises two metal oxide films and one silicon dioxide film, and the two metal oxide films are both provided between the thin film transistor and the first passivation layer, and the silicon dioxide film is provided between the two metal oxide films.

10. A display panel, characterized by, The array substrate comprises any one of claims 1 to 9.

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