AHB architecture GaN packaging structure of SOP16 packaging 10-pin sealed power supply chip

Abstract

The utility model relates to an AHB architecture GaN packaging structure of a SOP16 packaging 10-pin sealed power supply chip, belonging to the integrated circuit technology field, the packaging structure comprises a first base island, a second base island, a GaN control main chip, a first power GaN tube chip and a second power GaN tube chip, the GaN control main chip and the second power GaN tube chip are arranged in the second base island, the first power GaN tube chip is arranged in the first base island, the second power GaN tube chip is arranged in the second base island, and the second power GaN tube chip is arranged in the second base island. The first power GaN tube chip is arranged in the first base island, the interface end comprises input ends VIN, HB, VCCH, XCD and VCC, an output end CS, control ends VS and FB and grounding ends GND1 and GND2, the first pin, the second pin and the third pin are combined, the twelfth pin and the thirteenth pin are combined, and the fifteenth pin and the sixteenth pin are combined for heat dissipation, so that the heat dissipation efficiency is improved. The tenth pin and the fourteenth pin are removed, and the number of the pins is controlled to be 10 groups, so that the requirement of GaN driving control is ensured, and the design area is saved.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrated circuit technical field, concretely is a SOP16 package 10 pin combined seal power supply chip's AHB architecture GaN package structure. BACKGROUND

[0002] AHB architecture GaN power management chip is based on asymmetric half bridge architecture, integrates two gallium nitride power devices, and the main role is that the cooperation of peripheral components is that alternating current is converted into direct current stable voltage through AHB architecture GaN power management chip high frequency electric energy, but AHB architecture GaN power management chip is driven plus AHB architecture GaN chip working mode is reduced by more than half than conventional mos tube forward voltage, effectively reduces the power consumption of itself under full load working condition, for high-power application environment, may also face challenges in thermal management, there is thermal gradient between multiple chips, and heat transfer and heat dissipation are not efficient enough, which will also lead to the decline of overall system performance, under the background of national vigorous promotion of energy saving and emission reduction and reduction of energy consumption, an SOP16 package type AHB architecture GaN power management chip package is urgently needed. SUMMARY

[0003] The utility model discloses a SOP16 package 10 pin combined seal power supply chip's AHB architecture GaN package structure, to overcome the deficiency of prior art, to solve the above technical problems, the utility model has adopted the following technical scheme:

[0004] A SOP16 package 10 pin combined seal power supply chip's AHB architecture GaN package structure, comprising:

[0005] First base island, first power GaN tube chip is arranged on the first base island, and the first base island is bonded with the first power GaN tube chip through conductive glue;

[0006] Second base island, GaN control main chip and second power GaN tube chip are arranged on the second base island, and the second base island is bonded with the second power GaN tube chip and first power GaN tube chip through conductive glue;

[0007] The interface end comprises an input end VIN, HB, VCCH, XCD, VCC, an output end CS, a control end VS, FB, and ground ends GND1 and GND2. The structure reduces 16 groups of pins to 10 groups of pins, wherein the first pin, the second pin and the third pin are combined as a pin GND1 for heat dissipation, the pin GND1 leads out the ground end GND1, the fourth pin leads out the output end CS as a pin CS, the fifth pin leads out the control end VS as a pin VS, the sixth pin leads out the control end FB as a pin FB, the seventh pin leads out the input end VCC as a pin VCC, the eighth pin leads out the ground end GND2 as a pin GND2, the ninth pin leads out the input end XCD as a pin XCD, the tenth pin and the fourteenth pin are cancelled, the eleventh pin leads out the input end VCCH as a pin VCCH, the twelfth pin and the thirteenth pin are combined as a pin HB leading out the input end CS and performing heat dissipation, and the fifteenth pin and the sixteenth pin are combined as a pin VIN leading out the input end VIN and performing heat dissipation. The pin is optimized to the maximum extent, which can meet the demand of high-power, high-efficiency and fast GaN drive control, save design area, and improve reliability.

[0008] Preferably, the first base island leads out a pin VIN, a pin HB, a pin VCCH and a pin XCD, and the second base island leads out a pin GND1, a pin CS, a pin VS, a pin FB, a pin VCC and a pin GND2.

[0009] Preferably, the GaN control main chip, the first power GaN tube chip and the second power GaN tube chip are arranged in a triangular shape.

[0010] Preferably, the first base island and the second base island are isolated from the input end VIN, HB, VCCH, XCD, VCC, the output end CS and the control end VS, FB through an insulating layer.

[0011] Preferably, the pin GND1, the pin GND2, the pin CS, the pin VS, the pin FB, the pin VCC end and the pin XCD, the pin VCCH, the pin HB and the pin VIN are symmetrically arranged on both sides of the packaging structure.

[0012] Preferably, a first gate G1, a first source S1 and a first drain D1 are arranged on the first power GaN tube chip, a second gate G2, a second source S2 and a second drain D2 are arranged on the second power GaN tube chip, and a control pin GTH and a control pin GTL are arranged on the GaN control main chip.

[0013] Preferably, the first gate G1 connects the control pin GTH, the first source S1 connects the pin HB of the package, the first drain D1 connects the pin VIN of the package, the second gate G2 connects the control pin GTL, the second source S2 connects the pin GND2 of the package, and the second drain D2 connects the pin HB of the package.

[0014] Preferably, the pin CS, the pin VS, the pin FB, the pin VCC, the pin GND1 and the pin GND2, the pin XCD, the pin VCCH and the pin HB are respectively connected to the output terminal CS, the control terminal VS and FB, the input terminal VCC, the ground terminal GND1 and GND2, the input terminal XCD, VCCH and HB by wire bonding, the wire bonding point of the control pin GTH is connected to the first gate G1 point of the first power GaN tube core by wire bonding, the wire bonding point of the control pin GTL is connected to the second gate G2 point of the second power GaN tube core by wire bonding, and the wire diameter of the wire bonding is 1.1 mil.

[0015] Preferably, the first drain D1 of the first power GaN tube core is connected to the pin VIN by wire bonding, the first source S1 point of the first power GaN tube core is connected to the pin HB by wire bonding, the second drain D2 point of the second power GaN tube core is connected to the pin HB by wire bonding, and the second source S2 point of the second power GaN tube core is connected to the pin GND1 by wire bonding.

[0016] Preferably, the back of the first base island and the second base island is exposed to copper skin, so that the chip can be directly welded on the PCB board in application, and excellent and balanced heat dissipation performance is ensured.

[0017] Beneficial effects: the AHB architecture GaN packaging structure of the SOP16 packaging 10-pin combined power supply chip provided by the utility model can reduce 16 groups of pins to 10 groups of pins, the combined pins can dissipate heat, more control pins can be provided, the demand of high-power rapid AHB architecture GaN control can be met, the design area of the combined power supply chip can be saved, more complex scene application demands can be adapted to, the back of the first base island and the second base island is set to exposed copper skin, so that the chip can be directly welded on the PCB board in application, and excellent and balanced heat dissipation performance is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0018] The drawings are used to provide a further understanding of the utility model, and constitute a part of the specification, are used together with the embodiments of the utility model to explain the utility model, and do not constitute the limitation to the utility model.

[0019] In the drawings:

[0020] Figure 1 is the overall schematic diagram of the AHB architecture GaN packaging structure of the SOP16 packaging 10-pin combined sealing power supply chip.

[0021] The figure mark: 1, GaN control main chip; 2, first power GaN tube chip; 3, second power GaN tube chip; 4, first base island; 5, second base island; 6, pin GND1; 7, pin CS; 8, pin VS; 9, pin FB; 10, pin VCC; 11, pin GND2; 12, pin XCD; 13, pin VCCH; 14, pin HB; 15, pin VIN. DETAILED DESCRIPTION

[0022] The technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The following text is only used to describe one AHB architecture GaN packaging structure of the SOP16 packaging 10-pin combined sealing power supply chip of the present application, and does not strictly limit the protection scope of the present application.

[0023] Embodiment: as shown in the figure, an AHB architecture GaN packaging structure of the SOP16 packaging 10-pin combined sealing power supply chip comprises: Figure 1

[0024] The first base island 4 is provided with the first power GaN tube chip 2, and the first base island 4 is bonded with the first power GaN control chip 2 through conductive glue;

[0025] The second base island 5 is provided with the GaN control main chip 1 and the second power GaN tube chip 3, and the second base island 5 is bonded with the second power GaN tube chip 1 and the first power GaN tube chip 2 through conductive glue;

[0026] ​The interface end includes input ends VIN, HB, VCCH, XCD, VCC, an output end CS, control ends VS, FB, and ground ends GND1 and GND2. The structure reduces 16 groups of pins to 10 groups of pins, wherein the first pin, the second pin and the third pin are combined as a pin GND16 for heat dissipation, the pin GND16 leads out the ground end GND1, the fourth pin leads out the output end CS as a pin CS7, the fifth pin leads out the control end VS as a pin VS8, the sixth pin leads out the control end FB as a pin FB9, the seventh pin leads out the input end VCC as a pin VCC10, the eighth pin leads out the ground end GND2 as a pin GND211, the ninth pin leads out the input end XCD as a pin XCD12, the tenth pin and the fourteenth pin are cancelled, the eleventh pin leads out the input end VCCH as a pin VCCH13, the twelfth pin and the thirteenth pin are combined as a pin HB14 leading out the input end CS and performing heat dissipation, and the fifteenth pin and the sixteenth pin are combined as a pin VIN15 leading out the input end VIN and performing heat dissipation. The pin is optimized to the maximum extent, which can meet the needs of high-power, high-efficiency and fast GaN drive control, save design area, and improve reliability.

[0027] In the embodiment, the first base island 4 leads out a pin VIN15, a pin HB14, a pin VCCH13 and a pin XCD12, and the second base island 5 leads out a pin GND16, a pin CS7, a pin VS8, a pin FB9, a pin VCC10 and a pin GND211.

[0028] In the embodiment, the GaN control main chip 1, the first power GaN tube chip 2 and the second power GaN tube chip 3 are arranged in a triangular shape.

[0029] In the embodiment, the first base island 4 and the second base island 5 isolate the input ends VIN, HB, VCCH, XCD, VCC, the output end CS and the control ends VS, FB through an insulating layer.

[0030] In the embodiment, the pin GND16, the pin GND211, the pin CS7, the pin VS8, the pin FB9, the pin VCC10 and the pin XCD12, the pin VCCH13, the pin HB14 and the pin VIN15 are symmetrically arranged on both sides of the packaging structure.

[0031] In the embodiment, a first gate G1, a first source S1 and a first drain D1 are arranged on the first power GaN tube chip 2, a second gate G2, a second source S2 and a second drain D2 are arranged on the second power GaN tube chip 3, and a control pin GTH and a control pin GTL are arranged on the GaN control main chip 1.

[0032] In the embodiment, the first gate G1 is connected to the control pin GTH, the first source S1 is connected to the pin HB14 of the package, the first drain D1 is connected to the pin VIN15 of the package, the second gate G2 is connected to the control pin GTL, the second source S2 is connected to the pin GND211 of the package, and the second drain D2 is connected to the pin HB14 of the package.

[0033] In the embodiment, the pin CS7, the pin VS8, the pin FB9, the pin VCC10, the pin GND16 and the pin GND211, the pin XCD12, the pin VCCH13 and the pin HB14 are respectively connected to the output end CS, the control end VS and FB, the input end VCC, the ground end GND1 and GND2, the input end XCD, VCCH and HB by wire bonding, the wire bonding point of the control pin GTH is connected to the first gate G1 point of the first power GaN tube core chip 2 by wire bonding, the wire bonding point of the control pin GTL is connected to the second gate G2 point of the second power GaN tube core chip 3 by wire bonding, and the wire diameter of the wire bonding is 1.1 mil.

[0034] In the embodiment, the first drain D1 of the first power GaN tube core chip is connected to the pin VIN15 by wire bonding, the first source S1 point of the first power GaN tube core chip is connected to the pin HB14 by wire bonding, the second drain D2 point of the second power GaN tube core chip is connected to the pin HB14 by wire bonding, and the second source S2 point of the second power GaN tube core chip is connected to the pin GND16 by wire bonding, and the wire diameter of the wire bonding is 1.1 mil.

[0035] In the embodiment, the back of the chip at the first base island 4 position and the second base island 5 position is exposed to copper skin, so that the chip can be directly welded on the PCB board in application, and excellent and balanced heat dissipation performance is ensured.

[0036] The embodiments of the utility model are described in detail above in combination with the drawings, but the utility model is not limited to the above-mentioned embodiments, and for the ordinary skilled in the art, after knowing the contents recorded in the utility model, under the premise of not departing from the principle of the utility model, a plurality of equivalent transformations and substitutions can be made, and these equivalent transformations and substitutions should be regarded as belonging to the protection scope of the utility model.

Claims

1. An AHB architecture GaN package structure for a 10-pin SOP16 packaged power supply chip, characterized in that: The application relates to a GaN power module structure. The first base island is bonded with the first power GaN tube core piece through conductive glue. The interface end comprises input ends VIN, HB, VCCH, XCD, VCC, output ends CS, control ends VS, FB and ground ends GND1 and GND2. The first, second and third pins are combined as a pin GND1 for heat dissipation.

2. The AHB architecture GaN packaging structure of a SOP 16 package 10-pin combined power supply chip according to claim 1, characterized in that: The fourth pin is taken as a pin CS to lead out the output end CS.

3. The AHB architecture GaN packaging structure of a SOP 16 package 10-pin combined package power supply chip according to claim 1, characterized in that: The fifth pin is taken as a pin VS to lead out the control end VS.

4. The AHB architecture GaN packaging structure of a SOP 16 package 10-pin combined power supply chip according to claim 1, characterized in that: The sixth pin is taken as a pin FB to lead out the control end FB.

5. The AHB architecture GaN packaging structure of a SOP 16 package 10-pin combined power supply chip according to claim 1, characterized in that: The seventh pin is taken as a pin VCC to lead out the input end VCC.

6. The AHB architecture GaN package structure of a SOP 16 package 10-pin combined package power supply chip according to claim 5, characterized in that: The eighth pin is taken as a pin GND2 to lead out the ground end GND2.

7. The AHB architecture GaN package structure of a SOP 16 package 10-pin combined package power supply chip according to claim 6, characterized in that: The ninth pin is taken as a pin XCD to lead out the input end XCD. The tenth and fourteenth pins are cancelled. The eleventh pin is taken as a pin VCCH to lead out the input end VCCH. The twelfth and thirteenth pins are combined as a pin HB to lead out the input end CS. The fifteenth and sixteenth pins are combined as a pin VIN to lead out the input end VIN. The first base island leads out the pins VIN, HB, VCCH and XCD. The second base island leads out the pins GND1, CS, VS, FB, VCC and GND2. The GaN control main chip, the first power GaN tube core piece and the second power GaN tube core piece are arranged in a triangular shape. The first base island and the second base island are isolated from the input ends VIN, HB, VCCH, XCD, VCC, the output ends CS and the control ends VS and FB through an insulating layer. The pins GND1, GND2, CS, VS, FB, VCC are symmetrically arranged on both sides of the packaging structure with the pins XCD, VCCH, HB and VIN. The first power GaN tube core piece is provided with a first gate G1, a first source S1 and a first drain D1. The second power GaN tube core piece is provided with a second gate G2, a second source S2 and a second drain D2. The GaN control main chip is provided with a control pin GTH and a control pin GTL. The first gate G1 is connected with the control pin GTH. The first source S1 is connected with the pin HB of the package. The first drain D1 is connected with the pin VIN of the package. The second gate G2 is connected with the control pin GTL. The second source S2 is connected with the pin GND2 of the package. The second drain D2 is connected with the pin HB of the package.

8. The AHB architecture GaN package structure of a SOP 16 package 10-pin combined package power supply chip according to claim 6, characterized in that: The pin CS, pin VS, pin FB, pin VCC, pin GND1 and pin GND2, pin XCD, pin VCCH and pin HB are respectively connected with the output terminal CS, control terminal VS and FB, input terminal VCC, ground terminal GND1 and GND2, input terminal XCD, VCCH and HB by wire bonding, the wire bonding point of the control pin GTH is connected with the first gate G1 point of the first power GaN tube chip by wire bonding, and the wire bonding point of the control pin GTL is connected with the second gate G2 point of the second power GaN tube chip by wire bonding.

9. The AHB architecture GaN package structure of a SOP 16 package 10-pin combined package power supply chip according to claim 6, characterized in that: The first drain D1 of the first power GaN tube chip is connected with the pin VIN by wire bonding, the first source S1 point of the first power GaN tube chip is connected with the pin HB by wire bonding, the second drain D2 point of the second power GaN tube chip is connected with the pin HB by wire bonding, and the second source S2 point of the second power GaN tube chip is connected with the pin GND1 by wire bonding.

10. The AHB architecture GaN package structure of a SOP 16 package 10-pin combined package power supply chip according to claim 1, characterized in that: The chip back of the first base island position and the second base island position is exposed copper skin.

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