Integrated chip

Abstract

The embodiment of the utility model provides an integrated chip comprising an isolation structure extending into the front side surface of a substrate. The isolation structure laterally surrounds the first device region of the substrate. The isolation structure includes a pair of isolation edges elongated in a first direction and at least partially defining a first device region. A pair of source / drain regions are disposed within the first device region and laterally spaced apart from each other in the first direction. A first gate electrode structure is disposed in the first device region between the pair of source / drain regions. The first gate electrode structure includes a first pair of opposing sidewalls elongated in a first direction. The opposing sidewalls are laterally offset by a non-zero distance from a corresponding one of the pair of isolation edges in a direction toward a center of the first gate electrode structure. This non-zero distance reduces the lateral footprint of the transistor, maintains the area of the device region, and increases the device density of the integrated chip.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to an integrated chip, and more particularly, to an integrated chip including a gate electrode structure of a medium voltage device. BACKGROUND

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate, such as silicon. Depending on the application of the integrated chip, different types of semiconductor devices are used by the integrated chip. The integrated chip can have devices operating at different voltage levels and can include high voltage devices, medium voltage devices, and low voltage devices integrated on one chip. This facilitates the integrated chip to perform various circuit functions, such as memory buffer, logic processing, source driver, gate driver, etc. SUMMARY

[0003] Embodiments of the present application provide an integrated chip including an isolation structure, a pair of source / drain regions, and a first gate electrode structure. The isolation structure extends into a front side surface of a substrate, wherein the isolation structure laterally surrounds a first device region of the substrate, wherein the isolation structure includes a first pair of isolation edges elongated in a first direction and at least partially defining the first device region. The pair of source / drain regions is disposed within the first device region and laterally spaced apart from each other in the first direction. The first gate electrode structure is disposed in the first device region and spaced between the pair of source / drain regions, wherein the first gate electrode structure includes a first pair of opposing sidewalls elongated in the first direction, wherein the first pair of opposing sidewalls is laterally offset from a corresponding isolation edge of the first pair of isolation edges by a non-zero distance in a direction toward a center of the first gate electrode structure.

[0004] The embodiment of the utility model provides a kind of integrated chip including semiconductor substrate, shallow trench isolation structure, first transistor and second transistor.Semiconductor substrate has with the first device area that second device area is laterally adjacent, shallow trench isolation structure extends into the front side surface of the semiconductor substrate, wherein the shallow trench isolation structure includes first pair of isolation edges and second pair of isolation edges, the first pair of isolation edges is elongated in first direction and at least partially divides the first device area, the second pair of isolation edges is elongated in the first direction and at least partially divides the second device area.First transistor is arranged in the first device area, wherein the first transistor includes first gate electrode structure and first pair of source / drain regions arranged on the opposite side of the first gate electrode structure, wherein the first gate electrode structure is elongated in second direction orthogonal to the first direction and directly overlaid on the first pair of isolation edges.Second transistor is arranged in the second device area, wherein the second transistor includes second gate electrode structure and second pair of source / drain regions arranged on the opposite side of the second gate electrode structure, wherein the second gate electrode structure includes a pair of opposite sidewalls elongated in the first direction, wherein the pair of opposite sidewalls of the second gate electrode structure is spaced between the second pair of isolation edges.

[0005] Based on the above, the embodiment of the utility model provides some embodiments of integrated chip with transistor, transistor includes gate electrode structure configured to low noise and increase the reliability of transistor.The opposite sidewall of the gate electrode structure of integrated chip is spaced between a pair of isolation edges, so that the opposite sidewall extending in first direction is not directly overlaid on shallow trench isolation structure.Due to the spacing of opposite sidewall and isolation edge, therefore reduce the noise in transistor, reduce the negative influence brought by reduced gate oxide integrity at the interface between shallow trench isolation structure and device area and alleviate or eliminate the bulging of gate electrode structure at the interface.In addition, the spacing of opposite sidewall of gate electrode structure reduces the lateral occupation area of transistor and maintains the area of device area at the same time.This increases the device density of integrated chip.

[0006] In order to make the above features and advantages of the embodiment of the utility model more obvious and easy to understand, the following embodiment is specifically described as follows with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIGS. 1A-1C Various views of integrated chip including transistor with gate electrode structure spaced between isolation edges of shallow trench isolation (STI) structure are shown.

[0008] FIGS. 2A-2C And FIGS. 3A-3C Various views of integrated chip including transistor with gate electrode structure spaced between isolation edges of shallow trench isolation (STI) structure are shown. FIGS. 1A-1Cvarious views of some other embodiments of the integrated chip.

[0009] FIG. 4A and 4B shows FIGS. 1A-1C top views of some other embodiments of the integrated chip.

[0010] FIGS. 5A-5C shows various views of some embodiments of the integrated chip including a low voltage (LV) region, a medium voltage (MV) region, and a high voltage (HV) region.

[0011] FIG. 6A and 6B shows FIGS. 5A-5C cross-sectional views of some other embodiments of the integrated chip.

[0012] FIG. 7 shows FIG. 6A and 6B cross-sectional views of some other embodiments of the integrated chip.

[0013] FIGS. 8A-20 shows various views of some embodiments of a method of forming a transistor having gate electrode structures spaced apart between isolation edges of STI structures.

[0014] FIG. 21 shows a method of some embodiments of a method of forming a transistor having gate electrode structures spaced apart between isolation edges of STI structures in the form of a flowchart.

[0015] BRIEF DESCRIPTION OF DRAWINGS

[0016] 100a, 100b, 200a, 200b, 300a, 300b, 500a, 500b, 600a, 600b, 700, 800a, 900, 900-1300, 1000, 1100, 1200, 1300, 1400a, 1500, 1600, 1700, 1800a, 1800b, 1900, 2000: cross-sectional view; 100c, 200c, 300c, 400a, 400b, 500c, 800b, 1400b, 1800c: top view; 102: substrate; 102f: front side surface; 104: shallow trench isolation structure / STI structure; 104a: isolation segment; 104el, 104e2, 530a, 532a: isolation edge; 105: transistor; 106: source / drain region; 108: gate dielectric structure; 110: gate electrode structure; 111: selectively conductive channel region; 112: sidewall spacer structure; 114: lightly doped region; 116: well region; 118: dielectric structure; 120: conductive contact; 120a: first conductive contact; 122: distance; 124a: first pair of opposing sidewalls / first sidewall; 124b: first pair of opposing sidewalls / second sidewall; 126a, 126b: second pair of opposing sidewalls; 130, 132, 134: length; 131, 206, 208: width; 202: body region; 204: protrusion; 302: drain region; 304: source region; 502a: low voltage region; 502b: medium voltage region; 502c: high voltage region; 503, 507: height; 504: low voltage transistor / transistor; 506: low voltage source / drain region / source / drain region; 508: low voltage lightly doped region; 509, 511: thickness; 510: low voltage gate electrode structure; 512: low voltage gate dielectric layer; 514: low voltage well region; 516: high voltage transistor / transistor; 518: high voltage source / drain region / source / drain region; 520: second high voltage well region; 522: high voltage gate electrode structure; 524: high voltage gate dielectric structure; 526: first high voltage well region; 602: second gate electrode layer; 603: upper gate dielectric layer; 604: first gate electrode layer; 606: first sidewall spacer layer; 608: second sidewall spacer layer; 702: first dielectric layer; 704: second dielectric layer; 706: gate electrode cap layer; 708: dummy fin structure; 1102: opening; 1402a: first sacrificial gate electrode structure / sacrificial gate electrode structure; 1402b: second sacrificial gate electrode structure / sacrificial gate electrode structure; 1402c: third sacrificial gate electrode structure / sacrificial gate electrode structure; 1404, 1406: opposing sidewalls; 2002: third dielectric layer; 2004: conductive metal line; 2100: method; 2102, 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118: acts; A-A', B-B': line; x, y, z: axis. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0018] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0019] An integrated chip can include multiple devices operating at different voltage levels, which can be used in a variety of applications. An integrated chip can include low-voltage (LV) devices (e.g., for memory or processing interfaces), medium-voltage (MV) devices (e.g., for source drivers), and high-voltage (HV) devices (e.g., for gate drivers) disposed on the same die. Medium-voltage devices can occupy a large area of ​​the die (e.g., about 70% or more) to support critical chip functions such as source drivers, digital-to-analog converters (DACs), etc.

[0020] A medium voltage device of an integrated chip is disposed on a semiconductor substrate of the integrated chip. A shallow trench isolation (STI) structure is disposed in the semiconductor substrate and includes isolation edges that divide a device region of the semiconductor substrate for the medium voltage device. The medium voltage device includes a gate dielectric structure recessed in the semiconductor substrate, a gate electrode structure over the gate dielectric structure, and a pair of source / drain regions disposed on opposite sides of the gate electrode structure. A selectively-conductive channel of the medium voltage device is disposed in the device region under the gate electrode structure and extends in a first direction between the pair of source / drain regions. The gate electrode structure extends over a first pair of the isolation edges of the STI structure elongated along the first direction.

[0021] The above challenges of the integrated chip include a large area occupied by the medium voltage device on the die and performance (e.g., noise, reliability, etc.) of the medium voltage device. For example, charge carriers can be trapped at an interface between the first pair of isolation edges and the device region due to defects at the interface. Since the gate electrode structure extends over the first pair of isolation edges, these trapped charge carriers cause noise in the medium voltage device. Further, after the STI structure is formed, the gate dielectric structure is grown in a recess formed in the device region of the semiconductor substrate. Growth (e.g., by thermal oxidation) of the gate dielectric structure along or near the first pair of isolation edges is reduced compared to growth of the gate dielectric structure in a recessed region away from the STI structure. This reduces gate oxide integrity (GOI) of the medium voltage device and causes one or more humps in the gate electrode structure at the first pair of isolation edges, which reduces device reliability and / or can cause delamination of the gate electrode structure. Further, to reduce the large area occupied by the medium voltage device, the device region of each medium voltage device can be scaled down. However, scaling down the device region of each medium voltage device can reduce gate breakdown voltage of the medium voltage device, increase leakage current, and / or reduce reliability.

[0022] Accordingly, some embodiments of integrated chips having transistors including gate electrode structures configured to reduce noise and increase reliability of the transistors are provided. An integrated chip includes an STI structure disposed in a substrate and dividing a device region. A transistor is disposed in the device region and includes a gate electrode structure overlying a gate dielectric structure and a pair of source / drain regions disposed in the device region on opposite sides of the gate electrode structure. The pair of source / drain regions are spaced apart from each other in a first direction. A first pair of isolation edges of the STI structure are elongated in the first direction. The gate electrode structure includes a first pair of opposing sidewalls elongated in the first direction. The first pair of opposing sidewalls of the gate electrode structure are spaced apart from each other between the first pair of isolation edges such that the first pair of opposing sidewalls elongated in the first direction do not directly overlie the STI structure. Due to the spacing of the first pair of opposing sidewalls from the first pair of isolation edges, noise in the transistor (e.g., due to trapped charge carriers at the interface between the STI structure and the device region) is reduced, negative effects of reduced GOI at the interface between the STI structure and the device region are reduced, and one or more protrusions of the gate electrode structure at the interface are mitigated or eliminated. In addition, the spacing of the first pair of opposing sidewalls of the gate electrode structure reduces the lateral footprint of the transistor while maintaining the area of the device region. This increases the device density of the integrated chip.

[0023] FIGS. 1A-1C Various views of an integrated chip including a transistor 105 having a gate electrode structure 110 spaced apart between isolation edges (104el, 104e2) of a shallow trench isolation (STI) structure 104 are shown. FIG. 1A A cross-sectional view 100a of some embodiments of the integrated chip taken along line A-A’ of FIG. 1C is shown. FIG. 1B A cross-sectional view 100b of some embodiments of the integrated chip taken along line B-B’ of FIG. 1C is shown. FIG. 1C A top view 100c of some embodiments of the integrated chip is shown, where, for ease of illustration, FIG. 1C the dielectric structure 118 in FIG. 1A and FIG. 1B is omitted.

[0024] The integrated chip includes an STI structure 104 that extends into a front side surface 102f of the substrate 102. The STI structure 104 partitions a device region of the substrate 102. A transistor 105 is disposed on the substrate 102 and laterally spaced within the device region. The transistor 105 includes a gate dielectric structure 108 recessed into the substrate 102, a gate electrode structure 110 over the gate dielectric structure 108, a sidewall spacer structure 112 disposed around the gate electrode structure 110, and a pair of source / drain regions 106 disposed in the substrate 102. One or more source / drain regions can refer to either a source or a drain, alone or collectively, depending on the contact. A well region 116 is disposed within the substrate 102 and under the transistor 105. The well region 116 includes a first doping type (e.g., p-type). The source / drain regions 106 are spaced apart from each other in a first direction (e.g., along an x-axis). The source / drain regions 106 include a second doping type (e.g., n-type) opposite the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. Further, a lightly doped region 114 is disposed within the substrate 102 and contiguous to a corresponding source / drain region of the pair of source / drain regions 106. The lightly doped region 114 includes the second doping type (e.g., n-type) with a lower doping concentration relative to the source / drain regions 106.

[0025] In some embodiments, the gate dielectric structure 108 extends from a lower surface of the substrate 102 to the front side surface 102f of the substrate 102. The gate dielectric structure 108 extends continuously laterally between the pair of source / drain regions 106 along the first direction. A dielectric structure 118 overlies the substrate 102. A plurality of conductive contacts 120 are disposed within the dielectric structure 118. The conductive contacts 120 facilitate electrical connections with the transistor 105. Upon receiving a bias, the gate electrode structure 110 is configured to generate an electric field that controls movement of charge carriers within a selectively conductive channel region 111 directly below the gate electrode structure 110. The selectively conductive channel region 111 extends between the source / drain regions 106 along the first direction.

[0026] Referring to FIG. 1B and FIG. 1CThe gate electrode structure 110 includes a first pair of opposing sidewalls (124a, 124b) elongated in a first direction (e.g., along the x-axis) and a second pair of opposing sidewalls (126a, 126b) elongated in a second direction (e.g., along the y-axis) orthogonal to the first direction. The second pair of opposing sidewalls (126a, 126b) extends continuously between the first pair of opposing sidewalls (124a, 124b). Further, the source / drain regions 106 are adjacent to corresponding sidewalls of the second pair of opposing sidewalls (126a, 126b). The STI structure 104 includes a pair of isolation edges (104el, 104e2) elongated in the first direction (e.g., along the x-axis) that at least partially divide the device region. In various embodiments, when viewed in a top-down view (e.g., as seen in FIG. 1 IB), the isolation edges (104el, 104e2) are linear and extend laterally in parallel with the first pair of opposing sidewalls (124a, 124b). In some embodiments, the isolation edges (104el, 104e2) are on opposite sides of the device region and have the same or substantially the same length. Further, the source / drain regions 106 each extend continuously laterally between the isolation edges (104el, 104e2) along the second direction (e.g., along the y-axis). The first pair of opposing sidewalls (124a, 124b) of the gate electrode structure 110 are laterally spaced apart between the isolation edges (104el, 104e2). In some embodiments, the first pair of opposing sidewalls (124a, 124b) are laterally offset from the isolation edges (104el, 104e2) by a non-zero distance 122. FIG. 1C

[0027] ​By spacing the gate electrode structure 110 away from the isolation edges (104el, 104e2), noise of the transistor 105 is reduced. For example, the spacing mitigates the contribution of trapped charge carriers at the interface between the STI structure 104 and the device region of the substrate 102 to the current flowing through the selectively conductive channel region 111, thereby reducing noise (e.g., reducing flicker noise). Furthermore, due to the presence of the STI structure 104 and a selective growth process (e.g., a local oxidation of silicon (LOCOS) process), proper growth of the gate dielectric structure 108 adjacent to the isolation edges (104el, 104e2) can be hindered. Spacing the gate electrode structure 110 away from the isolation edges (104el, 104e2) mitigates the negative effects of reduced GOI of the gate dielectric structure 108 at the interface and mitigates the presence of one or more bumps in the gate electrode structure 110, thereby mitigating delamination of the gate electrode structure 110 and increasing the reliability of the transistor 105. Furthermore, the spacing facilitates reducing the size of the gate electrode structure 110 and reducing the lateral footprint of the transistor 105. Thus, spacing the gate electrode structure 110 away from the isolation edges (104el, 104e2) increases the device density and overall performance of the integrated chip.

[0028] Referring to FIG. 1C The length 130 of the gate electrode structure 110 is less than the length 132 of the pair of source / drain regions 106. Furthermore, the length 134 of the gate dielectric structure 108 is greater than the length 130 of the gate electrode structure 110. In further embodiments, the width 131 of the gate electrode structure 110 is greater than the length 130 of the gate electrode structure 110. In some embodiments, the length 134 in the gate dielectric structure 108 is equal to the length 132 of the pair of source / drain regions 106. In some embodiments, the distance 122 is, for example, in the range of about 0.01 to 0.1 micrometers (pm) or some other suitable value. In various embodiments, a distance 122 greater than 0.01 pm facilitates reducing noise and negative effects from reduced GOI of the gate dielectric structure 108 at the isolation edges (104el, 104e2). In further embodiments, a distance 122 less than 0.1 pm facilitates reducing noise and negative effects from reduced GOI of the gate dielectric structure 108 while maintaining sufficient size of the gate electrode structure 110 over the device region of the transistor 105. This facilitates the gate electrode structure 110 to generate a control voltage for the selectively conductive channel region (e.g., the channel region 111) of the transistor 105, as well as to mitigate delamination of the gate electrode structure 110 and increase the reliability of the transistor 105. FIG. 1AThe electric field that drives the movement of charge carriers within the STI structure 104. In a further embodiment, the gate electrode structure 110 is completely laterally offset from the STI structure 104. In yet another embodiment, the gate electrode structure 110 does not directly cover any segment of the STI structure 104.

[0029] In some embodiments, the STI structure 104 may be, for example, or include silicon dioxide, silicon nitride, silicon oxynitride, some other dielectric materials, or any combination thereof. The gate dielectric structure 108 may be, for example, or include silicon dioxide, one or more high-dielectric-constant dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.), some other dielectric materials, or any combination thereof. As used herein, a high-dielectric-constant dielectric material is a dielectric material with a dielectric constant greater than 3.9. The gate electrode structure 110 may be, for example, or include polysilicon, doped polysilicon, one or more metal materials (such as one or more of tungsten, titanium, tantalum, aluminum, etc.), metal nitrides (such as titanium nitride, tantalum nitride, etc.), or any combination thereof. The substrate 102 may be, for example, or include silicon, germanium, silicon-germanium, epitaxial silicon, some other semiconductor materials, or the like. The transistor 105 may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0030] FIGS. 2A-2C It shows FIGS. 1A-1C Various views of some other embodiments of the integrated chip. FIG. 2A It shows along FIG. 2C A cross-sectional view 200a of some embodiments of the integrated chip, taken by line A-A'. FIG. 2B It shows along FIG. 2C A cross-sectional view 200b of some embodiments of the integrated chip, taken by line B-B'. FIG. 2C A top view 200c of some embodiments of the integrated chip is shown, wherein, for ease of illustration, FIG. 2C The middle part is omitted FIG. 2A and FIG. 2B Dielectric structure 118 in it.

[0031] Reference FIG. 2B and FIG. 2CThe first pair of opposing sidewalls (124a, 124b) of the gate electrode structure 110 includes a first sidewall 124a and a second sidewall 124b. In some embodiments, the gate electrode structure 110 includes a body region 202 and a protrusion 204. The body region 202 is defined between the first sidewall 124a and the second sidewall 124b. The protrusion 204 extends from the second sidewall 124b to a point above the STI structure 104. In some embodiments, the protrusion 204 directly overlies the STI structure 104. In various embodiments, the first conductive contact 120a directly overlies the protrusion 204 of the gate electrode structure 110 and is electrically coupled to the gate electrode structure 110. In further embodiments, a width 206 of the body region 202 is greater than a width 208 of the protrusion 204. Having the first conductive contact 120a disposed over the protrusion 204 facilitates providing electrical connection to the gate electrode structure 110 in an area laterally offset from a device region of the transistor 105. Thus, issues related to misalignment of the first conductive contact 120a over the gate electrode structure 110 (e.g., the first conductive contact 120a landing on the source / drain region 106 and / or other regions of the substrate 102) can be mitigated. This partially improves the overall performance of the transistor 105.

[0032] FIGS. 3A-3C Various views of some other embodiments of the integrated chip are shown. FIGS. 2A-2C Various views of some other embodiments of the integrated chip are shown. FIG. 3A Cross-sectional views 300a of some embodiments of the integrated chip taken along line A-A’ of FIG. 3C Cross-sectional views 300b of some embodiments of the integrated chip taken along line B-B’ of FIG. 3B Cross-sectional views 300b of some embodiments of the integrated chip taken along line B-B’ of FIG. 3C Cross-sectional views 300b of some embodiments of the integrated chip taken along line B-B’ of FIG. 3C Cross-sectional views 300b of some embodiments of the integrated chip taken along line B-B’ of FIG. 2C The dielectric structure 118 in FIG. 3A and FIG. 3B The dielectric structure 118 in

[0033] In some embodiments, the transistor 105 includes a drain region 302 and a source region 304 disposed within the substrate 102. In various embodiments, the body region 202 of the gate electrode structure 110 is annular and laterally surrounds the source region 304. Further, the drain region 302 is disposed on opposite sides of the gate electrode structure 110. In some embodiments, the drain region 302 includes two separate doped regions of the substrate 102 spaced apart from each other in a first direction (e.g., along the x-axis). In yet another embodiment, the drain region 302 is annular and extends around an outer periphery (not shown) of the body region 202 of the gate electrode structure 110.

[0034] FIG. 4A Various views of some other embodiments of the integrated chip are shown. FIGS. 1A-1CA top view 400a of some other embodiments of the integrated chip, wherein a plurality of conductive contacts 120 overlying the gate electrode structure 110 are spaced apart from each other along a line extending in a first direction (e.g., along the x-axis).

[0035] FIG. 4B It shows FIGS. 1A-1C A top view 400b of some other embodiments of the integrated chip, wherein a plurality of conductive contacts 120 overlying the gate electrode structure 110 are spaced apart from each other along a line extending in a second direction (e.g., along the y-axis).

[0036] FIGS. 5A-5C Various views of some embodiments of an integrated chip are shown, the integrated chip including a low voltage (LV) region 502a, a medium voltage (MV) region 502b and a high voltage (HV) region 502c. FIG. 5A It shows along FIG. 5C A cross-sectional view 500a of some embodiments of an integrated chip, taken by a line extending along the x-axis. FIG. 5B It shows along FIG. 5C A cross-sectional view 500b of some embodiments of the integrated chip, taken by lines extending along the y-axis in each region (502a, 502b, 502c). FIG. 5C A top view 500c of some embodiments of the integrated chip is shown, wherein, for ease of illustration, FIG. 5C The middle part is omitted FIG. 5A and FIG. 5B Dielectric structure 118 in it.

[0037] The integrated chip includes a low-voltage transistor 504 disposed in a low-voltage region 502a, a transistor 105 disposed in a medium-voltage region 502b, and a high-voltage transistor 516 disposed in a high-voltage region 502c. In some embodiments, transistor 105 may be referred to as a medium-voltage transistor. In various embodiments, low-voltage transistor 504 is configured to operate at a voltage in the range of about 0.7 to 1 volt (V), transistor 105 is configured to operate at a voltage in the range of about 6 to 10 V, and high-voltage transistor 516 is configured to operate at a voltage in the range of about 25 to 32 V or greater. It should be understood that the aforementioned voltage ranges of the transistors (504, 105, 516) in regions (502a, 502b, 502c) are merely non-limiting examples, and transistors operating at other voltage values ​​(e.g., 504, 105, 516) are also within the scope of this disclosure. Furthermore, although each of the regions (502a, 502b, 502c) depicts a single device, it should be understood that this is merely a non-limiting example and each of the regions (502a, 502b, 502c) may have any number of devices.

[0038] In some embodiments, the low voltage transistor 504 includes a low voltage well region 514, a low voltage gate dielectric layer 512, a low voltage gate electrode structure 510, a pair of low voltage lightly doped regions 508, and a pair of low voltage source / drain regions 506. A first portion of the STI structure 104 is disposed within and divides a first device region for the low voltage transistor 504 in the low voltage region 502a. The low voltage well region 514 is disposed within the substrate 102 and includes a first dopant type (e.g., p-type). The low voltage gate electrode structure 510 overlies the substrate 102, and the low voltage gate dielectric layer 512 is spaced between the low voltage gate electrode structure 510 and the substrate 102. The pair of low voltage source / drain regions 506 are disposed in the substrate 102 on opposite sides of the low voltage gate electrode structure 510. The pair of low voltage lightly doped regions 508 abut the pair of low voltage source / drain regions 506. In various embodiments, the low voltage source / drain regions 506 and the low voltage lightly doped regions 508 are doped regions of the substrate 102 and include a second dopant type (e.g., n-type). The low voltage source / drain regions 506 have a greater dopant concentration than the low voltage lightly doped regions 508.

[0039] In some embodiments, the height 503 of the STI structure 104 in the low voltage region 502a is approximately 1,250 Angstroms, is in a range of approximately 1,150 to 1,350 Angstroms, or some other suitable value. In various embodiments, the low voltage gate dielectric layer 512 has a thickness of approximately 10 Angstroms, is in a range of approximately 5 to 15 Angstroms, or some other suitable value. The low voltage gate dielectric layer 512 may, for example, be or include silicon dioxide, one or more high dielectric constant dielectric materials (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.), or the like. The low voltage gate electrode structure 510 may, for example, be or include polysilicon, doped polysilicon, one or more metallic materials (e.g., one or more of tungsten, titanium, tantalum, aluminum, etc.), metallic nitrides (e.g., titanium nitride, tantalum nitride, etc.), or the like.

[0040] The transistor 105 is disposed within the medium voltage region 502b. The transistor 105 includes a well region 116, a gate dielectric structure 108, a gate electrode structure 110, a pair of lightly doped regions 114, and a pair of source / drain regions 106. It should be understood that while the transistor 105 is configured as shown and / or described in FIGS. 1A-1C the medium voltage region 502b, the transistor 105 may, for example, be configured as shown and / or described in FIGS. 2A-2C , FIGS. 3A-3C , FIG. 4A or FIG. 4BThe second portion of the STI structure 104 is disposed within and divides a second device region of the transistor 105 in the medium voltage region 502b. The second portion of the STI structure 104 includes a pair of isolation edges (104el, 104e2) extending in the first direction (e.g., x-axis) that at least partially bound the second device region. In some embodiments, a height 507 of the STI structure 104 in the medium voltage region 502b is approximately 2,500 Angstroms, in a range of approximately 2,000 to 3,000 Angstroms, or some other suitable value. In further embodiments, a thickness 509 of the gate dielectric structure 108 is approximately 200 Angstroms, in a range of approximately 150 to 250 Angstroms, or some other suitable value.

[0041] In some embodiments, the high voltage transistor 516 includes a first high voltage well region 526, a second high voltage well region 520, a high voltage gate dielectric structure 524, a high voltage gate electrode structure 522, and a pair of high voltage source / drain regions 518. A third portion of the STI structure 104 is disposed within and divides a third device region of the high voltage transistor 516 in the high voltage region 502c. The first high voltage well region 526 and the second high voltage well region 520 are disposed within the substrate 102. The first high voltage well region 526 includes a first doping type (e.g., p-type) and the second high voltage well region 520 includes a second doping type (e.g., n-type). The high voltage gate dielectric structure 524 is recessed into the substrate 102. The high voltage gate electrode structure 522 overlies the high voltage gate dielectric structure 524. The pair of high voltage source / drain regions 518 are disposed in the substrate 102 on opposite sides of the high voltage gate electrode structure 522. The pair of high voltage source / drain regions 518 include the second doping type (e.g., n-type).

[0042] In some embodiments, the thickness 511 of the high-voltage gate dielectric structure 524 is about 900 Angstroms, within a range of about 800 to 1,000 Angstroms, or some other suitable value. In various embodiments, the thickness 509 of the gate dielectric structure 108 is less than the thickness 511 of the high-voltage gate dielectric structure 524. The high-voltage gate dielectric structure 524 can be, for example, or include, silicon dioxide, one or more high-k dielectric materials (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.), or the like. The high-voltage gate electrode structure 522 can be, for example, or include, polysilicon, doped polysilicon, one or more metallic materials (e.g., one or more of tungsten, titanium, tantalum, aluminum, etc.), metallic nitrides (e.g., titanium nitride, tantalum nitride, etc.), or the like. In various embodiments, the high-voltage gate dielectric structure 524 and the gate dielectric structure 108 include a first dielectric material (e.g., silicon dioxide) and the low-voltage gate dielectric layer 512 includes a second dielectric material (e.g., a high-k dielectric material) that is different than the first dielectric material. In some embodiments, the low-voltage gate electrode structure 510, the gate electrode structure 110, and the high-voltage gate electrode structure 522 include the same conductive material (e.g., tungsten, titanium, tantalum, aluminum, titanium nitride, tantalum nitride, etc.). The sidewall spacer structure 112 is disposed around the sidewalls of the low-voltage gate electrode structure 510, the gate electrode structure 110, and the high-voltage gate electrode structure 522. The sidewall spacer structure 112 can be, for example, or include, silicon dioxide, silicon nitride, or the like. In various embodiments, each of the low-voltage transistor 504, the transistor 105, and the high-voltage transistor 516 is configured as a planar transistor, e.g., a MOSFET.

[0043] Referring to FIG. 5B and FIG. 5C The low-voltage gate electrode structure 510 directly overlies a first pair of isolation edges (530a, 530b) of the STI structure 104 in the low-voltage region 502a. The high-voltage gate electrode structure 522 directly overlies a second pair of isolation edges (532a, 532b) of the STI structure 104 in the high-voltage region 502c. Further, the gate electrode structure 110 is spaced apart from a pair of isolation edges (104el, 104e2) of the STI structure 104 in the medium-voltage region 502b by a distance 122. Spacing the gate electrode structure 110 from the pair of isolation edges (104el, 104e2) reduces noise in the transistor 105, mitigates negative effects of reduced GOI of the gate dielectric structure 108 near the isolation edges (104el, 104e2), and mitigates one or more bumps in the gate electrode structure 110. Further, the spacing facilitates reducing a lateral footprint of the transistor 105, thereby reducing an overall size of the medium-voltage region 502b above the substrate 102. This increases space for other devices disposed above the substrate 102, thereby increasing a device density of the integrated chip.

[0044] FIG. 6A and6B Cross-sectional views 600a and 600b of some other embodiments of the integrated chip corresponding to FIGS. 5A-5C FIG. 6A Cross-sectional view 600a of the integrated chip corresponding to FIG. 5A FIG. 6B Cross-sectional view 600b of the integrated chip corresponding to FIG. 5B

[0045] In some embodiments, the top surfaces of the gate dielectric structure 108 and the high-voltage gate dielectric structure 524 are vertically offset from the front-side surface 102f of the substrate 102. An upper gate dielectric layer 603 is disposed along the top surfaces of the gate dielectric structure 108 and the high-voltage gate dielectric structure 524. In some embodiments, the upper gate dielectric layer 603 comprises silicon dioxide, a high-k dielectric material, or the like. In some embodiments, the sidewall spacer structure 112 comprises a first sidewall spacer layer 606 comprising a first material (e.g., silicon nitride) and a second sidewall spacer layer 608 comprising a second material different from the first material (e.g., silicon dioxide). In various embodiments, the first sidewall spacer layer 606 has an L-shape when viewed from a cross-section. In some embodiments, the low-voltage gate electrode structure 510, the gate electrode structure 110, and the high-voltage gate electrode structure 522 each comprise a first gate electrode layer 604 and a second gate electrode layer 602. In some embodiments, the first gate electrode layer 604 comprises a high-k dielectric material (e.g., hafnium oxide) and the second gate electrode layer 602 comprises a conductive material (e.g., tungsten, titanium, tantalum, aluminum, titanium nitride, tantalum nitride, some other conductive material, or any combination of the foregoing). In various embodiments, the first gate electrode layer 604 is U-shaped and extends along the bottom surface and opposite sidewalls of the second gate electrode layer 602. In various embodiments, the upper gate dielectric layer 603 is omitted (not shown).

[0046] FIG. 7 Cross-sectional views 700 of some other embodiments of the integrated chip corresponding to FIG. 6A

[0047] ​​​​In various embodiments, the low voltage transistor 504 is configured as a fin field-effect transistor (FinFET) or a gate-all-around FET (GAAFET) and each of the transistor 105 and the high voltage transistor 516 is configured as a planar MOSFET. In such embodiments, the pair of low voltage source / drain regions 506 are doped epitaxial silicon structures disposed on opposite sides of a low voltage gate electrode structure 510. In some embodiments, the low voltage gate electrode structure 510 overlies a fin structure extending from a lower region of the substrate 102. Further, the substrate 102 includes a plurality of dummy fin structures 708 laterally spaced between the low voltage region 502a and the medium voltage region 502b and laterally spaced between the medium voltage region 502b and the high voltage region 502c. In some embodiments, the low voltage gate electrode structure 510, the gate electrode structure 110, and the high voltage gate electrode structure 522 include a gate electrode cap layer 706 overlying the second gate electrode layer 602, respectively. The gate electrode cap layer 706 may, for example, be or include a conductive material, such as a metallic material, a silicide, or the like. In various embodiments, the STI structure 104 includes an isolation section 104a directly beneath the high voltage gate dielectric structure 524 laterally disposed between the pair of high voltage source / drain regions 518. A first dielectric layer 702 overlies the substrate 102 and a second dielectric layer 704 overlies the first dielectric layer 702. The plurality of conductive contacts 120 are disposed within the first dielectric layer 702 and the second dielectric layer 704. The first dielectric layer 702 and the second dielectric layer 704 may, for example, be or include silicon dioxide, a low-k dielectric material, or some other suitable material. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant less than 3.9.

[0048] FIGS. 8A-20 Various views 800a-2000 of some embodiments of a method of a transistor having a gate electrode structure spaced apart between isolation edges of an STI structure are shown. While the method is described with reference to the various views 800a-2000, it is understood that FIGS. 8A-20 the various views 800a-2000 shown in FIGS. 8A-20 the structures shown in FIGS. 8A-20 are not limited to the method, but can be independent of the method. While are described as a series of acts, it is understood

[0049] that these acts are not limiting, as in other embodiments the order of the acts can be changed, and other intermediate acts can be employed. FIG. 8A FIG. 8B asAs shown in the top-down view 800b, the STI structure 104 is formed within the substrate 102. The substrate 102 can be, for example, or include silicon, germanium, silicon germanium, epitaxial silicon, silicon-on-insulator (SOI), some other semiconductor material, or the like. In some embodiments, forming the STI structure 104 includes forming a mask layer (not shown) over the substrate 102, etching (e.g., by plasma etching, reactive ion etching, etc.) the substrate 102 to form one or more isolation trenches extending into a front side surface 102f of the substrate 102, depositing (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) a dielectric material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, or the like) within the one or more isolation trenches, and performing a removal process to remove the mask layer. The substrate 102 includes the low pressure region 502a, the medium pressure region 502b, and the high pressure region 502c. The STI structure 104 partitions one or more device regions in the low pressure region 502a, the medium pressure region 502b, and the high pressure region 502c.

[0050] FIG. 8A A cross-sectional view 800a taken along a line extending along the x-axis of the top-down view 800b is shown. As shown in the cross-sectional view 800a, the substrate 102 includes a front side surface 102f and a back side surface 102b. The STI structure 104 is formed within the substrate 102. The substrate 102 can be, for example, or include silicon, germanium, silicon germanium, epitaxial silicon, silicon-on-insulator (SOI), some other semiconductor material, or the like. In some embodiments, forming the STI structure 104 includes forming a mask layer (not shown) over the substrate 102, etching (e.g., by plasma etching, reactive ion etching, etc.) the substrate 102 to form one or more isolation trenches extending into a front side surface 102f of the substrate 102, depositing (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) a dielectric material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, or the like) within the one or more isolation trenches, and performing a removal process to remove the mask layer. The substrate 102 includes the low pressure region 502a, the medium pressure region 502b, and the high pressure region 502c. The STI structure 104 partitions one or more device regions in the low pressure region 502a, the medium pressure region 502b, and the high pressure region 502c. FIG. 8B FIG. 8B As seen in the top-down view 800b, the STI structure 104 includes a pair of isolation edges (104el, 104e2) elongated in a first direction (e.g., along the x-axis). The pair of isolation edges (104el, 104e2) at least partially bounds a device region in the medium pressure region 502b.

[0051] As seen in the top-down view 800b, the STI structure 104 includes a pair of isolation edges (104el, 104e2) elongated in a first direction (e.g., along the x-axis). The pair of isolation edges (104el, 104e2) at least partially bounds a device region in the medium pressure region 502b. FIG. 9 ​As shown in cross-sectional view 900, a first high-voltage well region 526, a second high-voltage well region 520, and a high-voltage gate dielectric structure 524 are formed within the high-voltage region 502c. The first high-voltage well region 526 is formed, for example, by a first ion implantation process and includes a first doping type (e.g., p-type). The second high-voltage well region 520 is formed, for example, by a second ion implantation process and includes a second doping type opposite to the first doping type (e.g., n-type). In some embodiments, the first high-voltage well region 526 is formed before the second high-voltage well region 520. In various embodiments, forming the high-voltage gate dielectric structure 524 includes: forming a mask layer (not shown) over a substrate 102; etching (e.g., plasma etching, reactive ion etching, etc.) a portion of the STI structure 104 in the substrate 102 and the intermediate-voltage region 502c to form an opening extending into the front surface 102f of the substrate; depositing (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) a gate dielectric material (e.g., silicon dioxide, a high-dielectric-constant dielectric material, etc.) within the opening; and performing a removal process to remove the mask layer. In some embodiments, the high-voltage gate dielectric structure 524 is formed via a localized oxidation of silicon (LOCOS) process. In a further embodiment, the high-voltage gate dielectric structure 524 is formed after the formation of the first high-voltage well region 526 and the second high-voltage well region 520.

[0052] like FIG. 10 As shown in the cross-sectional view 1000, a well region 116 and a pair of lightly doped regions 114 are formed within a medium-pressure region 502b. The well region 116 is formed, for example, by a first ion implantation process and includes a first doping type (e.g., p-type). The pair of lightly doped regions 114 is formed, for example, by a second ion implantation process and includes a second doping type (e.g., n-type).

[0053] like FIG. 11 As shown in the cross-sectional view 1100, a patterning process is performed on the front surface 102f of the substrate to form an opening 1102 in the intermediate pressure region 502b. In some embodiments, the patterning process includes: forming a mask layer (not shown) over the substrate 102; etching the substrate 102 (e.g., by plasma etching, reactive ion etching, etc.) to form the opening; and performing a removal process to remove the mask layer.

[0054] like FIG. 12 As shown in the cross-sectional view 1200, a gate dielectric structure 108 is formed within the medium-voltage region 502b. In some embodiments, the gate dielectric structure 108 is formed in the opening ( ) by a CVD process, PVD process, ALD process, thermal oxidation process, or some other suitable growth or deposition process. FIG. 11 A gate dielectric structure 108 is formed within (1102). In various embodiments, the gate dielectric structure 108 is formed using a LOCOS process.

[0055] likeFIG. 13 As shown in cross-sectional view 1300, a low-pressure well region 514 and a pair of low-pressure lightly doped regions 508 are formed within the low-pressure region 502a. The low-pressure well region 514 is formed, for example, by a first ion implantation process and includes a first doping type (e.g., p-type). The pair of low-pressure lightly doped regions 508 is formed, for example, by a second ion implantation process and includes a second doping type (e.g., n-type).

[0056] like FIG. 14A Sectional view 1400a and FIG. 14B As shown in top view 1400b, a low-voltage gate dielectric layer 512, an upper gate dielectric layer 603, and a plurality of sacrificial gate electrode structures (e.g., 1402a, 1402b, 1402c) are formed over a substrate 102. In some embodiments, the plurality of sacrificial gate electrode structures (1402a, 1402b, 1402c) include a first sacrificial gate electrode structure 1402a on the low-voltage gate dielectric layer 512 in the low-voltage region 502a, a second sacrificial gate electrode structure 1402b on the upper gate dielectric layer 603 in the medium-voltage region 502b, and a third sacrificial gate electrode structure 1402c on the upper gate dielectric layer 603 in the high-voltage region 502c. In some embodiments, the process for forming a low-voltage gate dielectric layer 512, an upper gate dielectric layer 603, and a plurality of sacrificial gate electrode structures (1402a, 1402b, 1402c) includes: depositing (e.g., by CVD, PVD, ALD, etc.) a gate dielectric film (e.g., comprising silicon dioxide, a high-dielectric-constant dielectric material, or the like) over a substrate 102; depositing a sacrificial gate electrode layer (e.g., comprising polysilicon or some other suitable material) over the gate dielectric film; and performing one or more patterning processes on the gate dielectric film and the sacrificial gate electrode layer. In various embodiments, each of the low-voltage region 502a, the medium-voltage region 502b, and the high-voltage region 502c may be subjected to an individual patterning process. For example, a first patterning process can be performed on the low-voltage region 502a to form a low-voltage gate dielectric layer 512 and a first sacrificial gate electrode structure 1402a, and a second patterning process can be performed on the medium-voltage region 502b to form an upper gate dielectric layer 603 and a second sacrificial gate electrode structure 1402b, and so on. In another embodiment, the plurality of sacrificial gate electrode structures (1402a, 1402b, 1402c) can be formed simultaneously by a single patterning process.

[0057] FIG. 14A It shows along FIG. 14B The sectional view 1400a is intercepted by the line extending along the x-axis from the top view 1400b. (See also...) FIG. 14BAs seen in the top view 1400b, the second sacrificial gate electrode structure 1402b includes a first pair of opposing sidewalls (1404, 1406) extending in a first direction (e.g., along the x-axis). Each of the opposing sidewalls (1404, 1406) of the second sacrificial gate electrode structure 1402b is spaced apart from a corresponding one of the isolation edges (104e1, 104e2) by a distance 122. In various embodiments, the distance 122 is, for example, in the range of about 0.01 to 0.1 μm or some other suitable value. In some embodiments, the length of the second sacrificial gate electrode structure 1402b (e.g., defined along the y-axis) is less than the lateral distance between the isolation edges (104e1, 104e2).

[0058] like FIG. 15 As shown in cross-sectional view 1500, a sidewall spacer structure 112 is formed around the periphery of the sacrificial gate electrode structures (1402a, 1402b, 1402c). In some embodiments, the process for forming the sidewall spacer structure 112 includes: depositing (e.g., by CVD, PVD, ALD, etc.) one or more sidewall spacer layers over the substrate 102 and along the sidewalls of the sacrificial gate electrode structures (1402a, 1402b, 1402c) and performing an etching process (e.g., plasma etching, reactive ion etching, etc.) to remove one or more sidewall spacer layers from the side surface.

[0059] like FIG. 16 As shown in the cross-sectional view 1600, a pair of low-voltage source / drain regions 506 are formed in a low-voltage region 502a, a pair of source / drain regions 106 are formed in a medium-voltage region 502b, and a pair of high-voltage source / drain regions 518 are formed in a high-voltage region 502c. In some embodiments, the low-voltage source / drain regions 506, 106, and 518 are formed by one or more ion implantation processes. In some embodiments, an individual ion implantation process may be performed on each of the low-voltage, medium-voltage, and high-voltage regions to form the source / drain regions (e.g., 506, 106, 518). For example, a first ion implantation process is performed on the low-voltage region 502a to form the pair of low-voltage source / drain regions 506, a second ion implantation process is performed on the medium-voltage region 502b to form the pair of source / drain regions 106, and so on. In a further embodiment, the low-voltage source / drain region 506 can be formed by an epitaxial growth process.

[0060] like FIG. 17As shown in the cross-sectional view 1700, a first dielectric layer 702 is formed on a substrate 102. In some embodiments, forming the first dielectric layer 702 includes: depositing (e.g., by CVD, PVD, ALD, etc.) a dielectric material (e.g., silicon dioxide, low dielectric constant dielectric material, etc.) on the substrate 102 and performing a planarization process (e.g., chemical mechanical planarization (CMP) process) on the first dielectric layer 702.

[0061] like FIG. 18A Sectional view 1800a and FIG. 18B Sectional view 1800b and FIG. 18C As shown in the top view 1800c, the low-voltage gate electrode structure 510, the gate electrode structure 110 and the high-voltage gate electrode structure 522 are formed in the low-voltage region 502a, the medium-voltage region 502b and the high-voltage region 502c, respectively, thereby defining the low-voltage transistor 504, the transistor 105 and the high-voltage transistor 516. FIG. 18A It shows along FIG. 18C The sectional view 1800a is intercepted by the line extending along the x-axis from the top view 1800c. FIG. 18B It shows along FIG. 18C The sectional view 1800b is taken by the line extending along the y-axis of each of the regions (502a, 502b, 502c) in the top view 1800c.

[0062] In some embodiments, the low-voltage gate electrode structure 510, the gate electrode structure 110, and the high-voltage gate electrode structure 522 are formed by one or more substitution processes. In various embodiments, the substitution process includes: removing one or more sacrificial gate electrode structures ( FIG. 17 The method comprises: 1402a, 1402b, 1402c) forming one or more gate openings above substrate 102; depositing (e.g., by CVD, PVD, ALD, sputtering, electroplating, electroless plating, etc.) one or more gate electrode layers within the one or more gate openings; and performing a planarization process (e.g., CMP process) on the one or more gate electrode layers. The one or more gate electrode layers include at least one conductive layer (e.g., including tungsten, titanium, tantalum, aluminum, titanium nitride, tantalum nitride, etc.). In some embodiments, the one or more gate electrode layers further include a gate dielectric layer (e.g., including a high dielectric constant dielectric material or the like), the gate dielectric layer extending along the at least one conductive layer (e.g., FIG. 6A and 6B The sidewalls and lower surface (shown and / or described) extend.

[0063] In various embodiments, each of the low-pressure region 502a, medium-pressure region 502b, and high-pressure region 502c may undergo an individual substitution process. For example, in such embodiments, a first substitution process may be performed on the low-pressure region 502a to form a low-pressure gate electrode structure 510, a second substitution process may be performed on the medium-pressure region 502b to form a gate electrode structure 110, and so on. In yet another embodiment, the low-pressure gate electrode structure 510, the gate electrode structure 110, and the high-pressure gate electrode structure 522 are formed simultaneously by a single substitution process. In such embodiments, the single substitution process includes: removing the sacrificial gate electrode structure ( FIG. 17 1402a, 1402b, 1402c) to form a gate opening above substrate 102; deposit one or more gate electrode layers within the gate opening (e.g., by CVD, PVD, ALD, sputtering, electroplating, electroless plating, etc.); and perform a planarization process (e.g., CMP process) on the one or more gate electrode layers.

[0064] like FIG. 18B Sectional view 1800b and FIG. 18C As shown in top view 1800c, the gate electrode structure 110 includes a first pair of opposing sidewalls (124a, 124b) extending in a first direction (e.g., along the x-axis), and the first pair of opposing sidewalls (124a, 124b) are spaced apart by a distance 122 between isolation edges (104e1, 104e2). Spacing the gate electrode structure 110 apart from the pair of isolation edges (104e1, 104e2) reduces noise, mitigates the negative impact of reduced GOI of the gate dielectric structure 108 near the isolation edges (104e1, 104e2), and reduces one or more bulges appearing in the gate electrode structure 110. Furthermore, the spacing helps reduce the lateral occupied area of ​​the gate electrode structure 110, thereby reducing the overall size of the medium-voltage region 502b above the substrate 102.

[0065] like FIG. 19 As shown in cross-sectional view 1900, a second dielectric layer 704 is formed over the first dielectric layer 702, and a plurality of conductive contacts 120 are formed over the substrate 102. The second dielectric layer 704 may be formed over the substrate 102, for example, by CVD, PVD, and ALD processes or some other suitable growth or deposition processes. In some embodiments, the process of forming the plurality of conductive contacts 120 includes: etching the first dielectric layer 702 and the second dielectric layer 704 to form contact openings in the first dielectric layer 702 and the second dielectric layer 704; depositing (e.g., by CVD, PVD, sputtering, electroless plating, etc.) a conductive material within the contact openings; and performing a planarization process (e.g., CMP process) on the conductive material.

[0066] like FIG. 20A cross-sectional view 2000 of the structure after forming the third dielectric layer 2002 and the plurality of conductive metal lines 2004 is shown. The third dielectric layer 2002 is formed over the second dielectric layer 704, and the plurality of conductive metal lines 2004 is formed over the conductive contacts 120. The third dielectric layer 2002 can be formed over the second dielectric layer 704, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. In various embodiments, the process for forming the plurality of conductive metal lines includes etching the third dielectric layer 2002 to form a plurality of openings in the third dielectric layer 2002, depositing (e.g., by CVD, PVD, sputtering, electroless plating, etc.) a conductive material within the openings, and performing a planarization process (e.g., a CMP process) on the conductive material.

[0067] FIG. 21 Method 2100 illustrates some embodiments of a method of forming a transistor having gate electrode structures spaced apart between isolation edges of STI structures, in accordance with the present disclosure. While the method 2100 is illustrated and / or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering or acts. Thus, in some embodiments, the acts can be performed in an order different than that shown, and / or performed concurrently. Further, in some embodiments, not all illustrated acts or events can be performed, and / or additional acts or events not shown can be performed, in some embodiments.

[0068] At act 2102, shallow trench isolation (STI) structures are formed within the low- voltage region, the middle-voltage region, and the high-voltage region of the substrate. FIG. 8A and FIG. 8B Cross-sectional view 800a and top view 800b illustrate some embodiments corresponding to act 2102.

[0069] At act 2104, a multi-channel ion implantation process is performed to form a high- voltage well region in the high-voltage region, a well region and a lightly doped region in the middle-voltage region, and a low-voltage well region and a low-voltage lightly doped region in the low-voltage region. FIGS. 9-13 Cross-sectional views 900-1300 illustrate some embodiments corresponding to act 2104.

[0070] At act 2106, a high-voltage gate dielectric structure is formed in the high-voltage region. FIG. 9 Cross-sectional view 900 illustrates some embodiments corresponding to act 2106.

[0071] At act 2108, a patterning process is performed on the substrate to form an opening in the substrate within the middle-voltage region. FIG. 11 Cross-sectional view 1100 illustrates some embodiments corresponding to act 2108.

[0072] At action 2110, a gate dielectric structure is formed within the opening and extending between the lightly doped regions. FIG. 12 A cross-sectional view 1200 is shown corresponding to some embodiments of action 2110.

[0073] At action 2112, a plurality of sacrificial gate electrode structures are formed over the substrate. The plurality of sacrificial gate electrode structures includes a first sacrificial gate electrode structure in the low voltage region, a second sacrificial gate electrode structure in the medium voltage region, and a third sacrificial gate electrode structure in the high voltage region. FIG. 14A and FIG. 14B A cross-sectional view 1400a and a top view 1400b are shown corresponding to some embodiments of action 2112.

[0074] At action 2114, a pair of high voltage source / drain regions are formed on opposite sides of the third sacrificial gate electrode structure, a pair of source / drain regions are formed on opposite sides of the second sacrificial gate electrode structure, and a pair of low voltage source / drain regions are formed on opposite sides of the first sacrificial gate electrode structure. FIG. 16 A cross-sectional view 1600 is shown corresponding to some embodiments of action 2114.

[0075] At action 2116, a low voltage gate electrode structure, a gate electrode structure, and a high voltage gate electrode structure are formed to replace the first, second, and third sacrificial gate electrode structures, respectively. The gate electrode structure is laterally offset from a pair of isolation edges of the isolation structure extending between the pair of source / drain regions, and the low voltage and high voltage gate electrode structures directly overlie other isolation edges of the isolation structure, respectively. FIG. 18A , FIG. 18B and FIG. 18C A cross-sectional view 1800a and 1800b and a top view 1800c are shown corresponding to some embodiments of action 2116.

[0076] At action 2118, a plurality of conductive contacts and a plurality of conductive metal lines are formed over the substrate. FIG. 19 and FIG. 20 A cross-sectional view 1900 and 2000 are shown corresponding to some embodiments of action 2118.

[0077] Thus, in some embodiments, the present disclosure relates to a transistor having a gate electrode structure spaced apart from a pair of isolation edges of a STI structure, wherein the pair of isolation edges are elongated in a first direction extending between a pair of source / drain regions disposed on opposite sides of the gate electrode structure.

[0078] In some embodiments, an integrated chip is provided, comprising: an isolation structure extending into a front side surface of a substrate, wherein the isolation structure laterally surrounds a first device region of the substrate, wherein the isolation structure comprises a pair of isolation edges elongated in a first direction and at least partially defining the first device region; a pair of source / drain regions disposed within the first device region and laterally spaced apart from each other in the first direction; and a first gate electrode structure disposed in the first device region and spaced between the pair of source / drain regions, wherein the first gate electrode structure comprises a first pair of opposing sidewalls elongated in the first direction, wherein the opposing sidewalls are laterally offset from corresponding ones of the pair of isolation edges by a non-zero distance in a direction toward a center of the first gate electrode structure.

[0079] In some embodiments, the integrated chip further comprises a first gate dielectric structure extending into the front side surface of the substrate and under the first gate electrode structure, wherein a length of the first gate dielectric structure defined along a second direction orthogonal to the first direction is greater than a length of the first gate electrode structure. In some embodiments, a length of the pair of source / drain regions is greater than the length of the first gate electrode structure. In some embodiments, the first gate dielectric structure laterally extends continuously between the first pair of isolation edges of the isolation structure. In some embodiments, the integrated chip further comprises a sidewall spacer structure laterally surrounding the first gate electrode structure, wherein the sidewall spacer structure is laterally spaced between the first pair of isolation edges of the isolation structure. In some embodiments, the integrated chip further comprises a second gate electrode structure disposed in a second device region of the substrate adjacent to the first device region, wherein the isolation structure comprises a second pair of isolation edges at least partially dividing the second device region, wherein the second gate electrode structure directly overlies the second pair of isolation edges. In some embodiments, a length of the second gate electrode structure is greater than the length of the first gate electrode structure. In some embodiments, the non-zero distance is in a range from about 0.01 to 0.1 microns.

[0080] In some embodiments, the disclosure provides an integrated chip comprising: a semiconductor substrate having a first device region laterally adjacent to a second device region; a shallow trench isolation (STI) structure extending into a front side surface of the semiconductor substrate, wherein the STI structure comprises a first pair of isolation edges elongated in a first direction and at least partially dividing the first device region and a second pair of isolation edges elongated in the first direction and at least partially dividing the second device region; a first transistor disposed within the first device region, wherein the first transistor comprises a first gate electrode structure and a first pair of source / drain regions disposed on opposite sides of the first gate electrode structure, wherein the first gate electrode structure is elongated in a second direction orthogonal to the first direction and directly overlies the first pair of isolation edges; and a second transistor disposed within the second device region, wherein the second transistor comprises a second gate electrode structure and a second pair of source / drain regions disposed on opposite sides of the second gate electrode structure, wherein the second gate electrode structure comprises a pair of opposing sidewalls elongated in the first direction, wherein the opposing sidewalls of the second gate electrode structure are spaced between the second pair of isolation edges.

[0081] In some embodiments, the integrated chip further comprises a sidewall spacer wrapped around the second gate electrode structure, wherein a distance between the pair of opposing sidewalls of the second gate electrode structure and the second pair of isolation edges is greater than a lateral thickness of the sidewall spacer. In some embodiments, the second gate electrode structure comprises a protrusion extending from a first sidewall of the pair of opposing sidewalls past a first edge of the second pair of isolation edges, wherein the protrusion directly overlies a portion of the shallow trench isolation structure in the second device region, wherein a length of the protrusion is less than a length of the first sidewall. In some embodiments, the integrated chip further comprises a conductive contact directly overlying and contacting the protrusion and electrically coupled to the second gate electrode structure. In some embodiments, the first transistor comprises a first gate dielectric structure recessed into the semiconductor substrate and under the first gate electrode structure, wherein the second transistor comprises a second gate dielectric structure recessed into the semiconductor substrate and under the second gate electrode structure, wherein a length of the second gate dielectric structure defined along the second direction is greater than a length of the second gate electrode structure. In some embodiments, a length of the first gate dielectric structure defined along the second direction is less than a length of the first gate electrode structure. In some embodiments, a thickness of the first gate dielectric structure is greater than a thickness of the second gate dielectric structure. In some embodiments, the first transistor is configured as a fin field effect transistor and the second transistor is configured as a planar metal oxide semiconductor field effect transistor, wherein the semiconductor substrate comprises a plurality of fin structures laterally spaced between the first transistor and the second transistor.

[0082] In some embodiments, the disclosure provides a method for forming an integrated chip, the method comprising: forming an isolation structure extending into a front side surface of a substrate, wherein the isolation structure comprises a pair of isolation edges, wherein the isolation edges each extend in a first direction and at least partially define a first device region of the substrate; forming a first gate dielectric structure recessed in the substrate and continuously laterally extending between the pair of isolation edges; forming a first gate electrode structure over the first gate dielectric structure, wherein the first gate electrode structure comprises a first pair of opposing sidewalls, wherein the opposing sidewalls extend in the first direction and are parallel to each other, wherein the opposing sidewalls are each spaced apart from an adjacent isolation edge of the pair of isolation edges by a lateral distance; and performing an ion implantation process to form a pair of source / drain regions on opposite sides of the first gate electrode structure, wherein the source / drain regions extend in a second direction orthogonal to the first direction.

[0083] In some embodiments, the method further comprises forming a second gate electrode structure over a second device region of the substrate, wherein the isolation structure divides the second device region of the substrate, and wherein the second gate electrode structure directly overlies at least a portion of the isolation structure. In some embodiments, the first gate electrode structure and the second gate electrode structure are formed simultaneously. In some embodiments, the first gate dielectric structure continuously laterally extends from the pair of opposing sidewalls to the pair of isolation edges.

[0084] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the present application; even though the above-described embodiments of the present application have been described in detail, those skilled in the art should understand that the technical solutions recorded in the above-described embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An integrated chip, characterized by, including: an isolation structure extending into a front side surface of a substrate, wherein the isolation structure laterally surrounds a first device region of the substrate, wherein the isolation structure includes a first pair of isolation edges elongated in a first direction and at least partially defining the first device region; a pair of source / drain regions disposed within the first device region and laterally spaced apart from one another in the first direction; and a first gate electrode structure disposed in the first device region and spaced between the pair of source / drain regions, wherein the first gate electrode structure includes a first pair of opposing sidewalls elongated in the first direction, wherein the first pair of opposing sidewalls is laterally offset from a corresponding isolation edge of the first pair of isolation edges by a non-zero distance in a direction toward a center of the first gate electrode structure.

2. The integrated chip of claim 1, wherein, further including: a first gate dielectric structure extending into the front side surface of the substrate and under the first gate electrode structure, wherein a length of the first gate dielectric structure defined along a second direction orthogonal to the first direction is greater than a length of the first gate electrode structure.

3. The integrated chip of claim 1, wherein, further including: a sidewall spacer structure laterally surrounding the first gate electrode structure, wherein the sidewall spacer structure is laterally spaced between the first pair of isolation edges of the isolation structure.

4. The integrated chip of claim 1, wherein, further including: a second gate electrode structure disposed in a second device region of the substrate adjacent to the first device region, wherein the isolation structure includes a second pair of isolation edges at least partially dividing the second device region, wherein the second gate electrode structure directly overlies the second pair of isolation edges.

5. An integrated chip, characterized by including: a semiconductor substrate having a first device region laterally adjacent to a second device region; a shallow trench isolation structure extending into a front side surface of the semiconductor substrate, wherein the shallow trench isolation structure includes a first pair of isolation edges elongated in a first direction and at least partially dividing the first device region and a second pair of isolation edges elongated in the first direction and at least partially dividing the second device region; a first transistor disposed within the first device region, wherein the first transistor includes a first gate electrode structure and a first pair of source / drain regions disposed on opposing sides of the first gate electrode structure, wherein the first gate electrode structure is elongated in a second direction orthogonal to the first direction and directly overlies the first pair of isolation edges; and a second transistor disposed within the second device region, wherein the second transistor includes a second gate electrode structure and a second pair of source / drain regions disposed on opposing sides of the second gate electrode structure, wherein the second gate electrode structure includes a pair of opposing sidewalls elongated in the first direction, wherein the pair of opposing sidewalls of the second gate electrode structure is spaced apart between the second pair of isolation edges.

6. The integrated chip of claim 5, wherein, further including: a sidewall spacer wrapped around the second gate electrode structure, wherein a distance between the pair of opposing sidewalls of the second gate electrode structure and the second pair of isolation edges is greater than a lateral thickness of the sidewall spacer.

7. The integrated chip of claim 5, wherein, wherein the second gate electrode structure includes a protrusion extending from a first sidewall of the pair of opposing sidewalls past a first edge of the second pair of isolation edges, wherein the protrusion directly overlies a portion of the shallow trench isolation structure in the second device region, wherein a length of the protrusion is less than a length of the first sidewall.

8. The integrated chip of claim 7, wherein, Also included are: a conductive contact directly overlying and contacting the protrusion and electrically coupled to the second gate electrode structure.

9. The integrated chip of claim 5, wherein, wherein the first transistor includes a first gate dielectric structure recessed into the semiconductor substrate and underlying the first gate electrode structure, wherein the second transistor includes a second gate dielectric structure recessed into the semiconductor substrate and underlying the second gate electrode structure, wherein a length of the second gate dielectric structure defined along the second direction is greater than a length of the second gate electrode structure.

10. The integrated chip of claim 5, wherein, wherein the first transistor is configured as a fin field effect transistor and the second transistor is configured as a planar metal oxide semiconductor field effect transistor, wherein the semiconductor substrate includes a plurality of fin structures laterally spaced apart between the first transistor and the second transistor. wherein the first transistor is configured as a fin field effect transistor and the second transistor is configured as a planar metal oxide semiconductor field effect transistor, wherein the semiconductor substrate includes a plurality of fin structures laterally spaced apart between the first transistor and the second transistor.

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