Light-emitting chip, semiconductor device, light-emitting device, and image forming and printing apparatus

Abstract

The utility model provides a light-emitting chip, a semiconductor device, a light-emitting device and imaging printing equipment. The light-emitting chip comprises a first semiconductor device, the first semiconductor device comprises a first substrate, a plurality of light-emitting elements and a first joint part, the light-emitting elements and the first joint part are arranged on the first substrate, and the first joint part is electrically connected with the light-emitting elements; the second semiconductor device comprises a second substrate, a driving integrated circuit layer and a second joint part, the driving integrated circuit layer and the second joint part are arranged on the second substrate, the driving integrated circuit layer is electrically connected with the second joint part, the first joint part is jointed with the second joint part, and the first joint part is electrically connected with the second joint part. According to the utility model, the problem of low yield of the LED printing head in the prior art is solved.

Description

Technical Field

[0001] This utility model relates to the field of printing equipment technology, and more specifically, to a light-emitting chip, a semiconductor device, a light-emitting device, and an imaging printing device. Background Technology

[0002] In today's global printing industry, electrophotographic printing has become the mainstream mode of office printing, mainly including LED (Light-Emitting Diode) printing, laser printing, and inkjet printing. Among them, LED printing, as an emerging dot matrix printing technology, is increasingly favored by users due to its advantages such as fast printing speed, good image quality, simple optical path, small size, long service life, energy saving, and environmental friendliness.

[0003] Currently, the core component of a conventional LED printhead in an LED printer, the integrated light-emitting driver IC, mainly consists of a substrate and an LED epitaxial film and a driver IC layer film disposed on the substrate. However, the LED epitaxial film and the driver IC layer film are formed on their respective substrates. Through techniques such as thin-film transfer, the LED epitaxial film and driver IC layer film are peeled off from their original substrates and migrated to fixed positions on the substrate. Thin-film transfer technology has high requirements for process stability and precision to ensure uniform bonding between the migrated film and the substrate, maintaining good conductivity. Any minute deviation can affect the yield of the LED printhead.

[0004] In other words, existing LED printheads suffer from low yield rates. Utility Model Content

[0005] The main objective of this invention is to provide a light-emitting chip, a semiconductor device, a light-emitting device, and an imaging printing device to solve the problem of low yield in existing LED printheads.

[0006] To achieve the above objectives, according to one aspect of the present invention, a light-emitting chip is provided, comprising: a first semiconductor device, the first semiconductor device including a first substrate and a plurality of light-emitting elements and a first bonding portion disposed on the first substrate, the first bonding portion being electrically connected to the plurality of light-emitting elements; and a second semiconductor device, the second semiconductor device including a second substrate and a driving integrated circuit layer and a second bonding portion disposed on the second substrate, the driving integrated circuit layer being electrically connected to the second bonding portion, the first bonding portion being bonded to the second bonding portion, and the first bonding portion being electrically connected to the second bonding portion.

[0007] Furthermore, the first bonding portion includes: a plurality of first bonding pads, each first bonding pad being electrically connected to a first electrode of a plurality of light-emitting elements in a one-to-one correspondence; at least one second bonding pad, each second bonding pad being electrically connected to a second electrode of at least one light-emitting element, and the first bonding pads and the second bonding pads abutting against the second bonding portion.

[0008] Furthermore, the first semiconductor device also includes: a plurality of first connection lines, one end of which is connected to a first bonding pad, and the other end of which is connected to a first electrode of the light-emitting element.

[0009] Furthermore, the first semiconductor device also includes at least one connection terminal for connecting to an external signal source, and each connection terminal is electrically connected to a corresponding second bonding pad.

[0010] Furthermore, the first semiconductor device also includes at least one second connection line, one end of which is connected to a second bonding pad, and the other end of which is connected to a connection terminal.

[0011] Furthermore, multiple first bonding pads are arranged in an array.

[0012] Furthermore, the driver integrated circuit layer includes multiple light-emitting driver sub-circuits and at least one control processing sub-circuit. The second bonding portion includes: multiple third bonding pads, which are electrically connected to the output ports of the multiple light-emitting driver sub-circuits in a one-to-one correspondence, and the multiple third bonding pads abut against the multiple first bonding pads; at least one fourth bonding pad, which is electrically connected to the at least one control processing sub-circuit, and each fourth bonding pad abuts against each of the second bonding pads.

[0013] Furthermore, the first bonding portion further includes a first bonding layer, which surrounds the first bonding pad and the second bonding pad, and the orthographic projection of the first bonding layer on the first substrate is spaced apart from the orthographic projections of the first bonding pad and the second bonding pad on the first substrate; the second bonding portion further includes a second bonding layer, which surrounds the first bonding pad and the second bonding pad, and the orthographic projection of the second bonding layer on the second substrate is spaced apart from the orthographic projections of the first bonding pad and the second bonding pad on the second substrate, and the first bonding layer abuts against the second bonding layer.

[0014] Furthermore, the light-emitting chip satisfies at least one of the following: the first bonding layer and the second bonding layer are metal layers, and the first bonding layer and the second bonding layer are connected to the ground layer; the thickness of the first bonding layer is greater than or equal to 100 nm and less than or equal to 200 nm; the width of the first bonding layer is greater than or equal to 100 μm and less than or equal to 200 μm; the thickness of the second bonding layer is greater than or equal to 100 nm and less than or equal to 200 nm; the width of the second bonding layer is greater than or equal to 100 μm and less than or equal to 200 μm.

[0015] Furthermore, the first semiconductor device also includes a first bonding dielectric layer, the first bonding dielectric layer, the first bonding portion and the light-emitting element are located on the same side of the first substrate, and the surface of the first bonding portion away from the first substrate is flush with the surface of the first bonding dielectric layer away from the first substrate.

[0016] Furthermore, the second semiconductor device also includes a second bonding dielectric layer, the second bonding dielectric layer and the second bonding portion are located on the same side of the second substrate, and the surface of the second bonding portion away from the second substrate is flush with the surface of the second bonding dielectric layer away from the second substrate, and the second bonding dielectric layer is in contact with the first bonding dielectric layer.

[0017] Furthermore, the first substrate has a first bonding region, the orthographic projection of the first bonding portion on the first substrate is located within the first bonding region, the ratio of the width W2 of the first bonding region to the width W1 of the first substrate is greater than or equal to 0.3 and less than or equal to 0.5; the ratio of the length L2 of the first bonding region to the length L1 of the first substrate is greater than or equal to 0.5 and less than or equal to 1.

[0018] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; and the aforementioned light-emitting chip, wherein the light-emitting chip is disposed on the substrate.

[0019] According to another aspect of the present invention, a light-emitting device is provided, comprising the semiconductor device described above.

[0020] According to another aspect of the present invention, an imaging printing apparatus is provided, including the above-described light-emitting device.

[0021] Furthermore, the resolution of the imaging printing equipment should reach at least 600 DPI.

[0022] The light-emitting chip using the technical solution of this utility model includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first substrate and a plurality of light-emitting elements and a first bonding portion disposed on the first substrate. The first bonding portion is electrically connected to the plurality of light-emitting elements. The second semiconductor device includes a second substrate and a driving integrated circuit layer and a second bonding portion disposed on the second substrate. The driving integrated circuit layer is electrically connected to the second bonding portion. The first bonding portion is bonded to the second bonding portion and is electrically connected to the second bonding portion.

[0023] By providing a first bonding portion on a first semiconductor device and a second bonding portion on a second semiconductor device, the first and second bonding portions are bonded together, avoiding the film peeling and migration steps and simplifying the process complexity in the manufacturing process. This not only reduces the need for high-end, expensive semiconductor equipment, such as film peeling machines and mass transfer equipment, but also lowers equipment usage and maintenance costs. Furthermore, a simplified process typically means shorter production cycles and higher production efficiency, further reducing manufacturing costs. Since the first and second bonding portions in this application are directly bonded without mass transfer, the physical stress during the mass transfer process is avoided, thereby enhancing the structural stability of the first and second semiconductor devices, reducing internal chip damage caused by uneven stress, and effectively improving product yield.

[0024] Furthermore, traditional thin-film transfer techniques, due to issues with the uniformity of the film's bonding with the substrate after migration and the resulting step height, directly affect the connectivity of interconnects and the uniformity of light emission from the light-emitting element. The technical solution of this application avoids these potential problems by directly bonding the first and second semiconductor devices, thereby improving the uniformity and consistency of chip light emission, reducing the probability of interconnect open-circuit failures, and enhancing chip reliability. In this application, the direct bonding of the first and second semiconductor devices eliminates the need for film peeling, significantly improving the yield of the light-emitting chip. Attached Figure Description

[0025] The accompanying drawings, which form part of this application, are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an undue limitation of the present invention. In the drawings:

[0026] Figure 1 A schematic diagram of the structure of a light-emitting chip according to an optional embodiment of the present invention is shown;

[0027] Figure 2 It shows Figure 1 A schematic diagram of the internal structure of the first semiconductor device in China;

[0028] Figure 3 It shows Figure 2 A partial enlarged view of the first semiconductor device in the middle;

[0029] Figure 4 It shows Figure 1 A view of the second semiconductor device from one angle;

[0030] Figure 5 It shows Figure 1 A view of the light-emitting chip from one angle;

[0031] Figure 6 It shows Figure 1 A schematic diagram of the bonding process between the first semiconductor device and the second semiconductor device;

[0032] Figure 7 It shows Figure 6 A schematic diagram of the structure after the first semiconductor device and the second semiconductor device are joined together;

[0033] Figure 8 A schematic diagram illustrating the bonding process between the first semiconductor device and the second semiconductor device in another optional embodiment of the present invention is shown;

[0034] Figure 9 It shows Figure 8 A schematic diagram of the structure after the first semiconductor device and the second semiconductor device are joined together;

[0035] Figure 10 A schematic diagram of the structure of a light-emitting chip according to another optional embodiment of the present invention is shown;

[0036] Figure 11 A schematic diagram of the semiconductor device in one optional embodiment of the present invention is shown;

[0037] Figure 12 A schematic diagram of the light-emitting device in an optional embodiment of the present invention is shown;

[0038] Figure 13 It shows Figure 12 A view of the central lens component from one angle;

[0039] Figure 14 It shows Figure 12 The positional relationship between the intermediate lens component and the object plane and image plane;

[0040] Figure 15 A schematic diagram of the imaging printing device in an optional embodiment of the present invention is shown.

[0041] The above figures include the following reference numerals:

[0042] 10. First semiconductor device; 11. First substrate; 111. First bonding region; 12. Light-emitting element; 13. First bonding portion; 131. First bonding pad; 132. Second bonding pad; 133. First bonding layer; 14. First interconnect; 15. Connecting terminal; 16. Second interconnect; 17. First bonding dielectric layer; 20. Second semiconductor device; 21. Second substrate; 22. Driver integrated circuit layer; 23. Second bonding portion; 231. Third bonding pad; 232. Fourth bonding pad ; 233, Second bonding layer; 24, Second bonding dielectric layer; 25, Third connecting line; 30, Substrate; 40, Light-emitting chip; 50, Socket; 100, Semiconductor device; 200, Frame; 201, First opening; 202, Second opening; 300, Lens component; 301, Support; 302, Columnar optical lens; 410, Light-emitting device; 420, Photosensitive drum; 430, Charging roller; 440, Toner cartridge; 450, Transfer roller; 460, Fixing roller; 470, Paper receiving component; 480, Paper dispensing component. Detailed Implementation

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0045] In this utility model, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not used to limit this utility model.

[0046] To address the low yield problem of existing LED printheads, this invention provides a light-emitting chip, a semiconductor device, a light-emitting device, and an imaging printing device.

[0047] like Figures 1 to 10As shown, the light-emitting chip 40 includes a first semiconductor device 10 and a second semiconductor device 20. The first semiconductor device 10 includes a first substrate 11 and a plurality of light-emitting elements 12 and a first bonding portion 13 disposed on the first substrate 11. The first bonding portion 13 is electrically connected to the plurality of light-emitting elements 12. The second semiconductor device 20 includes a second substrate 21 and a driving integrated circuit layer 22 and a second bonding portion 23 disposed on the second substrate 21. The driving integrated circuit layer 22 is electrically connected to the second bonding portion 23. The first bonding portion 13 is bonded to the second bonding portion 23 and is electrically connected to the second bonding portion 23.

[0048] By providing a first bonding portion 13 on the first semiconductor device 10 and a second bonding portion 23 on the second semiconductor device 20, the first bonding portion 13 and the second bonding portion 23 are bonded together, avoiding the film peeling and migration steps and simplifying the process complexity in the production process. This not only reduces the need for high-end, expensive semiconductor equipment, such as film peeling machines and mass transfer equipment, but also reduces equipment usage and maintenance costs. Furthermore, a simplified process typically means shorter production cycles and higher production efficiency, further reducing manufacturing costs. Since the first bonding portion 13 and the second bonding portion 23 in this application are directly bonded without mass transfer, physical stress during the mass transfer process is avoided, thereby enhancing the structural stability of the first semiconductor device 10 and the second semiconductor device 20, reducing internal chip damage caused by uneven stress, and effectively improving product yield.

[0049] Furthermore, traditional thin-film transfer techniques, due to issues with the uniformity of the film's bonding with the substrate after migration and the resulting step height, directly affect the connectivity of interconnects and the uniformity of light emission from the light-emitting element 12. The technical solution of this application avoids these potential problems by directly bonding the first semiconductor device 10 and the second semiconductor device 20, thereby improving the uniformity and consistency of chip light emission, reducing the probability of interconnect open-circuit failures, and enhancing chip reliability. In this application, the direct bonding of the first semiconductor device 10 and the second semiconductor device 20 eliminates the need for film peeling, significantly improving the yield of the light-emitting chip 40.

[0050] In some alternative embodiments, the first joint 13 and the second joint 23 may be connected by thermoforming or bonding.

[0051] In some alternative embodiments, the first substrate 11 has a planar surface. The first substrate 11 may be made of materials such as GaAs, sapphire, or SiC. The second substrate 21 has a planar surface. The second substrate 21 may be made of silicon, or may be made of other compound semiconductors, organic semiconductors, or insulators such as sapphire or glass.

[0052] In some optional embodiments, the thickness of the first substrate 11 is greater than or equal to 200 μm and less than or equal to 400 μm. This ensures the structural strength of the first substrate 11 while avoiding excessive thickness, which would hinder the miniaturization of the first semiconductor device 10. For example, the thickness of the first substrate 11 is 300 μm. The thickness of the second substrate 21 is greater than or equal to 200 μm and less than or equal to 400 μm. This ensures the structural strength of the second substrate 21 while avoiding excessive thickness, which would hinder the miniaturization of the second semiconductor device 20. For example, the thickness of the second substrate 21 is 300 μm.

[0053] Optionally, the light-emitting element 12 is an LED.

[0054] In some alternative embodiments, please refer to Figures 1 to 4 The light-emitting elements 12 can be arranged in a single row, and can be composed of multiple light-emitting elements 12 with the same power arranged at a high density and equal spacing. The array density of the light-emitting elements 12 can achieve a resolution of greater than or equal to 600 DPI. In addition, the light-emitting elements 12 are not limited to a single row arrangement, but can also be arranged in multiple rows, or in a houndstooth pattern. No specific restrictions are made here.

[0055] In some alternative embodiments, please refer to Figure 2The first bonding portion 13 includes a plurality of first bonding pads 131 and at least one second bonding pad 132. Each first bonding pad 131 is electrically connected to a first electrode of a plurality of light-emitting elements 12 in a one-to-one correspondence; each second bonding pad 132 is electrically connected to a second electrode of at least one light-emitting element 12. The first bonding pads 131 and the second bonding pads 132 abut against the second bonding portion 23. Through the one-to-one connection of the first bonding pads 131 to the first electrodes (typically control electrodes or cathodes) of the light-emitting elements 12, and the connection of the second bonding pads 132 to the second electrodes (typically common electrodes or anodes) of the light-emitting elements 12, a stable electrical input and output path can be ensured for each light-emitting element 12. This precise electrical pairing reduces interference and attenuation during signal transmission, enhancing the response speed and light output consistency of the light-emitting elements 12. By directly forming the first bonding pads 131 and the second bonding pads 132 on the first semiconductor device 10, complex and expensive steps such as thin film peeling, transfer, and repair are eliminated, simplifying the chip fabrication process. This not only reduces investment costs in manufacturing equipment, but also reduces losses during the process, improves yield, and ultimately reduces the manufacturing cost per chip.

[0056] In some alternative embodiments, please refer to Figure 2 and Figure 3 The first semiconductor device 10 also includes a plurality of first connection lines 14. One end of each first connection line 14 is connected to a first bonding pad 131, and the other end is connected to the first electrode of the light-emitting element 12. By using the first connection lines 14, a stable electrical connection can be ensured between the first electrode of the light-emitting element 12 and the first bonding pad 131. The first connection lines 14 can be made of various conductive materials, such as gold, aluminum, copper, or palladium, which have good conductivity and mechanical strength, effectively reducing the resistance at the connection and maintaining long-term connection stability. Each first connection line 14 is directly connected to the first electrode of a light-emitting element 12, which optimizes the current distribution in the array of light-emitting elements 12, ensuring that each light-emitting element 12 receives the required operating current, thereby achieving a uniform light emission effect. Especially in a common-anode light-emitting element 12 array, this connection method can precisely control the driving current of each light-emitting element 12, avoiding the problem of uneven current distribution among multiple light-emitting elements 12.

[0057] In some optional embodiments, all light-emitting elements 12 may share a single second electrode, or several light-emitting elements 12 may share a single second electrode; no specific limitation is made here. When the driving current of the light-emitting elements 12 needs to be large, the number of second bonding pads 132 can be further increased, and they can be grouped and driven according to the number of light-emitting elements 12, the effective current of the light-emitting elements 12, and the current-carrying capacity of the interconnects. The second electrode can be connected to the second bonding pad 132 via an interconnect (not shown in the figure), in which case the current-carrying capacity of the interconnect is greater than the current-carrying capacity of the first connection line 14. For example, the current-carrying capacity of the interconnect is N times the current-carrying capacity of the first connection line 14, where N is a natural number greater than or equal to 2. For example, the COM electrode is the anode, the control electrode is the cathode, the anode is the second electrode, and the cathode is the first electrode.

[0058] In some alternative embodiments, the first connection line 14 is formed inside the first semiconductor device 10, rather than as an external lead. For example, the first connection line 14 is a conductive thin film, which can be made of materials including gold, palladium, aluminum, polycrystalline silicon, conductive oxide, etc. Alternatively, the conductive thin film can be a single-layer film, such as a gold film, or a multi-layer film, such as a multi-layer film with titanium, platinum, and gold layers, or a multi-layer film with palladium and gold layers. When the first connection line 14, with a thickness of 0.5 μm and a width of 5 μm, passes through, it can provide several milliamps of current. The material, thickness, and width of the first connection line 14 can be designed according to the current requirements of the light-emitting element 12. The first connection line 14 is formed using chemical vapor deposition (CVD) or sputtering technology. Of course, the first connection line 14 can also be formed using other processes, which are not specifically limited here.

[0059] In some alternative embodiments, please refer to Figure 2 and Figure 3 The first bonding pad 131 is connected to the end of the first connecting line 14. The width of the first bonding pad 131 is greater than the width of the first connecting line 14 to ensure a stable connection between the first bonding pad 131 and the first connecting line 14. At the same time, the size of the first bonding pad 131 is designed to be larger to facilitate the reduction of the bonding alignment tolerance when the first bonding pad 131 is bonded to the third bonding pad 231, which is beneficial to improving the product yield.

[0060] In some alternative embodiments, the first bonding pad 131 can be a conductive thin film. The material of the first bonding pad 131 is the same as the material of the first bonding layer 133 or the material of the first connecting line 14, but it can also be a different material, as long as there is no inter-atomic diffusion between the different materials to avoid causing defects at the connection area.

[0061] In some alternative embodiments, please refer to Figure 2 and Figure 3The first semiconductor device 10 also includes at least one connection terminal 15 for connecting to an external signal source, and each connection terminal 15 is electrically connected to a corresponding second bonding pad 132. The presence of the connection terminal 15 allows the first semiconductor device 10 to be directly electrically connected to an external signal source (such as a control system, power supply, etc.) without the need for additional cables or complex wiring structures. This not only simplifies the assembly process of the LED printhead but also provides convenience in equipment maintenance and upgrades, reducing the possibility of connection errors. Furthermore, since the connection terminal 15 is directly electrically connected to the second bonding pad 132 on the first semiconductor device 10, and the distance between the connection terminal 15 and the second bonding pad 132 is relatively short, the signal transmission path is greatly shortened, thereby reducing signal delay, attenuation, and interference, and improving the integrity of signal transmission. This is particularly important for LED printheads, as they require high-precision signal transmission to control the accurate lighting of each light-emitting element 12 to achieve high-quality printed images.

[0062] Optionally, the external signal source may include power signals, clock signals, data signals, and other control signals.

[0063] In some alternative embodiments, please refer to Figure 2 and Figure 3 The first semiconductor device 10 also includes at least one second connection line 16, one end of which is connected to the second bonding pad 132, and the other end of which is connected to the connection terminal 15. The second connection line 16 ensures a stable and efficient electrical connection between the light-emitting element 12 array and the external circuitry. This connection method reduces potential breakpoints in the signal transmission path, enhances the robustness of the electrical connection, and maintains stable performance even during long-term operation or in harsh environments. The second connection line 16 can be designed to have a higher current carrying capacity. Compared to the first connection line 14, the second connection line 16 can more effectively distribute large currents, avoiding localized overheating or electromigration caused by current concentration, thereby improving the thermal stability of the chip and the uniformity of current distribution.

[0064] In some alternative embodiments, the first connecting line 14 and the second connecting line 16 are on the same layer, that is, the first connecting line 14 and the second connecting line 16 can be manufactured in the same process step.

[0065] In some alternative embodiments, the first bonding pad 131, the second bonding pad 132, and the connection terminal 15 are located on the same layer, that is, the first bonding pad 131, the second bonding pad 132, and the connection terminal 15 can be fabricated in the same process step.

[0066] In some alternative embodiments, please refer to Figure 2 and Figure 3 Multiple first bonding pads 131 are arranged in an array. This array of first bonding pads 131 ensures that the first electrode of each light-emitting element 12 (such as an LED) has a direct and independent electrical connection point. This design reduces crossovers and interference in the signal transmission path, improving signal integrity and the reliability of electrical connections, especially crucial in high-resolution printheads where precise control of each light-emitting element 12 is critical. The array of first bonding pads 131 also simplifies the design of the first semiconductor device 10 and simplifies packaging. This design allows for high-density electrical connections between the first semiconductor device 10 and the second semiconductor device 20, reducing the length and complexity of internal wires and facilitating more compact chip layouts and designs.

[0067] In some alternative embodiments, please refer to Figure 4 and Figure 7 The driving integrated circuit layer 22 includes multiple light-emitting driving sub-circuits and at least one control processing sub-circuit. The second bonding portion 23 includes multiple third bonding pads 231 and at least one fourth bonding pad 232. The multiple third bonding pads 231 are electrically connected to the output ports of the multiple light-emitting driving sub-circuits one-to-one, and the multiple third bonding pads 231 abut against the multiple first bonding pads 131. The at least one control processing sub-circuit is electrically connected to the fourth bonding pads 232, and each fourth bonding pad 232 abuts against each second bonding pad 132. The design of multiple light-emitting driving sub-circuits allows each light-emitting element 12 to be controlled by an independent driving circuit. This not only enables precise adjustment of the brightness of each light-emitting element 12, but also allows for rapid response based on image data, optimizing the quality of image printing. Since the light-emitting driving sub-circuits correspond one-to-one with the third bonding pads 231 and are directly electrically connected to the first bonding pads 131 on the first semiconductor device 10, rapid signal transmission and precise control are ensured. By directly contacting the first bonding pad 131 and the third bonding pad 231, signal reflections and crosstalk that may occur in traditional wire bonding or thin-film transfer steps are reduced, ensuring high-quality transmission of drive signals and enhancing the clarity and contrast of printed images. The direct electrical connection between the third bonding pad 231 and the first bonding pad 131 forms a direct path for heat conduction, reducing thermal resistance and facilitating rapid heat dissipation from the light-emitting element 12. This extends the lifespan of the light-emitting element 12 and the integrated circuit, and improves thermal stability during the printing process. The connection between the control processing subcircuit and the fourth bonding pad 232, as well as its direct contact with the second bonding pad 132, improves the speed and accuracy of signal processing. This enables the chip to quickly process high-speed data streams, meeting the requirements of high-resolution printheads, while ensuring accurate conversion and control of image data.

[0068] Multiple third bonding pads 231 are bonded to multiple first bonding pads 131, and each fourth bonding pad 232 is bonded to each second bonding pad 132. Multiple light-emitting elements 12 emit light through timing logic and data driving. The driving integrated circuit layer 22 includes an array driving section, a control timing logic processing section, a data processing section, and a COM section, etc. Each section is interconnected through multiple connection lines and electrically connected to the corresponding bonding pads in the first semiconductor device 10 through the connection lines and their bonding pads. The control timing logic processing section, data processing section, etc., correspond to the clock signals, data signals, and other control signals input to the first semiconductor device 10, and they are each connected to the corresponding bonding pads through connection lines. In particular, the COM section corresponds to the COM terminal of the first semiconductor device 10 and is connected to the corresponding bonding pad through corresponding connection lines. In some optional embodiments, at least one second bonding pad 132 is connected to the COM terminal of the first semiconductor device 10.

[0069] In some alternative embodiments, please refer to Figure 6 and Figure 7 The first bonding portion 13 further includes a first bonding layer 133, which surrounds the first bonding pad 131 and the second bonding pad 132. The orthographic projection of the first bonding layer 133 on the first substrate 11 is spaced apart from the orthographic projections of the first bonding pad 131 and the second bonding pad 132 on the first substrate 11. The second bonding portion 23 further includes a second bonding layer 233, which surrounds the third bonding pad 231 and the fourth bonding pad 232. The orthographic projection of the second bonding layer 233 on the second substrate 21 is spaced apart from the orthographic projections of the first bonding pad 131 and the second bonding pad 132 on the second substrate 21. The first bonding layer 133 abuts against the second bonding layer 233. By providing a first bonding layer 133 on the first bonding portion 13 and a second bonding layer 233 on the second bonding portion 23, the first bonding layer 133 and the second bonding layer 233 are bonded together, thereby improving the bonding stability between the first bonding portion 13 and the second bonding portion 23, avoiding the risk of disconnection between the first bonding pad 131 and the third bonding pad 231, and between the second bonding pad 132 and the fourth bonding pad 232, and improving the stability of the operation of the light-emitting chip 40.

[0070] Furthermore, the first bonding layer 133 surrounds the first bonding pad 131 and the second bonding pad 132, and the second bonding layer 233 surrounds the third bonding pad 231 and the fourth bonding pad 232. This surrounding design provides additional protection for the bonding pads, preventing external structures from affecting the bonding between the pads during the bonding process, and also reducing the risk of pad breakage caused by external forces or thermal expansion during bonding and use. This reinforcement helps improve the mechanical stability and durability of the light-emitting chip 40. The introduction of the first bonding layer 133 and the second bonding layer 233 simplifies the bonding process in the fabrication of the light-emitting chip 40. The presence of the bonding layers allows for stable bonding at lower temperatures and pressures, avoiding the high temperature or high pressure conditions that may damage the light-emitting chip 40 in traditional bonding processes, thus reducing process difficulty and cost. The spacing between the first bonding layer 133 and the second bonding layer 233 and the bonding pads ensures isolation between different electrical networks, preventing short-circuit faults. This precise electrical isolation is essential for maintaining the normal operation of the complex circuits inside the chip.

[0071] It should be noted that the first bonding layer 133 surrounding the first bonding pad 131 and the second bonding pad 132 can include various configurations. It can be that the first bonding layer 133 is connected end-to-end to form a ring structure, with the first bonding pad 131 and the second bonding pad 132 surrounding its inner side. Alternatively, the first bonding layer 133 can be only a portion of the first bonding pad 131 and the second bonding pad 132. No specific limitation is made here. The first bonding layer 133 can be a continuous structure or a discontinuous structure. For example, the first bonding layer 133 may have a clearance interval to avoid the first connection line 14, thus preventing a short circuit between the first connection line 14 and the first bonding layer 133. Similarly, the second bonding layer 233 surrounding the third bonding pad 231 and the fourth bonding pad 232 can include various configurations. It can be that the second bonding layer 233 is connected end-to-end to form a ring structure, with the third bonding pad 231 and the fourth bonding pad 232 surrounding its inner side. Alternatively, the second bonding layer 233 can be only a portion of the second bonding layer surrounding the third bonding pad 231 and the fourth bonding pad 232. No specific limitation is made here. The second bonding layer 233 can be a continuous structure or a discontinuous structure. For example, the second bonding layer 233 has a clearance interval to avoid the third connecting line 25, so as to avoid a short circuit between the third connecting line 25 and the second bonding layer 233.

[0072] In some alternative embodiments, the portion of the first bonding layer 133 corresponding to the first connecting line 14 may be an insulating material to prevent a short circuit between the first bonding layer 133 and the first connecting line 14. For example, the first bonding layer 133 includes a metal sublayer and an insulating layer, with the insulating layer closer to the first connecting line 14 relative to the metal sublayer. Alternatively, the insulating layer may be located between the first connecting line 14 and the metal sublayer.

[0073] In some alternative embodiments, the portion of the second bonding layer 233 corresponding to the third connecting line 25 may be made of insulating material to prevent a short circuit between the second bonding layer 233 and the third connecting line 25. For example, the second bonding layer 233 includes a metal sublayer and an insulating layer, with the insulating layer closer to the third connecting line 25 relative to the metal sublayer. Alternatively, the insulating layer may be located between the third connecting line 25 and the metal sublayer.

[0074] In some optional embodiments, the first bonding layer 133 and the second bonding layer 233 are metal layers, and both the first bonding layer 133 and the second bonding layer 233 are connected to the ground layer. Setting the first bonding layer 133 and the second bonding layer 233 as metal layers improves the structural strength of the first bonding layer 133 and the second bonding layer 233, and facilitates stable bonding between the first bonding layer 133 and the second bonding layer 233. Metal layers have good thermal conductivity and can serve as part of a heat dissipation path, rapidly dissipating the heat generated during chip operation. The connection between the first bonding layer 133, the second bonding layer 233, and the ground layer forms a continuous heat transfer path, which helps improve the thermal stability of the entire light-emitting chip 40.

[0075] Furthermore, the first bonding layer 133 and the second bonding layer 233 are connected to the ground plane, which effectively provides a low-impedance path, reduces the potential difference between components, and avoids chip damage caused by static electricity or voltage fluctuations. Simultaneously, the first bonding layer 133 and the second bonding layer 233 can serve as effective electrostatic shielding layers, reducing the influence of external electromagnetic fields on the signals inside the driver integrated circuit layer, while also suppressing the radiation of internal signals outwards, protecting the chip from interference, and improving signal purity and stability. The arrangement of the first bonding layer 133 and the second bonding layer 233 effectively reduces interference during signal transmission, making it suitable for devices requiring high signal integrity, such as high-resolution printers and high-definition displays, significantly improving the signal transmission quality and printing / display effects of the device.

[0076] In some alternative embodiments, the first bonding layer 133 and the second bonding layer 233 may be made of materials such as palladium, gold, or palladium gold.

[0077] In some alternative embodiments, the first bonding layer 133 and the second bonding layer 233 can be manufactured using mature and cost-effective processes such as chemical vapor deposition (CVD) and sputtering. Compared with complex processes such as thin film stripping and transfer, the direct deposition of the metal layer and its connection to the ground layer simplifies the chip manufacturing process, reduces manufacturing costs and process difficulty, and improves production yield.

[0078] In some alternative embodiments, the first bonding layer 133, the first bonding pad 131, and the second bonding pad 132 are located on the same layer, that is, the first bonding layer 133, the first bonding pad 131, and the second bonding pad 132 can be formed in the same process step.

[0079] In some alternative embodiments, the second bonding layer 233, the third bonding pad 231, and the fourth bonding pad 232 are located on the same layer, that is, the second bonding layer 233, the third bonding pad 231, and the fourth bonding pad 232 can be formed in the same process step.

[0080] In some optional embodiments, the thickness of the first bonding layer 133 is greater than or equal to 100 nm and less than or equal to 200 nm; the width of the first bonding layer 133 is greater than or equal to 100 μm and less than or equal to 200 μm. Setting the thickness of the first bonding layer 133 between 100 nm and 200 nm ensures the shielding effect of the first bonding layer 133 on the inner first bonding pad 131 and second bonding pad 132, reducing static electricity generation. Setting the width of the first bonding layer 133 between 100 μm and 200 μm facilitates the bonding of the first bonding layer 133 and the second bonding layer 233 while avoiding the first bonding layer 133 occupying too much space, which would be detrimental to the miniaturization of the first semiconductor device 10.

[0081] In some optional embodiments, the thickness of the second bonding layer 233 is greater than or equal to 100 nm and less than or equal to 200 nm; the width of the second bonding layer 233 is greater than or equal to 100 μm and less than or equal to 200 μm. Setting the thickness of the second bonding layer 233 between 100 nm and 200 nm ensures the shielding effect of the second bonding layer 233 on the inner third bonding pad 231 and fourth bonding pad 232, reducing static electricity generation. Setting the width of the second bonding layer 233 between 100 μm and 200 μm facilitates the bonding between the first bonding layer 133 and the second bonding layer 233 while avoiding the first bonding layer 133 occupying too much space, which would be detrimental to the miniaturization of the first semiconductor device 10. Preferably, the widths of the first bonding layer 133 and the second bonding layer 233 are the same.

[0082] In some alternative embodiments, the first bonding pad 131 and the second bonding pad 132 are located on the same layer, while the first connection line 14 and the second connection line 16 are located on the same layer. However, the first bonding pad 131 and the first connection line 14 are located on different layers, with the first connection line 14 located between the first bonding pad 131 and the first substrate 11. The thickness of the first bonding layer 133 is the same as the sum of the thickness of the first bonding pad 131 and the thickness of the first connection line 14.

[0083] In some alternative embodiments, please refer to Figure 6 and Figure 7 The second semiconductor device 20 also includes a plurality of third connection lines 25. The two ends of each third connection line 25 are connected to the light-emitting driving sub-circuit and the third bonding pad 231, respectively. The third bonding pad 231 and the fourth bonding pad 232 are located on the same layer, but the third bonding pad 231 and the third connection lines 25 are located on different layers. The third connection lines 25 are located within the driving integrated circuit layer 22 between the third bonding pad 231 and the second substrate 21. The thickness of the second bonding layer 233 is the same as the sum of the thickness of the third bonding pad 231 and the thickness of the driving integrated circuit layer 22.

[0084] In some alternative embodiments, the third connection line 25 is formed inside the second semiconductor device 20, rather than as an external lead. For example, the third connection line 25 is a conductive thin film, which can be made of materials including gold, palladium, aluminum, polycrystalline silicon, conductive oxide, etc. Alternatively, the conductive thin film can be a single-layer film, such as a gold film, or a multi-layer film, such as a multi-layer film with titanium, platinum, and gold layers, or a multi-layer film with palladium and gold layers. When the third connection line 25, with a thickness of 0.5 μm and a width of 5 μm, passes through, it can provide several milliamps of current. The material, thickness, and width of the third connection line 25 can be designed according to the current requirements of the light-emitting element 12. The third connection line 25 is formed using chemical vapor deposition (CVD) or sputtering technology. Of course, the third connection line 25 can also be formed using other processes, which are not specifically limited here.

[0085] In some alternative embodiments, the third bonding pad 231 is connected to the end of the third connecting line 25. The width of the third bonding pad 231 is greater than the width of the third connecting line 25 to ensure a stable connection between the third bonding pad 231 and the third connecting line 25. At the same time, the size of the third bonding pad 231 is designed to be larger to reduce the bonding alignment tolerance when the first bonding pad 131 and the third bonding pad 231 are bonded, which is beneficial to improving the product yield.

[0086] In some alternative embodiments, the third bonding pad 231 can be a conductive thin film. The material of the third bonding pad 231 is the same as the material of the second bonding layer 233 or the material of the third connecting line 25, but it can also be a different material, as long as there is no inter-atomic diffusion between the different materials to avoid causing defects at the connection area.

[0087] In some optional embodiments, the thickness of the second bonding layer 233 is greater than or equal to 100 nm and less than or equal to 200 nm; the width of the second bonding layer 233 is greater than or equal to 100 μm and less than or equal to 200 μm. Setting the thickness of the second bonding layer 233 between 100 nm and 200 nm ensures the shielding effect of the second bonding layer 233 on the inner third bonding pad 231 and fourth bonding pad 232, reducing static electricity generation. Setting the width of the second bonding layer 233 between 100 μm and 200 μm facilitates the bonding between the first bonding layer 133 and the second bonding layer 233 while avoiding the second bonding layer 233 occupying too much space, which would be detrimental to the miniaturization of the second semiconductor device 20.

[0088] In some optional embodiments, the first semiconductor device 10 further includes a first bonding dielectric layer 17. The first bonding dielectric layer 17, the first bonding portion 13, and the light-emitting element 12 are located on the same side of the first substrate 11, and the surface of the first bonding portion 13 away from the first substrate 11 is flush with the surface of the first bonding dielectric layer 17 away from the first substrate 11. By providing the first bonding dielectric layer 17, and having the first bonding dielectric layer 17 flush with the first bonding portion 13, it is easier to bond the first semiconductor device 10 and the second semiconductor device 20, effectively reducing the difficulty of bonding them. In addition, the first bonding dielectric layer 17 can also isolate multiple electrical structures inside the first bonding portion 13, helping to reduce electromagnetic interference between signals. At the same time, the first bonding dielectric layer 17 can also protect the structure between it and the first substrate 11, reducing damage to the internal structure during bonding and other processes.

[0089] In some alternative embodiments, the first bonding dielectric layer 17 is an insulating layer to prevent short circuits between electrical structures in the first semiconductor device 10.

[0090] In some alternative embodiments, the first bonding medium layer 17 is a light-transmitting layer, and the first bonding medium layer 17 is located on the light-emitting element 12 to ensure that the light emitted by the light-emitting element 12 can be emitted from the first bonding medium layer 17.

[0091] In some alternative embodiments, the first bonding dielectric layer 17 has multiple through holes, and multiple light-emitting elements 12 are located at the multiple through holes to ensure that the light emitted by the light-emitting elements 12 can be emitted. In this embodiment, the first bonding dielectric layer 17 can be a light-transmitting layer or a non-light-transmitting layer.

[0092] In some alternative embodiments, please refer to Figures 6 to 9The second semiconductor device 20 further includes a second bonding dielectric layer 24. The second bonding dielectric layer 24 and the second bonding portion 23 are located on the same side of the second substrate 21, and the surface of the second bonding portion 23 away from the second substrate 21 is flush with the surface of the second bonding dielectric layer 24 away from the second substrate 21. The second bonding dielectric layer 24 is in contact with the first bonding dielectric layer 17. By providing the second bonding dielectric layer 24, and ensuring that the second bonding dielectric layer 24 is flush with the second bonding portion 23, it is easier to bond the first semiconductor device 10 and the second semiconductor device 20, effectively reducing the bonding difficulty between them. In addition, the second bonding dielectric layer 24 can also isolate multiple electrical structures inside the second bonding portion 23, helping to reduce electromagnetic interference between signals. At the same time, the second bonding dielectric layer 24 can also protect the structure between it and the second substrate 21, reducing damage to the internal structure during bonding and other processes.

[0093] In some alternative embodiments, please refer to Figure 2 and Figure 3 The first substrate 11 has a first bonding region 111. The orthographic projection of the first bonding portion 13 on the first substrate 11 is located within the first bonding region 111. The ratio of the width W2 of the first bonding region 111 to the width W1 of the first substrate 11 is greater than or equal to 0.3 and less than or equal to 0.5; the ratio of the length L2 of the first bonding region 111 to the length L1 of the first substrate 11 is greater than or equal to 0.5 and less than or equal to 1. This facilitates the optimization of the positional relationship between the first bonding region 111 and the light-emitting element 12, which is beneficial for a more compact structure of the first semiconductor device 10 and for reducing the size of the first semiconductor device 10. The compact design not only reduces the size of the device but also reduces its energy consumption and improves its energy efficiency. For portable printers, this design makes the device lighter and easier to carry. At the same time, the highly integrated design also extends the battery life of the device, improving its practicality.

[0094] In some alternative embodiments, the width W1 of the first substrate 11 is greater than or equal to 1.5 mm and less than or equal to 2.52 mm, and the length L1 of the first substrate 11 is greater than or equal to 9 mm and less than or equal to 15 mm. This arrangement is beneficial for miniaturization of the first semiconductor device 10. For example, the width W1 of the first substrate 11 is 2 mm, and the length L1 is 10.8288 mm.

[0095] In some alternative embodiments, the width W2 of the first joining region 111 is greater than or equal to 0.6 mm and less than or equal to 1 mm, and the length L2 of the first joining region 111 is greater than or equal to 6 mm and less than or equal to 13 mm. For example, the width W2 of the first joining region 111 is 0.8 mm and the length L2 is 7.84 mm.

[0096] In some optional embodiments, the minimum distance D between the light-emitting element 12 and the side of the first substrate 11 is greater than or equal to 3 μm and less than or equal to 5 μm. This ensures the miniaturization of the first semiconductor device 10 and avoids the influence of external structures on the light-emitting element 12, while effectively ensuring the spacing between the two light-emitting elements 12 on the side after the two light-emitting chips are installed and spliced ​​in a straight line.

[0097] In some alternative embodiments, the width of the first connecting line 14 is greater than or equal to 3 μm and less than or equal to 8 μm, and the thickness of the first connecting line 14 is greater than or equal to 0.3 μm and less than or equal to 0.8 μm, so as to ensure the current carrying capacity of the first connecting line 14 while reducing the size of the first connecting line 14.

[0098] In some alternative embodiments, the area of ​​the first bonding pad 131 is smaller than the area of ​​the second bonding pad 132 to ensure the current carrying capacity of the second bonding pad 132. For example, the size of the first bonding pad 131 is greater than or equal to 50um*60um and less than or equal to 70um*90um. For example, the size of the second bonding pad 132 is greater than or equal to 60um*80um and less than or equal to 90um*120um.

[0099] After the second semiconductor device 20 is bonded to the first semiconductor device 10, the second semiconductor device 20 is located within the first bonding region 111. The size of the second semiconductor device 20 is the same as the size of the first bonding region 111, and no further limitation is made here.

[0100] In one specific embodiment, the width W1 of the first substrate 11 is 2 mm and the length L1 is 10.8288 mm. The width W2 of the first bonding region 111 is 0.8 mm and the length L2 is 7.84 mm. The number of light-emitting elements 12 on the first substrate 11 is 256, the width W3 of the light-emitting elements 12 is 22.3 μm, the height H is 40 μm, and the arrangement period T is 42.3 μm, achieving 600 DPI. The minimum distance D between the light-emitting element 12 and the first substrate 11 is 5 μm; the width of the first connecting line 14 is preferably 5 μm, the thickness is 0.5 μm, and the minimum trace spacing of the first connecting line 14 is 5 μm; the size of the first bonding pad 131 is 60 μm * 80 μm, and the number of the first bonding pads 131 corresponds to the number of light-emitting elements 12, which is 256; the size of the second bonding pad 132 is 80 μm * 100 μm, and the number can be selected as 20; the number of further connecting terminals 15 corresponds to the second bonding pad 132, which is 20, and the size of the connecting terminals 15 can be selected as 80 μm * 100 μm. The width and length of the second substrate 21 are the same as the width and length of the first bonding area 111, while the size of the third connecting line 25 inside the second semiconductor device 20 is the same as the size of the first connecting line 14, the size and number of the third bonding pad 231 are the same as those of the first bonding pad 131, and the size and number of the fourth bonding pad 232 are the same as those of the second bonding pad 132.

[0101] Preferably, the materials at the junction of the first semiconductor device 10 and the second semiconductor device 20 are the same.

[0102] When the first semiconductor device 10 and the second semiconductor device 20 are joined, the second semiconductor device 20 can be placed upside down and joined to the second joint 23 through the first joint 13 to achieve electrical connection. Ohmic contact or contact with low resistivity is formed at the joint pad to form the light-emitting chip 40.

[0103] During the bonding process, after using conventional bonding techniques, a sintering process can be performed to ensure bonding strength, such as sintering at 250 degrees Celsius. This results in a strong structural connection between the bonding layer and the bonding pads. Simultaneously, sintering can reduce the contact resistance between the bonding pads to some extent.

[0104] The technical solution of this application mainly provides a light-emitting chip 40, whose manufacturing process does not involve the peeling and migration of thin films. This avoids the need for existing integrated chip thin film transfer technology and mass transfer technology, reduces the need for many expensive semiconductor manufacturing equipment such as thin film peeling, mass transfer, thin film migration, and repair, and reduces the high stability and high precision process requirements required for migration. This simplifies the manufacturing process and reduces the difficulty, thereby reducing the manufacturing cost of the light-emitting chip 40 and improving the light emission uniformity, reliability, and other performance characteristics of the light-emitting chip 40.

[0105] In some alternative embodiments, such as Figure 8 and Figure 9 In the illustrated embodiment, the first bonding portion 13 lacks a first bonding layer 133, instead having only first bonding pads 131 and second bonding pads 132. The second bonding portion 23 lacks a second bonding layer 233, instead having only third bonding pads 231 and fourth bonding pads 232. The surfaces of the first semiconductor device 10 and the second semiconductor device 20 are treated using appropriate chemical methods to remove contaminants and provide planarized surfaces, such as planarization to the atomic level of ≤2nm or higher. For example, the first bonding dielectric layer 17 is flush with the surface of the first bonding pads 131 and 132 on the side away from the first substrate 11, and the second bonding dielectric layer 24 is flush with the surface of the third bonding pads 231 and 232 on the side away from the second substrate 21. Subsequently, these two surfaces are brought into close contact and bonded together by heating and pressurization, resulting in close contact between objects of the same material. Simultaneously, the bonding pads also form ohmic contacts with low resistivity. At this point, in order to obtain an effective and firm bond, although the heating temperature is higher than the aforementioned bonding temperature with a bonding layer, the bonding layer growth process is omitted, and problems caused by bonding layer defects are also avoided.

[0106] In some alternative embodiments, such as Figure 1 In the embodiment shown, the length of the second semiconductor device 20 is less than the length of the first semiconductor device 10. This arrangement can reduce the amount of material used and lower the cost.

[0107] In some alternative embodiments, such as Figure 10 In the embodiment shown, the length of the second semiconductor device 20 can be the same as the length of the first semiconductor device 10, and the length of the first bonding region 111 can be the same as the length of the first substrate 11. This arrangement can effectively avoid the difference in local stress caused by the inconsistency in length between the first semiconductor device 10 and the second semiconductor device 20, which could lead to internal damage and defects. At the same time, this arrangement will increase the cost of raw materials. The design can be made according to specific usage requirements.

[0108] like Figure 11As shown, the semiconductor device 100 includes a substrate 30 and the aforementioned light-emitting chip 40, with the light-emitting chip 40 disposed on the substrate 30. A socket 50 can be mounted on the substrate 30, serving as an interface for communication between the substrate 30 and external systems to obtain power signals, clock signals, data signals, and other control signals required for the normal operation of the semiconductor device 100. The substrate 30 can be a rectangular substrate with printed circuit patterns, such as a ceramic substrate, PCB, or glass substrate. Specifically, the substrate 30 contains bonding pads electrically connected to the connection terminals 15 of the light-emitting chip 40, and these bonding pads are simultaneously connected to different circuit networks on the substrate 30. Furthermore, the substrate may preferably include other resistors, capacitors, memory chips, ESD chips, operational amplifier chips, etc., necessary for the operation of the semiconductor device 100.

[0109] like Figure 11 As shown, multiple light-emitting chips 40 can be attached to the same substrate 30. Multiple light-emitting chips 40 can be mounted in a straight line along the length of the substrate 30 using adhesives such as chip adhesive. The spacing between two adjacent light-emitting chips 40 is greater than or equal to 8 μm and less than or equal to 12 μm, so as to ensure that the distance between two adjacent light-emitting elements 12 in two adjacent light-emitting chips 40 is greater than or equal to 38 μm and less than or equal to 44 μm, further ensuring that the resolution of the semiconductor device 100 can reach 600 DPI.

[0110] The connection terminal 15 of the light-emitting chip 40 is bonded to the substrate 30 by gold wire bonding process and forms an electrical connection with the corresponding bonding pad, so that the circuit network on the substrate 30 is connected to the circuit inside the light-emitting chip 40, so as to provide various signals required for the normal operation of the light-emitting chip 40.

[0111] The number of light-emitting chips 40 attached to the semiconductor device 100 must be an integer, and the length of the semiconductor device 100 is not specifically limited. The arrangement of the multiple light-emitting chips 40 is not limited to a single-row linear arrangement, but can also be arranged in multiple rows, a houndstooth pattern, or any other arbitrary arrangement, and can be designed according to actual needs.

[0112] like Figure 12As shown, the light-emitting device 410 includes the aforementioned semiconductor device 100. The light-emitting device 410, having the semiconductor device 100, has high resolution. The light-emitting device 410 is, for example, an LED printhead. The light-emitting device 410 includes a frame 200 and a lens component 300. The frame 200 provides support and has a receiving cavity and a first opening 201 and a second opening 202 communicating with the receiving cavity. The first opening 201 and the second opening 202 are arranged opposite to each other, and the area of ​​the first opening 201 is smaller than the area of ​​the second opening 202. The semiconductor device 100 is disposed within the receiving cavity and located at the second opening 202. The lens component 300 is located at the first opening 201, and light emitted from the semiconductor device 100 is emitted through the lens component 300. The frame 200 is preferably made of a material with excellent heat dissipation properties to prevent performance degradation due to excessively high temperatures caused by poor heat dissipation during normal light-emitting operation.

[0113] Figure 13 The diagram shows a front view of a lens assembly 300, also known as a self-focusing lens or a radially variable refractive index lens, which mainly comprises a side support 301 and a cylindrical optical lens 302. The cylindrical optical lens 302 plays a primary role in the lens assembly 300, and its refractive index distribution gradually changes radially, providing focusing and imaging functions. Preferably, two rows of cylindrical optical lenses 302 are provided; alternatively, one, three, or four rows can also be used.

[0114] like Figure 14 As shown, the cylindrical optical lens 302 has focal points on both sides. The "object plane" mark indicates the first focal point, corresponding to the light-emitting surface of the array light-emitting element 12 inside the cavity, i.e., the surface of the first semiconductor device 10. The length of the focal point determines the distance between the light-emitting chip 40 and the lower surface of the lens component 300. The "image plane" mark indicates the second focal point, i.e., the image plane position on the other side of the cylindrical optical lens 302. This distance determines the position of the exposure area on the surface of the photosensitive drum when it is subsequently assembled into a printer. The light emitted by the light-emitting chip 40 is imaged upright by the lens component 300 and then onto the surface of the photosensitive drum of the printer to form a latent image through exposure on the surface of the photosensitive drum.

[0115] Preferably, the length of the light-emitting device 410 is the same as the length of the semiconductor device 100, and is determined by the specific parameters and functional requirements of the light-emitting device 410, such as the printing area, and is not specifically limited. Among them, the light-emitting chip 40 is a key component of the light-emitting device 410, and its cost determines the price of the light-emitting device 410.

[0116] like Figure 15 As shown, the imaging printing apparatus includes the aforementioned light-emitting device 410. The imaging printing apparatus can be a printer.

[0117] Figure 15This is a schematic diagram of an imaging printing device, which mainly includes the aforementioned light-emitting device 410, photosensitive drum 420, charging roller 430, toner cartridge 440, transfer roller 450, fixing roller 460, paper receiving component 470, and paper feeding component 480. A layer of photosensitive semiconductor material, such as selenium, is coated on the surface of the photosensitive drum 420. The photosensitive semiconductor material is an insulator in the absence of light, but becomes a conductor when exposed to light. During printing, the photosensitive drum 420 rotates at a constant speed. First, a high voltage is generated by a high-voltage circuit, and this high voltage is used to charge the surface of the photosensitive drum 420 through the charging roller 430, causing the surface of the photosensitive drum 420 to be uniformly charged. After the photosensitive drum 420 is irradiated by the light from the light-emitting device 410, the charge in the irradiated area disappears, while the unirradiated areas remain charged. The light emitted by the light-emitting device 410 is modulated according to the image data received by the imaging printing device, thus forming a latent image on the surface of the photosensitive drum 420. The toner in the toner cartridge 440 is charged with the same polarity as the photosensitive drum 420. When the photosensitive drum 420 passes over the toner cartridge 440, according to the principle that like charges repel and unlike charges attract, the toner in the toner cartridge 440 is attracted to the light-illuminated area of ​​the photosensitive drum 420, while the unilluminated area remains untouched, thus developing the image. When the inked photosensitive drum 420 rotates to the paper surface, the toner is transferred onto the paper by the oppositely charged transfer roller 450 underneath. After being heated by the fixing roller 460, the toner melts and penetrates into the printing paper, forming a stable image. The light-emitting device 410 is a key component of the imaging printing equipment and is a significant part of the production cost of the imaging printing equipment.

[0118] As can be seen from the above, by utilizing the technical solution of this application, compared with the light-emitting device 410 containing existing conventional semiconductor composite chips, this application reduces the complexity of semiconductor chip manufacturing process, saves the manufacturing process cost of light-emitting device 410, and further reduces the production cost of imaging printing equipment.

[0119] Specifically, the imaging printing device achieves a resolution of 600 DPI. Further, by using a multi-row, bird-and-bird arrangement of the light-emitting elements 12 or mounting the light-emitting chips 40 in a bird-and-bird pattern, and by further densifying the light-emitting elements 12, a resolution of 1200 DPI or higher can be achieved. The imaging printing device with the aforementioned light-emitting device 410 has excellent resolution.

[0120] Obviously, the embodiments described above are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0121] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0122] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0123] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A light-emitting chip, characterized in that, include: A first semiconductor device (10) includes a first substrate (11) and a plurality of light-emitting elements (12) disposed on the first substrate (11) and a first bonding portion (13), wherein the first bonding portion (13) is electrically connected to the plurality of light-emitting elements (12). The second semiconductor device (20) includes a second substrate (21) and a driving integrated circuit layer (22) and a second bonding portion (23) disposed on the second substrate (21). The driving integrated circuit layer (22) is electrically connected to the second bonding portion (23), and the first bonding portion (13) is bonded to the second bonding portion (23).

2. The light-emitting chip according to claim 1, characterized in that, The first joint (13) includes: Multiple first bonding pads (131) are provided, and each first bonding pad (131) is electrically connected to a first electrode of a plurality of light-emitting elements (12) in a one-to-one correspondence. At least one second bonding pad (132) is provided, each second bonding pad (132) being electrically connected to the second electrode of at least one of the light-emitting elements (12), and the first bonding pad (131) and the second bonding pad (132) abut against the second bonding portion (23).

3. The light-emitting chip according to claim 2, characterized in that, The first semiconductor device (10) further includes: Multiple first connection lines (14) are provided, one end of which is connected to the first bonding pad (131), and the other end of which is connected to the first electrode of the light-emitting element (12).

4. The light-emitting chip according to claim 2, characterized in that, The first semiconductor device (10) further includes at least one connection terminal (15) for connecting to an external signal source, and each of the connection terminals (15) is electrically connected to each of the second bonding pads (132).

5. The light-emitting chip according to claim 4, characterized in that, The first semiconductor device (10) further includes at least one second connection line (16), one end of the second connection line (16) being connected to the second bonding pad (132), and the other end of the second connection line (16) being connected to the connection terminal (15).

6. The light-emitting chip according to claim 2, characterized in that, Multiple first bonding pads (131) are arranged in an array.

7. The light-emitting chip according to claim 2, characterized in that, The driving integrated circuit layer (22) includes multiple light-emitting driving sub-circuits and at least one control processing sub-circuit, and the second junction (23) includes: Multiple third bonding pads (231) are electrically connected to the output ports of multiple light-emitting driving sub-circuits, and the multiple third bonding pads (231) are correspondingly abutted against the multiple first bonding pads (131). At least one fourth bonding pad (232), at least one of the control processing sub-circuits is electrically connected to the fourth bonding pad (232), and each of the fourth bonding pads (232) abuts against each of the second bonding pads (132).

8. The light-emitting chip according to claim 7, characterized in that, The first bonding portion (13) further includes a first bonding layer (133), the first bonding layer (133) surrounds the first bonding pad (131) and the second bonding pad (132), and the orthographic projection of the first bonding layer (133) on the first substrate (11) is spaced apart from the orthographic projection of the first bonding pad (131) on the first substrate (11) and the orthographic projection of the second bonding pad (132) on the first substrate (11); The second bonding portion (23) further includes a second bonding layer (233), which surrounds the first bonding pad (131) and the second bonding pad (132). The orthographic projection of the second bonding layer (233) on the second substrate (21) is spaced apart from the orthographic projection of the first bonding pad (131) on the second substrate (21) and the orthographic projection of the second bonding pad (132) on the second substrate (21). The first bonding layer (133) abuts against the second bonding layer (233).

9. The light-emitting chip according to claim 8, characterized in that, The light-emitting chip (40) satisfies at least one of the following: The first bonding layer (133) and the second bonding layer (233) are metal layers, and the first bonding layer (133) and the second bonding layer (233) are connected to the ground layer; The thickness of the first bonding layer (133) is greater than or equal to 100 nm and less than or equal to 200 nm; The width of the first bonding layer (133) is greater than or equal to 100 μm and less than or equal to 200 μm; The thickness of the second bonding layer (233) is greater than or equal to 100 nm and less than or equal to 200 nm; The width of the second bonding layer (233) is greater than or equal to 100 μm and less than or equal to 200 μm.

10. The light-emitting chip according to any one of claims 1 to 9, characterized in that, The first semiconductor device (10) further includes a first bonding dielectric layer (17), the first bonding dielectric layer (17), the first bonding portion (13) and the light-emitting element (12) are located on the same side of the first substrate (11), and the surface of the first bonding portion (13) away from the first substrate (11) is flush with the surface of the first bonding dielectric layer (17) away from the first substrate (11).

11. The light-emitting chip according to claim 10, characterized in that, The second semiconductor device (20) further includes a second bonding dielectric layer (24), the second bonding dielectric layer (24) and the second bonding portion (23) are located on the same side of the second substrate (21), and the surface of the second bonding portion (23) away from the second substrate (21) is flush with the surface of the second bonding dielectric layer (24) away from the second substrate (21), and the second bonding dielectric layer (24) is in contact with the first bonding dielectric layer (17).

12. The light-emitting chip according to any one of claims 1 to 9, characterized in that, The first substrate (11) has a first bonding region (111), and the orthographic projection of the first bonding portion (13) on the first substrate (11) is located within the first bonding region (111). The ratio of the width W2 of the first bonding region (111) to the width W1 of the first substrate (11) is greater than or equal to 0.3 and less than or equal to 0.

5. The ratio of the length L2 of the first bonding region (111) to the length L1 of the first substrate (11) is greater than or equal to 0.5 and less than or equal to 1.

13. A semiconductor device, characterized in that, include: substrate(30); At least one light-emitting chip (40) as described in any one of claims 1 to 12, the light-emitting chip (40) being disposed on the substrate (30).

14. A light-emitting device, characterized in that, Includes the semiconductor device (100) as described in claim 13.

15. An imaging printing device, characterized in that, Includes the light-emitting device (410) as described in claim 14.

16. The imaging printing apparatus according to claim 15, characterized in that, The resolution of the imaging printing device is at least 600 DPI.

Images