GaN packaging structure of SOP12-packaged 9-pin sealed power supply chip
By using an SOP12 package structure that combines power GaN transistors and GaN driver chips, the problems of large package space and poor heat dissipation are solved, achieving high power control and improved reliability, thus meeting the needs of high-density electronic products.
Patent Information
- Application Number
- CN202423062891.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2026-02-03
- Estimated Expiration
- 2034-12-12
AI Technical Summary
Conventional GaN power management chip packages suffer from large footprint, poor heat dissipation, and difficulty in thermal management, which affect product lifespan and reliability, and cannot meet the needs of high-density, highly integrated electronic products.
The GaN package structure of the power chip adopts the SOP12 package and a 9-pin co-package, which co-packages the power GaN transistor and the GaN driver chip, eliminates the traditional 8th and 10th pins, and combines the 11th and 12th pins for heat dissipation. The pins are bonded to the base island surface with conductive adhesive, and the pin design is optimized to meet the high power control requirements.
It fulfills the requirements for high-power GaN drive control, saves design area, improves reliability, provides more control pin access, adapts to complex application scenarios, and can achieve multi-chip packaging without 3D packaging.
Smart Images
Figure CN223872755U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, specifically to a GaN package structure for a 9-pin SOP12 packaged power supply chip. Background Technology
[0002] As modern semiconductor technology develops towards high density and high integration, electronic components are becoming smaller and thinner. Semiconductor devices are becoming flatter and have higher power density as electronic products become smaller. However, conventional products are not encapsulated, occupy a lot of space, and cause serious interference during operation, affecting product life and reliability. They can no longer meet the needs of the rapidly developing market.
[0003] The main function of GaN power management chips is to convert AC power into a stable DC voltage through the high-frequency power of external components. However, the forward voltage of GaN power management chips is reduced by more than half compared to conventional MOSFETs, effectively reducing their own power consumption under full load. For high-power applications, thermal management may also face challenges. There is a thermal gradient between multiple chips, and the heat transfer and heat dissipation are not efficient enough, which can lead to a decrease in overall system performance. Under the background of the country's vigorous promotion of energy conservation, emission reduction and energy consumption reduction, there is an urgent need for an SOP12 packaged GaN power management chip. Utility Model Content
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a GaN package structure for a 9-pin SOP12 packaged power supply chip. To solve the above-mentioned technical problems, this invention adopts the following technical solution:
[0005] A GaN package structure for a 9-pin SOP12 packaged power supply chip includes:
[0006] A first base island, on one side of which a GaN control chip and a power GaN transistor are respectively disposed. The GaN control chip and the power GaN transistor chip are arranged vertically. The power GaN transistor is provided with a gate G, a source S and a drain D.
[0007] The interface includes input terminals SW, HV, and VCC, output terminals CS, VS, and FB, ground terminals GND1 and GND2, and a control pin G. Each interface terminal is led out by nine sets of pins, including pins 1, 2, 3, 4, 5, 6, 7, 9, 11, and 12. Pins 11 and 12 in the package structure are combined into one pin. Pin GND2 is used for heat dissipation. The nine sets of pins are connected to the interface terminals respectively. The control terminal VS is led out from pin 1, the control terminal FB is led out from pin 2, the input terminal VCC is led out from pin 3, the ground terminal GND1 is led out from pin 4, the output terminal CS is led out from pins 5 and 6, the input terminal SW is led out from pin 7, the input terminal HV is led out from pin 9, and the ground terminal GND2 is led out from pins 11 and 12, i.e., pin GND2.
[0008] Preferably, an insulating layer for isolation is provided between the first base island and the input terminal SW, input terminal HV, input terminal VCC, output terminal CS, control terminal VS, control terminal FB and control pin G.
[0009] Preferably, the control terminal VS of the GaN control chip is connected to pin 1 of the package, the control terminal FB of the GaN control chip is connected to pin 2 of the package, the input terminal VCC of the GaN control chip is connected to pin 3 of the package, the ground terminal GND1 of the GaN control chip is connected to pin 4 of the package, the ground terminal GND2 of the first base island is connected to pin GND2 of the package, the output terminal CS of the GaN control chip is connected to pin 5 of the package, the input terminal HV of the GaN control chip is connected to pin 9 of the package, the gate G of the power GaN transistor is connected to the control pin G of the packaged GaN control chip, the source S of the power GaN transistor is connected to pin 6 of the package, and the drain D of the power GaN transistor is connected to pin 7 of the package.
[0010] Preferably, the first, second, third, fourth, fifth, and sixth pins are symmetrically arranged on both sides of the package structure with the seventh, ninth, and GND2 pins to form a GaN package structure for a 9-pin SOP12 packaged power chip.
[0011] Preferably, the first, second, third, fourth, and fifth pins are respectively connected to the bonding points of the interface terminals VS, FB, VCC, GND1, and CS of the GaN control chip via wire bonding. The bonding point of the control pin G of the GaN control chip is connected to the gate G of the power GaN transistor via wire bonding. The drain D of the power GaN transistor is connected to the seventh pin via wire bonding. The source S of the power GaN transistor is connected to the sixth pin via wire bonding.
[0012] Preferably, the wire diameter of the bonding wire is 1.1 micrometers, and the thickness of the bonding point of the GaN control chip is 1.8 micrometers.
[0013] Preferably, the back of the chip at the first base island location has exposed copper foil, which allows the back of the chip to be directly soldered onto the PCB board during application, ensuring excellent and balanced heat dissipation performance.
[0014] Preferably, the GaN control chip and the power GaN transistor are both bonded to the surface of the first base island using conductive adhesive.
[0015] Beneficial effects: This utility model provides an SOP12 packaged GaN power management chip packaging structure. By encapsulating the power GaN transistor and the GaN driver chip, the 8th and 10th pins of the traditional technology are eliminated to ensure high voltage safety distance. The 11th and 12th pins of the traditional packaging structure are combined for heat dissipation. The pins are optimized to the maximum extent while meeting the requirements of high-power GaN drive control. It can meet the requirements of high-power fast GaN control, save design area, improve reliability, and provide more control pin access to adapt to more complex application scenarios. Multi-chip packaging can be achieved in one package without the need for 3D form. Attached Figure Description
[0016] The accompanying drawings are provided to further understand the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation thereof.
[0017] In the attached diagram:
[0018] Figure 1 This is a schematic diagram of the GaN package structure of the SOP12 packaged 9-pin co-packaged power chip of this utility model.
[0019] The following pins are labeled in the diagram: 1. GaN control chip; 2. Power GaN transistor; 3. First base island; 4. Control terminal VS; 5. Control terminal FB; 6. Input terminal VCC; 7. Ground terminal GND1; 8. Output terminal CS; 9. Control pin G; 10. Gate G; 11. Source S; 12. Drain D; 13. Input terminal HV; 14. Pin 1; 15. Pin 2; 16. Pin 3; 17. Pin 4; 18. Pin 5; 19. Pin 6; 20. Pin 7; 21. Pin 9; 22. Pin GND2. Detailed Implementation
[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, and not all of the embodiments. The following text is only used to describe a GaN package structure of a SOP12 packaged 9-pin co-packaged power chip of the present utility model, and does not strictly limit the protection scope of the specific claims of the present utility model.
[0021] Example: Figure 1 As shown, a GaN package structure for a 9-pin SOP12 packaged power supply chip includes:
[0022] A first base island 3 is provided on one side of a GaN control chip 1 and a power GaN transistor 2. The GaN control chip 1 and the power GaN transistor 2 are arranged vertically. The power GaN transistor 2 is provided with a gate G, a source S and a drain D.
[0023] The interface includes input terminals SW, HV13, and VCC6, output terminal CS8, control terminals VS4 and FB5, ground terminals GND17 and GND2, and control pin G9. Each interface terminal is led out by nine sets of pins, including pins 14, 15, 16, 17, 18, 19, 20, 21, 11, and 12. Pins 11 and 12 in the package structure are combined into a single pin. GND222 is used for heat dissipation. Nine sets of pins are connected to the interface terminals respectively. The control terminal VS4 is led out from pin 14, the control terminal FB5 is led out from pin 15, the input terminal VCC6 is led out from pin 16, the ground terminal GND17 is led out from pin 17, the output terminal CS8 is led out from pins 18 and 19, the input terminal SW is led out from pin 20, the input terminal HV13 is led out from pin 21, and the ground terminal GND2 is led out from pins 11 and 12, i.e., pin GND222.
[0024] In this embodiment, an insulating layer is provided between the first base island 3 and the input terminal SW, input terminal HV13, input terminal VCC6, output terminal CS8, control terminal VS4, control terminal FB5 and control pin G9 for isolation.
[0025] In this embodiment, the control terminal VS4 of the GaN control chip 1 is connected to pin 14 of the package; the control terminal FB5 of the GaN control chip 1 is connected to pin 15 of the package; the input terminal VCC6 of the GaN control chip 1 is connected to pin 16 of the package; the ground terminal GND17 of the GaN control chip 1 is connected to pin 17 of the package; the ground terminal GND2 of the first base island 3 is connected to pin GND222 of the package; the output terminal CS8 of the GaN control chip 1 is connected to pin 18 of the package; the input terminal HV13 of the GaN control chip 1 is connected to pin 21 of the package; the gate G10 of the power GaN transistor 2 is connected to the control pin G9 of the packaged GaN control chip 1; the source S11 of the power GaN transistor 2 is connected to pin 19 of the package; and the drain D12 of the power GaN transistor 2 is connected to pin 20 of the package.
[0026] In this embodiment, pins 14, 25, 36, 47, 58, and 619 are symmetrically arranged on both sides of the package structure with pins 7, 9, and GND222, forming a GaN package structure for a 9-pin SOP12 packaged power chip.
[0027] In this embodiment, pins 14, 25, 36, 47, and 58 are respectively connected to the bonding points of the interface terminals VS, FB, VCC, GND1, and CS of the GaN control chip 1 via wire bonding. The bonding point of the control pin G9 of the GaN control chip 1 is connected to the gate G10 of the power GaN transistor 2 via wire bonding. The drain D12 of the power GaN transistor 2 is connected to pin 7 20 via wire bonding. The source S11 of the power GaN transistor 2 is connected to pin 6 19 via wire bonding.
[0028] In this embodiment, the wire diameter of the bonding wire is 1.1 micrometers, and the bonding point thickness of the GaN control chip 1 is 1.8 micrometers.
[0029] In this embodiment, the back of the chip at the first base island 3 position has exposed copper foil, which allows the back of the chip to be directly soldered onto the PCB board during application, ensuring excellent and balanced heat dissipation performance.
[0030] In this embodiment, both the GaN control chip 1 and the power GaN transistor 2 are bonded to the surface of the first base island 3 with conductive adhesive.
[0031] This invention eliminates the 8th and 10th pins of the traditional technology to ensure a high-voltage safety distance by encapsulating the power GaN transistor 2 and the GaN driver chip 1 together. It also combines the 11th and 12th pins of the traditional packaging structure for heat dissipation. This design optimizes the pin count to the maximum extent while meeting the high-power GaN drive control requirements, and provides more control pin access.
[0032] It should be noted that the specific model and size of the power GaN transistor 2 and GaN control chip 1 used in the packaging structure proposed in this utility model can be determined according to the actual application environment and system parameter requirements. The above is only one possible specific method and is not intended to limit the scope of its actual implementation.
[0033] The embodiments of the present utility model have been described in detail above with reference to the accompanying drawings. However, the present utility model is not limited to the above embodiments. For those skilled in the art, after learning the contents of the present utility model, they can make several equivalent changes and substitutions without departing from the principle of the present utility model. These equivalent changes and substitutions should also be considered to fall within the protection scope of the present utility model.
Claims
1. A GaN package structure for a 9-pin SOP12 packaged power supply chip, characterized in that: include: A first base island, on one side of which a GaN control chip and a power GaN transistor are respectively disposed. The GaN control chip and the power GaN transistor chip are arranged vertically. The power GaN transistor is provided with a gate G, a source S and a drain D. The interface includes input terminals SW, HV, and VCC, output terminals CS, VS, and FB, ground terminals GND1 and GND2, and a control pin G. Each interface terminal is led out by nine sets of pins, including pins 1, 2, 3, 4, 5, 6, 7, 9, 11, and 12. Pins 11 and 12 in the package structure are combined into one pin. Pin GND2 is used for heat dissipation. The nine sets of pins are connected to the interface terminals respectively. The control terminal VS is led out from pin 1, the control terminal FB is led out from pin 2, the input terminal VCC is led out from pin 3, the ground terminal GND1 is led out from pin 4, the output terminal CS is led out from pins 5 and 6, the input terminal SW is led out from pin 7, the input terminal HV is led out from pin 9, and the ground terminal GND2 is led out from pins 11 and 12, i.e., pin GND2.
2. The GaN package structure of a 9-pin SOP12 packaged power supply chip according to claim 1, characterized in that: An insulating layer is provided between the first base island and the input terminals SW, HV, VCC, CS, VS, FB, and G for isolation.
3. The GaN package structure of a 9-pin SOP12 packaged power chip according to claim 1, characterized in that: The control terminal VS of the GaN control chip is connected to pin 1 of the package; the control terminal FB of the GaN control chip is connected to pin 2 of the package; the input terminal VCC of the GaN control chip is connected to pin 3 of the package; the ground terminal GND1 of the GaN control chip is connected to pin 4 of the package; the first base island ground terminal GND2 is connected to pin GND2 of the package; the output terminal CS of the GaN control chip is connected to pin 5 of the package; the input terminal HV of the GaN control chip is connected to pin 9 of the package; the gate G of the power GaN transistor is connected to the control pin G of the packaged GaN control chip; the source S of the power GaN transistor is connected to pin 6 of the package; and the drain D of the power GaN transistor is connected to pin 7 of the package.
4. The GaN package structure of a 9-pin SOP12 packaged power supply chip according to claim 1, characterized in that: Pins 1, 2, 3, 4, 5, and 6 are symmetrically arranged on both sides of the package structure with pins 7, 9, and GND2.
5. The GaN package structure of a 9-pin SOP12 packaged power supply chip according to claim 1, characterized in that: Pins 1, 2, 3, 4, and 5 are respectively connected to the interface terminals VS, FB, VCC, GND1, and CS of the GaN control chip via wire bonding. The control pin G of the GaN control chip is connected to the gate G of the power GaN transistor via wire bonding. The drain D of the power GaN transistor is connected to pin 7 via wire bonding. The source S of the power GaN transistor is connected to pin 6 via wire bonding.
6. The GaN package structure of a 9-pin SOP12 packaged power supply chip according to claim 5, characterized in that: The wire diameter of the bonding wire is 1.1 micrometers, and the thickness of the bonding point of the GaN control chip is 1.8 micrometers.
7. The GaN package structure of a 9-pin SOP12 packaged power supply chip according to claim 1, characterized in that: The back of the chip at the first base island location has exposed copper.
8. The GaN package structure of a 9-pin SOP12 packaged power supply chip according to claim 1, characterized in that: Both the GaN control chip and the power GaN transistor are bonded to the surface of the first base island using conductive adhesive.