Basepad frame for sealing multiple transistors

Abstract

The utility model discloses a base island frame used for sealing multiple transistors, comprising a first base island used for bearing a first power device and guiding out heat of the first power device; the high-voltage pin group comprises a first high-voltage pin, and the first high-voltage pin is electrically connected with the first base island; the second high-voltage pin is used for bearing a second power device and bearing part of high-voltage signal bonding wires of the first power device, and the second power device is electrically connected with the first base island; the second base island is used for bearing a main control chip, and the main control chip is electrically connected with the first power device and the second power device; and the low-voltage pin group is electrically connected with the second base island. The multi-transistor packaging structure is novel in structure, can achieve the purpose of multi-transistor packaging, achieves the purposes of compact power supply and peripheral system BOM cost saving, and is stable in heating.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a base island framework for multi-transistor co-packing. Background Technology

[0002] Co-packaging is commonly seen in the co-packaging of MOSFETs and main control chips, and also in the co-packaging of bridge diodes in low-power devices. It is generally used in low-power ACDC products in flyback or BUCK circuits. In ACDC products with a power rating greater than 100W, co-packaging is less common, mainly due to the increased heat generation and size of power devices, while the number of available package base islands is decreasing.

[0003] In ACDC products exceeding 100W, reducing power supply size and BOM cost through increased integration of the main control chip and peripheral components is a major direction in power supply development. With the widespread adoption of third-generation semiconductors, miniaturized high-power ACDC power supplies are rapidly entering the market. Achieving miniaturization and reduced production costs through power device upgrades remains a key challenge. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned technical problems existing in the prior art and to provide a base island frame for multi-transistor co-packing. The structure is novel and can achieve the purpose of multi-transistor co-packing, thereby achieving a compact power supply, saving system BOM costs, and stable heat generation.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A base island framework for multi-transistor co-packing, characterized in that it comprises:

[0007] The first base island is used to support the first power device and dissipate the heat of the first power device;

[0008] High-voltage pin group, the high-voltage pin group includes:

[0009] The first high-voltage pin is electrically connected to the first base island;

[0010] The second high-voltage pin is used to carry the high-voltage signal wire of the second power device and to receive part of the high-voltage signal of the first power device. The second power device is electrically connected to the first base island.

[0011] The second base island is used to carry the main control chip, and the main control chip is electrically connected to the first power device and the first power device.

[0012] The low-voltage pin group is electrically connected to the second base island.

[0013] Furthermore, there is a first gap between the high-voltage pin group and the low-voltage pin group, which meets the requirements of high-voltage insulation gap.

[0014] Furthermore, the first spacing is greater than 2mm. The reasonable spacing design greatly reduces the risk of voltage breakdown and air discharge due to insufficient spacing.

[0015] Furthermore, there is a second gap between the first high-voltage pin and the second high-voltage pin, which meets the requirements for high-voltage insulation gap.

[0016] Furthermore, the second spacing is greater than 2mm. The reasonable spacing design greatly reduces the risk of voltage breakdown and air discharge due to excessively small spacing.

[0017] Furthermore, the low-voltage pin group includes a first low-voltage pin, a second low-voltage pin, a third low-voltage pin, a fourth low-voltage pin, and a fifth low-voltage pin, with a third spacing between adjacent low-voltage pins, which has the advantages of ensuring electrical safety and reducing signal interference.

[0018] Furthermore, the third low-voltage pin is electrically connected to the second base island, ensuring smooth signal output during wire bonding while maintaining a reasonable area and reliable placement of the main control chip.

[0019] Furthermore, the third spacing is greater than 0.5mm. A reasonable spacing design can prevent electrical short circuits between adjacent low-voltage pins and reduce signal interference between adjacent low-voltage pins.

[0020] Furthermore, the first low-voltage pin, the second low-voltage pin, the third low-voltage pin, the fourth low-voltage pin, and the fifth low-voltage pin are arranged in a left-right sequence, with clear wiring.

[0021] Furthermore, the first low-voltage pin, the second low-voltage pin, the third low-voltage pin, the fourth low-voltage pin, and the fifth low-voltage pin are arranged in a front-to-back sequence, which reduces the area occupied and is more conducive to wiring.

[0022] This utility model, by adopting the above-mentioned technical solution, has the following beneficial effects:

[0023] 1. Electrical isolation between the two base islands prevents breakdown between pins caused by large voltage differences, thus meeting packaging or reliability requirements.

[0024] 2. This utility model is applicable to all bridge packages and can also be used for co-packaging of different power ranges. Different packages can be selected for different power ranges of ACDC power supplies, which can achieve the purpose of co-packaging multiple transistors, thereby achieving a compact power supply, saving system BOM costs, and ensuring stable heat dissipation. Attached Figure Description

[0025] The present invention will be further described below with reference to the accompanying drawings:

[0026] Figure 1 This is a schematic diagram of the base island frame for multi-transistor co-packing according to the present invention;

[0027] Figure 2 This is a side view of the present invention.

[0028] In the diagram: A - First base island; B - Second base island; 1 - First low-voltage pin; 2 - Second low-voltage pin; 3 - Third low-voltage pin; 4 - Fourth low-voltage pin; 5 - Fifth low-voltage pin; 6 - Second high-voltage pin; 7 - First high-voltage pin. Detailed Implementation

[0029] like Figure 1 As shown, this utility model discloses a base island frame for multi-transistor co-packing, comprising: a first base island A, a high-voltage pin group, a second base island B, and a low-voltage pin group. The first base island A is used to support the first power device and dissipate the heat dissipated by the first power device. The shape of the first base island A is enlarged according to actual conditions to facilitate heat conduction and reliable placement of the larger first power device. When the first base island A is exposed, a back-gold coating process is used; when the first base island A is not exposed, a molding process is used.

[0030] The second base island B is used to carry the main control chip, which is electrically connected to the first power device and the first power device.

[0031] The high-voltage pin group includes a first high-voltage pin 7 and a second high-voltage pin 6. The first high-voltage pin 7 is electrically connected to the first base island A. The second high-voltage pin 6 is used to carry the second power device and receive the high-voltage signal bonding wire of part of the first power device. The second power device is electrically connected to the first base island A.

[0032] There is a second gap between the first high-voltage pin 7 and the second high-voltage pin 6. The second gap is greater than 2mm. The reasonable design of the gap greatly reduces the risk of voltage breakdown and air discharge due to the gap being too small, and meets the requirements of high-voltage insulation gap.

[0033] The low-voltage pin group includes a first low-voltage pin 1, a second low-voltage pin 2, a third low-voltage pin 3, a fourth low-voltage pin 4, and a fifth low-voltage pin 5. The first low-voltage pin 1, the second low-voltage pin 2, the third low-voltage pin 3, the fourth low-voltage pin 4, and the fifth low-voltage pin 5 are arranged in a left-right sequence, which makes the wiring clear; or the first low-voltage pin 1, the second low-voltage pin 2, the third low-voltage pin 3, the fourth low-voltage pin 4, and the fifth low-voltage pin 5 are arranged in a front-back sequence, which reduces the occupied area and is more conducive to wiring.

[0034] There is a third gap between two adjacent low-voltage pins, which is greater than 0.5mm. The reasonable design of the gap can prevent electrical short circuits between adjacent low-voltage pins and reduce signal interference between adjacent low-voltage pins, thus ensuring electrical safety.

[0035] There is a first gap between the fifth low-voltage pin 5 and the second high-voltage pin 6. The first gap is greater than 2mm. The reasonable design of the gap greatly reduces the risk of voltage breakdown and air discharge due to the gap being too small, and meets the requirements of high-voltage insulation gap.

[0036] The third low-voltage pin 3 is electrically connected to the second base island B, ensuring smooth signal output during wire bonding while maintaining a reasonable area and reliable placement of the main control chip.

[0037] like Figure 2 As shown, the pins of the high-voltage pin group and the low-voltage pin group can be designed as K-pins according to the layout. K-pins facilitate the wiring of the minimum circuits of power devices and signal circuits.

[0038] Electrical isolation between the two base islands prevents breakdown between pins caused by large voltage differences, thus meeting packaging or reliability requirements.

[0039] This invention is applicable to all bridge packages. For example, if the shape of the bridge package is selected as a GBU package shell, GBP package shell, KBP package shell or KBJ package shell, it can also be applied to the co-packaging of different power ranges. Different packages can be selected for different power ranges of ACDC power supplies to achieve the purpose of co-packaging multiple transistors, thereby achieving the purpose of compact power supply, saving system BOM costs, and stable heat dissipation.

[0040] The above are merely specific embodiments of this utility model, but the technical features of this utility model are not limited thereto. Any simple changes, equivalent substitutions, or modifications made based on this utility model to solve essentially the same technical problems and achieve essentially the same technical effects are all covered within the protection scope of this utility model.

Claims

1. A base island frame for multi-transistor co-packing, characterized in that, include: The first base island is used to support the first power device and dissipate the heat of the first power device; High-voltage pin group, the high-voltage pin group comprising: The first high-voltage pin is electrically connected to the first base island; The second high-voltage pin is used to carry the second power device and receive the high-voltage signal wire of part of the first power device. The second power device is electrically connected to the first base island. The second base island is used to carry the main control chip, which is electrically connected to the first power device and the second power device; A low-voltage pin group, which is electrically connected to the second base island.

2. The base island frame for multi-transistor co-packing according to claim 1, characterized in that: There is a first spacing between the high-voltage pin group and the low-voltage pin group.

3. The base island frame for multi-transistor co-packing according to claim 2, characterized in that: The first spacing is greater than 2mm.

4. The base island frame for multi-transistor co-packing according to claim 1, characterized in that: There is a second gap between the first high-voltage pin and the second high-voltage pin.

5. A base island frame for multi-transistor co-packing according to claim 4, characterized in that: The second spacing is greater than 2mm.

6. The base island frame for multi-transistor co-packing according to claim 1, characterized in that: The low-voltage pin group includes a first low-voltage pin, a second low-voltage pin, a third low-voltage pin, a fourth low-voltage pin, and a fifth low-voltage pin, with a third spacing between adjacent low-voltage pins.

7. A base island frame for multi-transistor co-packing according to claim 6, characterized in that: The third low-voltage pin is electrically connected to the second base island.

8. A base island frame for multi-transistor co-packing according to claim 6, characterized in that: The third spacing is greater than 0.5 mm.

9. A base island frame for multi-transistor co-packing according to claim 6, characterized in that: The first low-voltage pin, the second low-voltage pin, the third low-voltage pin, the fourth low-voltage pin, and the fifth low-voltage pin are arranged in a left-right sequence.

10. A base island frame for multi-transistor co-packing according to claim 6, characterized in that: The first low-voltage pin, the second low-voltage pin, the third low-voltage pin, the fourth low-voltage pin, and the fifth low-voltage pin are arranged in a front-to-back sequence.

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