Electrical test device and electrical test system

Abstract

The utility model provides an electrical test device and an electrical test system. The electrical test device is characterized in that a chip to be tested is arranged on the surface of one side of a test daughter board, and a pin header connector is arranged on the surface of the other side of the test daughter board; a female header connector is arranged on the surface of one side of the test mother board, the female header connector of the test mother board is connected to a pin header connector of the test daughter board to form a test assembly, a test control circuit is arranged on the surface of the other side of the test mother board, and the test control circuit is connected to the power end of the test daughter board through the female header connector and the pin header connector. The bias module is used for providing bias conditions for electrical testing for a power supply end; and a test assembly is arranged in the test box and is used for carrying out electrical test on the to-be-tested chip. Therefore, the operation difficulty can be reduced, the test efficiency can be improved, and the electrical test cost can be reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to electrical test technical field especially relates to a kind of electrical test device and electrical test system. BACKGROUND

[0002] In the related art, most of the high-reliability chip products need to be electrically tested. The purpose of electrical testing is to ensure the quality and reliability of the chip and to verify whether the design of the chip meets the specifications and requirements.

[0003] Currently, Socket aging seat and Tray disc can be used for chip electrical testing. However, when using Socket aging seat, the chip needs to be sucked and / or placed according to pin1. During the process of transferring the chip using Tray disc, the chip with a particularly small size is prone to be turned over and tilted during the vibration of the Tray disc, resulting in high operation difficulty, slow operation speed, and easy loss of samples during the process of taking the chip. Considering the development cost, the manufacturing cost of Socket aging seat and Tray disc is also very expensive. Therefore, how to set up an electrical test device to reduce the operation difficulty and improve the test efficiency, and reduce the electrical test cost is a problem to be solved. SUMMARY

[0004] Therefore, the utility model provides an electrical test device and electrical test system, which can reduce the operation difficulty and improve the test efficiency, and reduce the device cost.

[0005] In the first aspect, the utility model provides an electrical test device, which comprises: a test sub-board, one side surface of the test sub-board is provided with a to-be-tested chip, and the other side surface is provided with a pin connector; a test mainboard, one side surface of the test mainboard is provided with a female connector, the female connector of the test mainboard is connected to the pin connector of the test sub-board to form a test assembly, and the other side surface of the test mainboard is provided with a test control circuit, the test control circuit is connected to the power supply end of the test sub-board via the female connector and the pin connector, and is used for providing the power supply end with a bias condition for electrical testing; a test box, the test box is provided with the test assembly, and is used for electrically testing the to-be-tested chip.

[0006] The utility model provides a kind of electrical test system, comprising: test daughter board, the surface of one side of test daughter board is provided with to be measured chip, and the surface of other side is provided with pin connector;Test motherboard, the surface of one side of test motherboard is provided with pin connector, and the pin connector of test motherboard is connected to the pin connector of test daughter board to form test assembly, and, test motherboard is provided with test control circuit, test control circuit is connected to the power supply end of test daughter board via pin connector and pin connector, for providing electrical test bias condition to power supply end;Test box, test box is provided with test assembly, for carrying out electrical test to to be measured chip.

[0007] The utility model embodiment provides a kind of electrical test device and electrical test system.Compared with the test mode that Socket aging seat and Tray disc are combined, the test mode of test daughter board and test motherboard is used to carry out electrical test to to be measured chip, can reduce the test cost when to be measured chip is electrically tested, and because to be measured chip is set on test daughter board, it is relatively easy to take and place to be measured chip, chip and appearance damage are not easy to appear, to further improve test efficiency can be thus.Electrically test to be measured chip more close to actual application scene can be further improved the accuracy of the electrical test result of to be measured chip by being arranged in test box. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to make the technical scheme in the embodiments of the utility model or the related technical scheme clearer, the drawings needed to be used in the embodiment or the related technical description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments described in the embodiments of the utility model, and other drawings can be obtained by those skilled in the art according to these drawings.

[0009] Figure 1 It is the structure schematic diagram of a kind of electrical test device provided by the utility model embodiment;

[0010] Figure 2 It is the structure schematic diagram of a kind of electrical test system provided by the utility model embodiment. DETAILED DESCRIPTION

[0011] In order to make the technical scheme in the embodiments of the utility model or the related technical scheme clearer, the drawings needed to be used in the embodiment or the related technical description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments described in the embodiments of the utility model, and other drawings can be obtained by those skilled in the art according to these drawings.

[0012] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description is for describing the embodiments of the application only and is not intended to be limiting of the application.

[0013] In the following description, reference is made to the "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or a different subset of all possible embodiments and can be combined with each other without conflict.

[0014] It should also be noted that the terms "first", "second", "third" in the embodiments of the application are only used to distinguish similar objects, and do not represent a specific order of the objects. Understandably, "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

[0015] In addition, the term "and / or" in the embodiments of the application is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents an "or" relationship between the associated objects before and after it.

[0016] In order to facilitate the understanding of the technical scheme of the embodiments of the application, the related technologies of the embodiments of the application are described as follows, and the following related technologies can be combined with the technical scheme of the embodiments of the application in any way, which all belong to the protection scope of the embodiments of the application.

[0017] In the related art, most chip products need to be electrically tested. The process of electrical testing is to ensure that the chip can perform its function as expected through strict testing and verification means. The purpose of electrical testing is to ensure the quality and reliability of the chip and to verify whether the design of the chip meets the specifications and requirements.

[0018] At present, the size of chips is getting smaller and smaller, and the size of common chips is less than 1 millimeter (mm) x 1 mm. The electrical test of the chip faces new challenges. In the process of electrical test of the chip, Socket aging seat and Tray can be used for electrical test of the chip. However, the manufacturing cost of Socket aging seat and Tray is high and the manufacturing cycle is long. For the high-priced large-scale System on Chip (SoC), Central Processing Unit (CPU), Graphics Processing Unit (GPU) and other digital chips, the cost of Socket aging seat and Tray can be covered. However, for small size analog chips, the selling price is low and the gross profit rate is not high. If Socket aging seat and Tray are used for electrical test, the hardware cost will be multiplied (such as 3-5 times).

[0019] In addition, when using Socket aging seat, the chip needs to be sucked and placed according to pin1. For small size chips, the operation difficulty of sucking and placing the chip is large, and when the chip is transferred between Socket aging seat and Tray, the vibration of Tray is easy to make the chip turn over and tilt. The operation difficulty of sucking and placing the single chip is large, and the problems of losing chip, appearance damage and low test efficiency are easy to occur.

[0020] Based on this, the utility model embodiment provides a kind of electrical test device, compared with the test mode of combination of Socket aging seat and Tray, test mode of test daughter board and test motherboard is used to carry out electrical test to the chip to be measured, it can reduce the test cost when the chip to be measured is electrically tested, and since the chip to be measured is arranged on test daughter board, it is easy to suck and place the chip to be measured, and it is not easy to lose chip and damage appearance, so as to further improve test efficiency.In addition, test assembly is arranged in test box, so that the electrical test of the chip to be measured is closer to actual application scene, and the accuracy of the electrical test result of the chip to be measured is improved.

[0021] In order to facilitate understanding of the technical scheme of the utility model embodiment, the technical scheme of the utility model is described in detail through specific embodiments below. The above related technologies can be combined with the technical scheme of the utility model embodiment arbitrarily, and they all belong to the protection scope of the utility model embodiment. The utility model embodiment includes at least part of the following contents.

[0022] Figure 1 is a structural schematic diagram of the electrical test device provided by the utility model embodiment, as Figure 1 shown, the electrical test device 100 can include:

[0023] The test sub-board 101 is provided with the to-be-tested chip 102 on one side surface and a pin connector 103 on the other side surface; the test mainboard 104 is provided with a pin connector 105 on one side surface, the pin connector 105 of the test mainboard 104 is connected to the pin connector 103 of the test sub-board 101 to form a test assembly, and the other side surface of the test mainboard 104 is provided with a test control circuit 106, the test control circuit 106 is connected to the power supply end of the test sub-board 101 via the pin connector 105 and the pin connector 103, and is used to provide a bias voltage condition for electrical testing; the test box 107 is provided with the test assembly, and is used to perform electrical testing on the to-be-tested chip 102.

[0024] It should be noted that the test sub-board 101 and the test mainboard 104 can be printed circuit boards (PCB).

[0025] It should be further noted that in the embodiment of the utility model, the size of the to-be-tested chip 102 can be arbitrary, and the to-be-tested chip 102 can select a larger chip or a smaller chip, and the embodiment of the utility model does not limit this.

[0026] It can be understood that the to-be-tested chip can be mounted on one side surface of the test sub-board by surface mounted technology (SMT), and the pin connector can be mounted on the other side surface of the test sub-board by SMT; the pin connector can be mounted on one side surface of the test mainboard by SMT.

[0027] Further, since the test sub-board 101 is relatively large, it is relatively easy to pick up and place the to-be-tested chip 102 after mounting the to-be-tested chip 102 on one side surface of the test sub-board 101 by SMT.

[0028] It should be further noted that in the related art, a dual in-line package (DIP) test seat can be connected to the pin connector of the test sub-board, so that the test mainboard is connected to the test sub-board to form a test assembly. However, compared with the pin connector 105, the cost of the DIP test seat is relatively high. Therefore, in the embodiment of the utility model, the pin connector 105 is usually used instead of the DIP test seat to be connected to the pin connector 103.

[0029] It should be understood that, Figure 1It is understood that the number of the row pin connector 103 and the number of the row female connector 105 can be any number, and the embodiments of the present application do not limit the number of the row pin connector 103 and the number of the row female connector 105.

[0030] Further, the row female connector 105 of one test motherboard 104 can be connected with the row pin connector 103 of one test daughter board 101, or the row female connector 105 of one test motherboard 104 can be connected with the row pin connector 103 of multiple test daughter boards 101, and the embodiments of the present application do not limit the number of the row pin connector 103 and the number of the row female connector 105. For example, 20 or 40 test daughter boards 101 on which the to-be-tested chips 102 are attached can be installed on the test motherboard 104.

[0031] It is understood that the test daughter board 101 can further include peripheral devices in addition to the to-be-tested chip 102 and the row pin connector 103, and the peripheral devices can be attached to the test daughter board 101 by SMT; the test motherboard 104 can further include peripheral devices in addition to the test control circuit 106 and the row female connector 105, and the peripheral devices can be attached to the test motherboard 104 by SMT. Further, the peripheral devices that cannot be placed on the test daughter board 101 can be placed on the test motherboard 104.

[0032] For example, the peripheral devices can include capacitors, resistors, inductors, etc., and the embodiments of the present application do not limit the peripheral devices.

[0033] It is understood that some pins of the to-be-tested chip 102 need to be connected with some peripheral devices to form a circuit, and thus the peripheral devices cannot be too far away from the pin connection wires. Based on this, the peripheral devices can be attached to the test daughter board 101 by SMT, so that the peripheral devices are close (e.g., less than 3 mm) to the pin connection wires of the to-be-tested chip 102.

[0034] It is further understood that the humidity condition required for the electrical test of the to-be-tested chip 102 is usually a high-humidity state; the temperature condition required for the electrical test of the to-be-tested chip 102 is usually a high-temperature state; and the pressure condition required for the electrical test of the to-be-tested chip 102 is usually a high-pressure state.

[0035] Further, after the test assembly is arranged in the test box 107, if the test box 107 is arranged in a high-temperature and high-humidity state, the test motherboard 104 is prone to deformation, and at this time, the test motherboard 104 can be fixed by using a metal frame to reduce the deformation of the test motherboard 104 in the high-temperature and high-humidity state.

[0036] It should be noted that the test motherboard 104 can be provided with a four-corner screw hole, so that a support stud can be installed through the four-corner screw hole.

[0037] In some embodiments, the test box 107 is used to perform electrical tests on the to-be-tested chip 102 by setting at least one environmental condition of humidity condition, temperature condition and pressure condition required for electrical tests of the to-be-tested chip 102.

[0038] Exemplarily, when at least one of the humidity condition is greater than or equal to 85% RH, the temperature condition is greater than or equal to 125 degrees Celsius, and the pressure condition is greater than or equal to 2.3 kpa, it is illustrated that the at least one environmental condition is relatively severe, and at this time, the electrical test of the to-be-tested chip is closer to the actual application scene. The electrical test of the to-be-tested chip under the at least one environmental condition can improve the accuracy of the electrical test result of the to-be-tested chip.

[0039] The electrical test device provided by the embodiment of the utility model, compared with the test mode of Socket aging seat and Tray disc, adopts the test mode of test daughter board and test mother board to perform electrical test on to-be-tested chip, can reduce the test cost when performing electrical test on to-be-tested chip, and because to-be-tested chip is arranged on test daughter board, so to-be-tested chip is easy to be sucked and placed, and chip loss and appearance damage are not easy to occur, thereby test efficiency can be further improved. In addition, test assembly is arranged in test box, so that electrical test of to-be-tested chip is closer to actual application scene, and the accuracy of electrical test result of to-be-tested chip is improved.

[0040] It should be understood that after the test mother board 104 is powered on by the external power supply, the test control circuit 106 arranged on the surface of the test mother board 104 can be used to provide a bias voltage condition for the power supply end of the test daughter board 101.

[0041] It should also be understood that after the test mother board 104 is powered on by the external power supply, the to-be-tested chip 102 on the test daughter board 101 does not necessarily work at this time, and the test mother board 104 needs to be connected to the signal source to make the to-be-tested chip 102 on the test daughter board 101 work in the expected mode.

[0042] In some embodiments, the other side surface of the test mother board 104 is also provided with a power supply filtering circuit and / or a signal filtering circuit. The power supply filtering circuit is used to filter out the interference voltage received by the test mother board 104, and the signal filtering circuit is used to filter out the interference signal received by the test mother board 104.

[0043] It should be noted that the interference voltage can be caused by lightning, surge, fast pulse group, etc.; the interference signal can be caused by high-frequency signal, electromagnetic radiation, radio wave, interference of other electrical equipment, etc., which are not limited by the embodiment of the utility model.

[0044] Based on the above technical scheme, by filtering out the interference voltage received by the test motherboard, and / or by filtering out the interference signal received by the test motherboard, the larger voltage fluctuation and / or larger signal fluctuation generated on the test motherboard can be reduced, and the stability of the test motherboard is improved.

[0045] In some embodiments, the power pin of the chip under test 102 can be connected to the power end of the test sub-board 101 via the first power circuit, the ground pin of the chip under test 102 can be connected to the ground end of the test sub-board 101 via the first ground circuit, and the signal pin of the chip under test 102 can be connected to the signal end of the test sub-board 101 via the first signal circuit.

[0046] Based on the above technical scheme, the power pin, the ground pin and the signal pin of the chip under test are connected to the corresponding end of the test sub-board via the first power circuit, the first ground circuit and the first signal circuit, respectively, so that the chip under test can obtain stable and reliable power supply, ground connection and signal transmission during electrical testing, thereby improving the accuracy and reliability of electrical testing.

[0047] In some embodiments, the test sub-board 101 is provided with at least one first ground line through hole in the thickness direction, and the at least one first ground line through hole is used to arrange the first ground circuit between the one side surface and the other side surface of the test sub-board 101; and / or the test motherboard 104 is provided with at least one second ground line through hole in the thickness direction, and the at least one second ground line through hole is used to arrange the second ground circuit between the one side surface and the other side surface of the test motherboard 104.

[0048] Based on the above technical scheme, the ground lines between the one side surface and the other side surface of the test sub-board can be connected together through the at least one first ground line through hole, and / or the ground lines between the one side surface and the other side surface of the test motherboard can be connected together through the at least one second ground line through hole, so that the test sub-board and / or the test motherboard can be made more secure and interference can be reduced.

[0049] In some embodiments, the at least one first ground line through hole is greater than or equal to a first preset distance value from the first power circuit in the extension direction of the test sub-board 101, and the at least one first ground line through hole is greater than or equal to a second preset distance value from the first signal circuit in the extension direction of the test sub-board 101; and / or the at least one second ground line through hole is greater than or equal to a third preset distance value from the second power circuit in the extension direction of the test motherboard 104, and the at least one second ground line through hole is greater than or equal to a fourth preset distance value from the second signal circuit in the extension direction of the test sub-board.

[0050] It should be noted that the first preset distance value, the second preset distance value, the third preset distance value and the fourth preset distance value can be set by a person skilled in the art according to an experience rule, or can be set according to other manners, and embodiments of the utility model do not limit this.

[0051] Exemplarily, the first preset distance value and the third preset distance value can both be 20 mils (mils), and the second preset distance value and the fourth preset distance value can both be 10 mils.

[0052] Based on the above technical solution, in the case that the distance value between the ground hole and the power line and the signal line is kept, electromagnetic interference and signal crosstalk can be effectively reduced, so that the circuit performance stability and test accuracy on the test daughter board and the test mother board are improved.

[0053] In some embodiments, the thickness of the test daughter board 101 is greater than or equal to a first preset thickness value, and / or the thickness of the test mother board 104 is greater than or equal to a second preset thickness value.

[0054] It should be noted that the first preset thickness value and the second preset thickness value can be set by a person skilled in the art according to an experience rule, or can be set according to other manners, and embodiments of the utility model do not limit this.

[0055] Exemplarily, the first preset thickness value can be 1 mm.

[0056] Exemplarily, the second preset thickness value can be 3 mm.

[0057] It should be noted that the test daughter board 101 and / or the test mother board 104 cannot be too thin. In the case that the test daughter board 101 and / or the test mother board 104 is too thin, the test daughter board 101 and / or the test mother board 104 will absorb moisture, so that the devices on the test daughter board 101 and / or the test mother board 104 are easily connected together, thereby causing a short circuit, and the test daughter board 101 and / or the test mother board 104 is also easily deformed.

[0058] Based on the above technical solution, by setting the thickness of the test daughter board and / or the thickness of the test mother board, the probability of short circuit of the test daughter board and / or the test mother board can be reduced, and the test daughter board and / or the test mother board is not easily deformed.

[0059] In some embodiments, the test daughter board 101 is provided with a detection site, and the detection site is used to detect whether the test daughter board 101 and the test mother board 104 are correctly connected.

[0060] It should be noted that the detection site can be a missing corner on the test sub-board 101, can be a private printing provided on one side surface of the test sub-board 101, or can be a detection site provided by other manners, and the embodiments of the utility model do not make limitation.

[0061] Based on the above technical scheme, by providing the detection site on the test sub-board, the probability of correct connection of the test sub-board and the test mainboard can be improved.

[0062] In some embodiments, the test sub-board 101 is cleaned by using alcohol and deionized water with a ratio of 10:3 under ultrasonic wave condition.

[0063] It should be noted that after the to-be-tested chip 102 and the pin connector 103 are attached on the test sub-board 101, the welding pollutants introduced to the test sub-board 101 can cause the leakage of the to-be-tested chip 102 to increase, thereby affecting the electrical test of the to-be-tested chip 102. Therefore, the test sub-board 101 needs to be cleaned.

[0064] Exemplarily, the cleaning process of the test sub-board 101 can include: first, using medical alcohol with a concentration of 75%, and cleaning the test sub-board 101 in an ultrasonic cleaner according to a cleaning solution with a ratio of alcohol: deionized water = 10L:3L, and cleaning for 1 min; second, using deionized water to clean the test sub-board 101 in the ultrasonic cleaner, and cleaning for 30 seconds (s); then, placing the cleaned test sub-board 101 in an oven at 125℃ for baking for 4 hours (h); finally, after the baked test sub-board 101 is placed back to normal temperature, the to-be-tested chip 102 on the test sub-board 101 is electrically tested. Experiments show that by cleaning the test sub-board 101 through the above cleaning process, the failure probability of the electrical test of the to-be-tested chip 102 can be reduced to about 0.01%.

[0065] Based on the above technical scheme, by using alcohol and deionized water with a ratio of 10:3 under ultrasonic wave condition to clean the test sub-board, the welding pollutants introduced to the test sub-board can be reduced, and the leakage probability of the to-be-tested chip can be reduced.

[0066] It should be understood that the above technical scheme is to clean the test sub-board 101, and it can be understood that the test mainboard 104 can also be cleaned by a similar cleaning method, and the embodiments of the utility model do not make repeated description here.

[0067] It should also be understood that before the test assembly is provided in the test box 107, the inner cavity of the test box 107 can also be regularly maintained and cleaned, so as to reduce the influence of the dirt pollution remaining in the test box 107 on the electrical test of the to-be-tested chip 102 in the experiment process.

[0068] In the related art, when the material of the pin connector is metal (such as a nickel-plated pin), the pin connector is prone to oxidation when in a high-temperature and high-humidity state, and the contact may be poor when plugging, thereby causing electro-static discharge (ESD) and electrical over stress (EOS).

[0069] Based on this, in some embodiments, the pin connector 103 is a gold-plated pin connector, and the gold-plated thickness of the pin connector 103 is within a preset thickness range.

[0070] It should be noted that the preset thickness range can be set according to the experience rule of a person skilled in the art, or can be set according to other manners, and the embodiments of the present application do not limit this.

[0071] Exemplarily, the gold-plated thickness of the pin connector 103 can be about 3 microinches.

[0072] Exemplarily, as shown in Table 1, by comparing the automatic test equipment (ATE) test results of the nickel-plated pin connector and the gold-plated pin connector, it can be seen that without cleaning the test subboard 101 and the test motherboard 104, the surface of the nickel-plated pin connector is prone to oxidation in a high-temperature and high-humidity (such as 130℃ / 85%RH) environment, while the 3 microinches gold-plated pin connector can effectively resist oxidation; with cleaning the test subboard 101 and the test motherboard 104, the dirt on the test subboard 101 and the test motherboard 104 can be effectively removed, and the oxidation probability of the nickel-plated pin connector is reduced.

[0073] The biased highly accelerated stress test (BHAST) and the unbiased highly accelerated stress test (UHAST) can be considered as two test boxes providing different test environments, the BHAST96h represents that the to-be-tested chip is subjected to 96h environmental stress electrical test under high temperature and high humidity conditions, the BHAST192h represents that the to-be-tested chip is subjected to 192h environmental stress electrical test under high temperature and high humidity conditions, and the UHAST96h represents that the to-be-tested chip is subjected to 96h environmental stress test under high temperature and high humidity conditions. In the BHAST, the to-be-tested chip is subjected to environmental stress electrical test through the test daughter board and the test mother board, the test mother board is powered on through an external power supply, and at this time, the pin header connector is easy to be corroded and oxidized; in the UHAST, the test mother board is not powered on through an external power supply, but is directly subjected to environmental stress test, and at this time, the pin header connector is not easy to be corroded and oxidized. Considering the actual situation, the test mother board is usually powered on through an external power supply, and therefore the test box 107 used in the embodiment of the utility model can be the BHAST.

[0074] As shown in Table 1, for the 3-micron gold-plated pin header connector 103, the test success probability of the pin header connector 105 is equivalent to that of the DIP test seat, and considering that the cost of the DIP test seat is relatively high, the pin header connector 105 is used instead of the DIP test seat in the embodiment of the utility model.

[0075] Table 1

[0076]

[0077]

[0078] Based on the above technical solution, by using the pin header connector plated with gold and having a gold-plating thickness within a preset thickness range, the pin header connector is not easy to be oxidized and has good contact, and is not easy to generate ESD / EOS.

[0079] In the embodiment of the utility model, after the environmental stress electrical test on the to-be-tested chip, the test daughter board can be placed on the ATE test board for ATE test, so as to detect whether each electrical parameter of the chip is within a specified range. If at least part of the parameters of the chip are detected to be out of the specified range, it is indicated that the chip needs to be optimized and designed.

[0080] It can be understood that the embodiment of the utility model is beneficial to exposing the possible risks of the chip in advance, is helpful to avoiding risks as early as possible in the design stage of the chip, optimizes the design, and therefore improves the reliability and quality of the chip.

[0081] The preferred embodiments of the present application are described in detail above with reference to the drawings, but the present application is not limited to the specific details in the above-described embodiments, and various simple modifications can be made to the technical solutions of the present application within the technical concept of the present application, and these simple modifications all belong to the protection scope of the present application. For example, in the above-described specific embodiments, various specific technical features are described, and in the case of no contradiction, any suitable combination can be made, and in order to avoid unnecessary repetition, the present application does not further describe various possible combination manners. For another example, various different embodiments of the present application can also be combined arbitrarily, as long as it does not deviate from the idea of the present application, and it should also be considered as the disclosed content of the present application. For another example, in the case of no conflict, various embodiments described in the present application and / or technical features in various embodiments can be combined with any related technology, and the technical solutions obtained after combination should also fall within the protection scope of the present application.

[0082] Figure 2 is a structural schematic diagram of an electrical test system provided by an embodiment of the present application. As shown in Figure 2 , the electrical test system 200 can include:

[0083] a test daughter board 210, one side surface of the test daughter board 210 is provided with a to-be-tested chip, and the other side surface is provided with a pin connector; a test mother board 220, one side surface of the test mother board 220 is provided with a female connector, the female connector of the test mother board 220 is connected to the pin connector of the test daughter board 210 to form a test assembly, and the test mother board 220 is provided with a test control circuit, the test control circuit is connected to a power supply end of the test daughter board 210 via the female connector and the pin connector, and is used for providing a bias condition of electrical test to the power supply end; and a test box 230, the test box 230 is provided with the test assembly, and is used for performing electrical test on the to-be-tested chip.

[0084] Those skilled in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed in the present application can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software mode depends on the specific application and design constraints of the technical solutions. Professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0085] It should be noted that in the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, article or device.

[0086] The above-mentioned embodiment serial numbers of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0087] The features disclosed in the several product embodiments of the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0088] The features disclosed in the several device embodiments of the present application can be combined arbitrarily without conflict to obtain new device embodiments.

[0089] The above-mentioned embodiments are only used to illustrate the present application, and are not limited to the present application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, all equivalent technical solutions belong to the scope of the present application, and the patent protection scope of the present application should be defined by the claims.

Claims

1. An electrical testing device, characterized by, The test sub-board is provided with a to-be-tested chip on one side surface and a pin connector on the other side surface. The test mainboard is provided with a pin connector on one side surface, the pin connector of the test mainboard is connected to the pin connector of the test sub-board to form a test assembly, and the other side surface of the test mainboard is provided with a test control circuit connected to the power supply end of the test sub-board through the pin connector and the pin connector, for providing the power supply end with a bias voltage condition of the electrical test. The test box is provided with the test assembly for electrical test of the to-be-tested chip. The pin connector is a gold-plated pin connector, and the gold-plating thickness of the pin connector is within a preset thickness range.

2. The apparatus of claim 1, wherein, The power supply pin of the to-be-tested chip is connected to the power supply end of the test sub-board through a first power supply circuit, the ground pin of the to-be-tested chip is connected to the ground end of the test sub-board through a first ground circuit, and the signal pin of the to-be-tested chip is connected to the signal end of the test sub-board through a first signal circuit.

3. The apparatus of claim 1 or 2, wherein, The test sub-board is provided with at least one first ground wire through hole in the thickness direction, and the at least one first ground wire through hole is used for arranging a first ground circuit between the one side surface and the other side surface of the test sub-board.

4. The apparatus of claim 3, wherein, And / or, The test mainboard is provided with at least one second ground wire through hole in the thickness direction, and the at least one second ground wire through hole is used for arranging a second ground circuit between the one side surface and the other side surface of the test mainboard. The at least one first ground wire through hole is greater than or equal to a first preset distance value from the first power supply circuit in the extension direction of the test sub-board, and the at least one first ground wire through hole is greater than or equal to a second preset distance value from the first signal circuit in the extension direction of the test sub-board.

5. The apparatus of claim 4, wherein, And / or, The at least one second ground wire through hole is greater than or equal to a third preset distance value from the second power supply circuit in the extension direction of the test mainboard, and the at least one second ground wire through hole is greater than or equal to a fourth preset distance value from the second signal circuit in the extension direction of the test mainboard. The thickness of the test sub-board is greater than or equal to a first preset thickness value, and / or the thickness of the test mainboard is greater than or equal to a second preset thickness value.

6. The apparatus of claim 1 or 2, wherein, The test sub-board is cleaned under ultrasonic wave conditions with a ratio of 10:3 of alcohol and deionized water.

7. The apparatus of claim 1 or 2, wherein, The other side surface of the test mainboard is further provided with a power supply filtering circuit and / or a signal filtering circuit, the power supply filtering circuit is used for filtering out the interference voltage received by the test mainboard, and the signal filtering circuit is used for filtering out the interference signal received by the test mainboard.

8. The apparatus of claim 1 or 2, wherein, The test sub-board is provided with a detection position for detecting whether the test sub-board and the test mainboard are correctly connected.

9. The apparatus of claim 1 or 2, wherein, The test box is used for electrical test of the to-be-tested chip by setting at least one environmental condition of humidity condition, temperature condition and pressure condition required for electrical test of the to-be-tested chip.

10. The apparatus of claim 1 or 2, wherein, The test sub-board is provided with a to-be-tested chip on one side surface and a pin connector on the other side surface.

11. An electrical test system, characterized by, ​ A test sub-board, one side surface of which is provided with a chip to be tested, and the other side surface of which is provided with a pin connector; A test mother board, one side surface of which is provided with a female connector, the female connector of the test mother board being connected to the pin connector of the test sub-board to form a test assembly, and the test mother board being provided with a test control circuit, the test control circuit being connected to a power supply end of the test sub-board via the female connector and the pin connector, for providing the power supply end with a bias condition of the electrical test; A test box, in which the test assembly is arranged, for performing the electrical test on the chip to be tested.

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