Large-current PCB via hole structure applied to QSFP-DD optical module
By embedding conductive pillars in the PCB vias of the QSFP-DD optical module and then soldering them, the area problem of via design under high current requirements was solved, achieving higher current carrying capacity and a more compact design.
Patent Information
- Application Number
- CN202520433778.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-03-13
AI Technical Summary
Existing QSFP-DD optical modules require more than 10A of current. Conventional via designs require multiple vias, which leads to layout and design difficulties and occupies a large circuit board area.
Conductive pillars are embedded in PCB vias and connected to the via body vias by solder layers and wave soldering, thereby increasing the cross-sectional area of the conductive material in the vias and improving the current carrying capacity.
It improves the current carrying capacity of vias, saves circuit board area, and optimizes the design.
Smart Images

Figure CN223885382U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to PCB via hole structure technical field, concretely relates to the large current PCB via hole structure for QSFP-DD optical module. BACKGROUND
[0002] In common printed circuit board (PCB) design, current is conducted between different wiring layers through via. For large current wiring, it is usually planned in the inner layer of PCB to provide a complete wiring plane, while the power supply module and the power terminal are usually soldered on the surface layer of PCB, and the current is conducted between the inner layer and the surface layer through PCB via. In the PCB production process, the via is usually manufactured by drilling and electroplating on the hole wall. Due to the limited thickness of the plating layer of the via, the common via is difficult to withstand large current. In the large current application scenario, multiple vias can be used to provide larger current. When multiple vias are used, a larger PCB area is needed to achieve it. QSFP-DD optical module is usually applied to the circuit board of compact design. Due to the increase of module power consumption, the current of QSFP-DD optical module has exceeded 10A. At least ten or more conventional vias are needed to meet this requirement using ordinary via design, which brings many challenges to the layout and design of QSFP-DD optical module circuit board. SUMMARY
[0003] The utility model aims at overcoming the insufficient prior art, and provides the large current PCB via hole structure for QSFP-DD optical module.
[0004] To achieve the above-mentioned purpose, the utility model adopts the following technical scheme:
[0005] The large current PCB via hole structure for QSFP-DD optical module comprises a via body provided on a PCB, a conductive layer is provided on the hole wall of the via body, the conductive layer is used to connect the surface layer and the inner layer of the PCB, a conductive column is embedded in the via body and penetrates both ends of the via body, and the column wall of the conductive column is in contact with the conductive layer of the via body.
[0006] Further, the gap between the conductive column and the hole wall of the via body is filled with a solder layer, and the conductive column and the via body are connected together by wave soldering.
[0007] Further, the top of the conductive column is provided with a connecting plate, the connecting plate is supported on the surface of the PCB, and the connecting plate and the surface pad on the top of the via body are connected into an integral whole by reflow soldering.
[0008] Further, the conductive column is a copper column.
[0009] The utility model discloses a structure of embedding the conductive column in the via, which increases the cross-sectional area of the conductive material in the via, improves the current-carrying capacity of the via, saves the required circuit board area and optimizes the design. BRIEF DESCRIPTION OF DRAWINGS
[0010] The utility model makes further detailed explanation in combination with the drawings and specific embodiment:
[0011] Figure 1 It is the structural diagram of the utility model. SPECIFIC EMBODIMENT
[0012] As Figure 1 The utility model discloses a large current PCB via structure of QSFP-DD optical module, including the via body 1 of being located on the PCB board 2, be equipped with the conductive layer 3 through electroplating on the hole wall of this via body 1, and the conductive layer 3 is used to connect the surface layer 4 and the inner layer 5 of the PCB board 2, and the conductive column 6 of penetrating both ends is buried in the inside of the via body 1, and the column wall of the conductive column 6 is connected with the conductive layer 3 of the via body 1.
[0013] Among them, the conductive column 6 is copper column.
[0014] The gap between the conductive column 6 and the hole wall of the via body 1 is filled with a solder layer 7, and the conductive column 6 and the via body 1 are connected together by wave soldering.
[0015] The top of the conductive column 6 is provided with a connecting plate 51, the connecting plate 61 is supported on the surface of the PCB board 2, and the connecting plate 61 and the surface pad 8 on the top periphery of the via body 1 are connected into an integral whole by reflow soldering.
[0016] In order to realize the target of increasing the current-carrying capacity of the via, the conductive column 6 is welded into the via. By adding a conductive body in the via, the cross-sectional area of the conductive material in the via is increased, thereby improving the current-carrying capacity of the via.
[0017] The specific method of embedding the conductive column 6 in the via of the utility model is as follows:
[0018] Step 1: after smearing the solder paste on the column wall surface of the conductive column 6, put it into the via;
[0019] Step 2: after inserting the conductive column 6, first reflow soldering is performed to fix the connecting plate at the top of the conductive column 6, and ensure that the connecting plate 61 and the surface pad 8 are reliably connected;
[0020] Step 3: through the wave soldering process, the gap between the conductive column 6 and the via wall is filled with solder, thereby achieving the purpose of improving the current capacity.
[0021] The specific embodiment of the utility model is described above, but the person skilled in the art should understand that this is only an example, and the person skilled in the art can make various changes or modifications to this embodiment without departing from the principles and essence of the utility model, but these changes and modifications all fall within the protection scope of the utility model.
Claims
1. A high-current PCB via structure applied to QSFP-DD optical modules, comprising a via body disposed on a PCB board, wherein a conductive layer is provided on the hole wall of the via body, the conductive layer being used to connect and conduct the surface layer and inner layer of the PCB board, characterized in that: The conductive column is embedded in the through hole body and penetrates through both ends of the through hole body.
2. The large current PCB via structure for a QSFP-DD optical module of claim 1, wherein: The gap between the conductive column and the hole wall of the through hole body is filled with a solder layer, and the conductive column and the through hole body are connected together through wave soldering.
3. The large current PCB via structure for a QSFP-DD optical module of claim 1, wherein: The top of the conductive column is provided with a connecting plate, the connecting plate is supported on the surface of the PCB, and the connecting plate and the surface pad of the top of the through hole body are connected into an integrated body through reflow soldering.
4. The large current PCB via structure for a QSFP-DD optical module of claim 1, wherein: The conductive column is a copper column.