Semiconductor device and image sensor

Abstract

The utility model relates to a semiconductor device and an image sensor, which comprises a semiconductor device of a plurality of optical detectors arranged in a substrate, and the substrate is provided with a front surface opposite to a back surface. The semiconductor device includes a floating diffusion node disposed in a substrate, wherein a plurality of photodetectors are disposed around the floating diffusion node. The trench isolation structure is disposed within the substrate and laterally surrounds the plurality of photodetectors. The trench isolation structure includes a first isolation structure disposed in the substrate and having a first depth, wherein the first isolation structure is disposed between adjacent photodetectors and laterally offset relative to the floating diffusion node. The trench isolation structure includes a second isolation structure extending from the back surface of the substrate to the floating diffusion node, wherein the second isolation structure is located right above the floating diffusion node and has a second depth less than the first depth.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device and an image sensor. BACKGROUND

[0002] An image sensor is a solid-state device configured to convert incident light (e.g., photons) into electrical signals. The electrical signals are then provided to a processor, which can convert the electrical signals into data that can be stored and / or viewed by a user. Integrated chips (ICs) having image sensors are widely used in modern electronic devices, such as cell phones, security cameras, medical devices, etc. SUMMARY

[0003] One aspect of the present application provides a semiconductor device. The semiconductor device includes a plurality of photodetectors disposed within a substrate, wherein the substrate has a front side opposite a back side. The semiconductor device also includes a floating diffusion node disposed within the substrate, wherein the plurality of photodetectors are disposed about the floating diffusion node. The semiconductor device also includes a trench isolation structure disposed within the substrate and laterally surrounding the plurality of photodetectors. The trench isolation structure includes a first isolation structure disposed within the substrate and having a first depth, and a second isolation structure extending from the back side of the substrate toward the floating diffusion node. The first isolation structure is disposed between adjacent photodetectors and laterally offset with respect to the floating diffusion node. The second isolation structure is disposed directly above the floating diffusion node and has a second depth that is less than the first depth.

[0004] Another aspect of the present application provides an image sensor. The image sensor includes an interconnect structure disposed on a front side surface of a substrate, wherein the substrate has a back side surface opposite the front side surface. The image sensor also includes a plurality of photodetectors disposed within the substrate. The image sensor also includes a partial depth isolation structure disposed within the substrate between the plurality of photodetectors, wherein the partial depth isolation structure extends from the back side surface of the substrate toward the interconnect structure, and wherein the partial depth isolation structure has a bottom surface above the front side surface of the substrate. The image sensor also includes a full depth isolation structure disposed within the substrate between the plurality of photodetectors, wherein the full depth isolation structure extends through an entire thickness of the substrate, and wherein the full depth isolation structure and the partial depth isolation structure together form at least a linear mesh segment of a trench isolation structure.

[0005] Yet another aspect of the present utility model provides a method of forming an image sensor. The method includes forming a photodetector within a substrate, where the substrate has a backside surface opposite a frontside surface. The method also includes patterning the frontside surface of the substrate to form a full-depth isolation structure opening through the substrate, where the full-depth isolation structure opening surrounds a first portion of the photodetector. The method also includes forming a full-depth isolation structure within the full-depth isolation structure opening. The method also includes patterning the backside surface of the substrate to form a partial-depth isolation structure opening surrounding a second portion of the photodetector, where the partial-depth isolation structure opening has a bottom surface that is above the frontside surface of the substrate, and where the partial-depth isolation structure opening is formed between opposing edges of the full-depth isolation structure. The method also includes forming a partial-depth isolation structure within the partial-depth isolation structure opening.

[0006] In order to make the above features and advantages of the present utility model more obvious and easy to understand, the following examples are specifically described below, and the detailed description is made in combination with the drawings as follows. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1-3 Various views showing some embodiments of image sensors having trench isolation structures including partial-depth isolation structures and full-depth isolation structures.

[0008] Figure 4 Top views showing some embodiments of image sensors having full-depth isolation structures including tab structures surrounding partial-depth isolation structures.

[0009] Figure 5 Cross-sectional views showing some embodiments of image sensors. Figure 4

[0010] Figure 6 Cross-sectional views showing some embodiments of image sensors having wedge-shaped partial-depth isolation structures.

[0011] Figure 7 , Figure 8 and Figure 9 Cross-sectional views showing some embodiments of image sensors having trench isolation structures extending into the backside surface of the substrate.

[0012] Figure 10 Top views showing image sensors having trench isolation structures including partial-depth isolation structures and full-depth isolation structures.

[0013] Figures 11-33 Various views showing some embodiments of methods of forming image sensors having trench isolation structures with full-depth isolation structures and partial-depth isolation structures having different depths. ​

[0014] Figures 34-40 Various cross-sectional views are shown of some other embodiments of a method for forming an image sensor including a trench isolation structure, wherein the trench isolation structure has a full-depth isolation structure and a partial-depth isolation structure with different depths.

[0015] Figure 41 and Figure 42 Flowcharts illustrating some embodiments of a method for forming an image sensor with an isolation structure are shown, wherein the isolation structure has a full-depth isolation structure and a partial-depth isolation structure with different depths.

[0016] Figures 43-48 Various views are shown of some embodiments of a method for forming an image sensor with a trench isolation structure, wherein the trench isolation structure has a full-depth isolation structure with one or more patch structures. Detailed Implementation

[0017] This utility model provides numerous different embodiments or examples of various features for implementing this utility model. Specific examples of components and arrangements are described below to simplify the utility model. These are, of course, merely examples and are not intended to be limiting. For instance, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various instances of this utility model. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Image sensors (e.g., semiconductor image sensors (CIS)) may include multiple pixel sensors disposed on a substrate. Each pixel sensor includes a photodetector configured to convert energy from a radiation source (e.g., light, infrared radiation, X-rays, etc.) into an electric current. To reduce the size of the image sensor, the pixel sensor has a shared pixel layout, where multiple photodetectors share a floating diffusion node disposed at the intersection of the multiple photodetectors. However, as the size of the image sensor decreases, the photodetectors are closer together, which increases crosstalk and noise between the pixel sensors. To reduce noise, the photodetectors are separated from each other by one or more isolation structures configured to reduce electrical or photonic crosstalk between the photodetectors. In some aspects, the one or more isolation structures are formed from one or more of the back or front side of the substrate containing the photodetectors and the floating diffusion node.

[0019] For example, a partial deep trench isolation (P-DTI) structure can be formed over the floating diffusion node, and a full deep trench isolation (F-DTI) structure can be formed through the substrate to surround the floating diffusion node and between adjacent photodetectors. The P-DTI structure and the F-DTI structure can be formed from either the backside or the frontside of the substrate. However, processing the P-DTI structure and the F-DTI structure on the same substrate requires precise control of multiple parameters. Notably, it is critical to ensure precise alignment of the trenches in which the P-DTI structure and the F-DTI structure are formed. Misalignment of the trenches can result in ineffective isolation, thereby increasing electronic noise and degrading the performance of the image sensor. Furthermore, as the pixel size in image sensors shrinks, it becomes increasingly complex to control the depth and profile of these trenches. Image miniaturization exacerbates the manufacturing challenges because the margin for error is reduced, where small misalignments can have a significant negative impact on the performance of the image sensor. Therefore, it is important to develop image sensors and related methods to reliably and accurately manufacture these isolation structures, especially at small pixel sizes.

[0020] Various aspects of the present disclosure are directed to an image sensor including a multi-depth trench isolation structure having a partial depth isolation structure and a full depth isolation structure within a substrate. The image sensor can include a plurality of pixel sensors disposed on the substrate. The pixel sensors each include a plurality of photodetectors disposed within the substrate and surrounded by a multi-depth isolation grid. The pixel sensors each have a shared pixel layout such that a floating diffusion node is disposed at a crossroad or center of the plurality of photodetectors. The partial depth isolation structure is disposed over the floating diffusion node at the crossroad of the photodetectors. The full depth isolation structure surrounds the photodetectors at a periphery offset from the partial depth isolation structure and has a first depth. The partial depth isolation structure has a second depth that is less than the first depth. In some embodiments, the first depth is equal to or greater than a full depth (i.e., an entire thickness or height) of the substrate, and the second depth is less than the full depth of the substrate. The partial depth isolation structure reduces leakage from the floating diffusion node and facilitates each pixel sensor having the shared pixel layout by providing a space within the substrate to accommodate the floating diffusion node. Furthermore, the full depth isolation structure across the full depth of the substrate facilitates better electrical and optical isolation between adjacent photodetectors and adjacent pixel sensors. The arrangement of the partial depth isolation structure and the full depth isolation structure forms a grid that effectively isolates the photodetectors, thereby reducing cross-talk and noise in the image sensor. As a result, the overall performance of the image sensor is improved.

[0021] In some examples discussed herein, a multi-depth trench isolation structure including a full-depth isolation structure and a partial-depth isolation structure is formed according to a two-step process. First, a full-depth isolation structure extending from a front side of a substrate is formed between photodetectors adjacent to a floating diffusion node. Second, a partial-depth isolation structure extending from a back side of the substrate is formed between sidewalls of the full-depth isolation structure over the floating diffusion node. The partial-depth isolation structure is formed by an initial etch and a subsequent extension etch. According to a mask and the initial etch, a partial-depth isolation opening is formed between the sidewalls of the full-depth isolation structure from a backside surface of the substrate. Since the mask formed on the backside surface of the substrate can have an alignment or registration error, a controlled extension etch can be applied to the partial-depth isolation opening to extend the partial-depth isolation opening to the sidewalls of the full-depth isolation structure without over-etching into other areas of the substrate. The partial-depth isolation opening is subsequently filled to form the partial-depth isolation structure. Thus, the partial-depth isolation opening is formed to have a controlled profile that can accommodate misalignment during fabrication processes.

[0022] The resulting multi-depth trench isolation structure provides space in the substrate for accommodating the floating diffusion node while enhancing electrical and optical isolation of the image sensor. In addition, front and back substrate processing with depth and profile control is also achieved to enable design flexibility of the multi-depth trench isolation structure.

[0023] Figures 1-3 Various views of some embodiments of the image sensor 100 including the trench isolation structure 130 having a full-depth isolation structure 132 and a partial-depth isolation structure 134 are shown. Figure 1 Cross-sectional views of some embodiments of the image sensor 100 taken along line A-A’ of Figure 3 Cross-sectional views of some embodiments of the image sensor 100 taken along line B-B’ of Figure 2 Cross-sectional views of some embodiments of the image sensor 100 taken along line B-B’ of Figure 3 Cross-sectional views of some embodiments of the image sensor 100 taken along line B-B’ of Figure 3 Top views of some embodiments of the image sensor 100 are shown.

[0024] Reference is now made concurrently to Figures 1-3The image sensor 100 has a plurality of pixel sensors 103 on a substrate 104. An interconnect structure 102 is disposed along a front side surface 104f of the substrate 104. In some embodiments, the substrate 104 includes a semiconductor body (e.g., bulk silicon) and / or has a first doping type (e.g., p-type). The interconnect structure 102 includes an interconnect dielectric structure 106, a plurality of conductive metal lines 108, and a plurality of vias 110. A plurality of pixel devices 112 are disposed along the front side surface 104f of the substrate 104 and are electrically coupled to each other and / or to other semiconductor devices (not shown) by the plurality of conductive metal lines 108 and the plurality of vias 110. The plurality of pixel devices 112 can include a gate 116 and a gate dielectric layer 114 disposed between the gate 116 and the front side surface 104f of the substrate 104.

[0025] A plurality of photodetectors 122 are disposed throughout the substrate 104. The plurality of pixel sensors 103 each include one or more photodetectors 122. For example, the pixel sensors 103 can each include a fourth photodetector 122 disposed in a shared pixel layout structure (e.g., a 2x2 shared pixel layout). In other embodiments, the pixel sensors 103 can have a 2x1 layout, a 3x2 layout, or some other suitable layout. The photodetectors 122 can each include a second doping type (e.g., n-type) opposite the first doping type (e.g., p-type). In some embodiments, the photodetectors 122 are rectangular in shape and have four sides. In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In various embodiments, a floating diffusion node 126 is disposed in the substrate 104 along the front side surface 104f and includes the second doping type (e.g., n-type). The floating diffusion node 126 can be disposed at a center or intersection of a corresponding pixel sensor 103, or at a center of a group of adjacent photodetectors (e.g., at a center of a 2x2 or 4x4 array of photodetectors). In this way, the pixel sensors 103 can, for example, have a shared pixel layout. The plurality of photodetectors 122 are configured to absorb incident light (e.g., photons) and generate respective electrical signals corresponding to the incident light. In such embodiments, the plurality of photodetectors 122 can generate electron-hole pairs from the incident light. In various embodiments, the pixel devices 112 can be configured to perform readout of the electrical signals generated from the plurality of photodetectors 122. For example, the pixel devices 112 can include one or more transfer transistors configured to selectively form a conductive path in the substrate 104 between the floating diffusion node 126 and an adjacent photodetector to transfer charge (e.g., charge accumulated by absorbing incident radiation) accumulated in the photodetector 122 to the floating diffusion node 126.

[0026] Trench isolation structures 130 are disposed within substrate 104 and include full-depth isolation structures 132 and partial-depth isolation structures 134. In some embodiments, full-depth isolation structures 132 extend from a front-side surface 104f of substrate 104 to a back-side surface 104b, and partial-depth isolation structures 134 extend from back-side surface 104b into substrate 104. A first depth dl of full-depth isolation structures 132 is greater than a second depth d2 of partial-depth isolation structures 134. In various embodiments, first depth dl is equal to or greater than a full depth (i.e., height or thickness) of substrate 104 and second depth d2 is less than the full depth of substrate 104. In some embodiments, trench isolation structures 130 are referred to as dual-depth isolation structures or hybrid-depth trench isolation structures.

[0027] In various embodiments, deep-trap regions 128 are disposed on back-side surface 104b of substrate 104 and include a second doping type (e.g., n-type) having a lower doping concentration than the plurality of photodetectors 122. In some embodiments, deep-trap regions 128 are configured to absorb incident light (e.g., photons) at a location above each photodetector and generate electron-hole pairs from the incident light, which can be transported to the respective photodetector, for example, thereby increasing a quantum efficiency (QE) of each photodetector. Since trench isolation structures 130 laterally surround the plurality of photodetectors 122 and are disposed between adjacent photodetectors 122, segments of deep-trap regions 128 above each photodetector 122 are isolated from one another. Thus, trench isolation structures 130 further increase optical and / or electrical isolation of each photodetector (e.g., further reduce cross-talk in the image sensor). In further embodiments, the doping concentration of the plurality of photodetectors 122 is in a range of about 1010atoms / cm2to 1011atoms / cm2or another suitable value. In some embodiments, the doping concentration of deep-trap regions 128 is in a range of about 1010atoms / cm2to 1011atoms / cm2or another suitable value. 13 atoms / cm2 3 to 1011 14 atoms / cm2 3 or another suitable value. In some embodiments, the doping concentration of deep-trap regions 128 is in a range of about 1010atoms / cm2to 1011atoms / cm2or another suitable value. 12 atoms / cm2 3 to 1011 14 atoms / cm2 3 or another suitable value.

[0028] In some embodiments, shallow well regions 124 are disposed along sidewalls of full-depth isolation structures 132 within substrate 104 and are configured to increase electrical isolation between adjacent photodetectors of plurality of photodetectors 122. In various embodiments, shallow well regions 124 are annular and continuously surround plurality of photodetectors 122 of first pixel sensor 103a when viewed from a top view. Shallow well regions 124 laterally offset from partial-depth isolation structures 134 and extend from a point vertically above a bottom surface of partial-depth isolation structures 134 to a point aligned with a bottom surface of full-depth isolation structures 132. Shallow well regions 124 comprise a first doping type (e.g., p-type).

[0029] Upper dielectric layer 140 is disposed along backside surface 104b of substrate 104. In some embodiments, upper dielectric layer 140 is an extension of partial-depth isolation structures 134 and covers full-depth isolation structures 132 and substrate 104. In various embodiments, upper dielectric layer 140 is configured as and / or referred to as a passivation layer. Conductive mesh structure 142 covers upper dielectric layer 140, and dielectric mesh structure 144 covers conductive mesh structure 142. Conductive mesh structure 142 and dielectric mesh structure 144 comprise sidewalls that define a plurality of openings positioned directly above corresponding photodetectors of plurality of photodetectors 122. In various embodiments, conductive mesh structure 142 comprises one or more metal layers configured to reduce cross-talk between adjacent photodetectors of plurality of photodetectors 122, thereby increasing optical isolation of the image sensor. Additionally, dielectric mesh structure 144 is configured to direct light to plurality of photodetectors 122 through total internal reflection, such that cross-talk is further reduced and QE of plurality of photodetectors 122 is increased. A plurality of optical filters 146 is disposed in the plurality of openings defined by sidewalls of conductive mesh structure 142 and dielectric mesh structure 144. Optical filters 146 are configured to transmit incident light of a particular wavelength while blocking incident light of other wavelengths. Furthermore, a plurality of microlenses 148 is disposed over optical filters 146 and is configured to focus incident light onto photodetectors 122.

[0030] The full-depth isolation structure 132 extends from the front side surface 104f of the substrate to the back side surface 104b of the substrate 104. In some embodiments, the full-depth isolation structure 132 is referred to as a first isolation structure, a deep trench isolation (DTI) structure, or a full DTI (F-DTI) structure. The full-depth isolation structure 132 extends substantially parallel to a first side and a second side of four sides of the photodetector. A bottom surface of the full-depth isolation structure 132 has a first width, and a top surface of the full-depth isolation structure 132 has a second width that is less than the first width. The full-depth isolation structure 132 includes a first trench fill layer 136 and a first liner 138. The first trench fill layer 136 is separated from the substrate 104 by the first liner 138, where the first liner 138 is disposed along an outer sidewall of the first trench fill layer 136.

[0031] The partial-depth isolation structure 134 extends from the back side surface 104b of the substrate to the front side surface 104f of the substrate 104. In some embodiments, the partial-depth isolation structure 134 is referred to as a second isolation structure, a DTI structure, a partial DTI (P-DTI) structure, or a partial back-side DTI (P-BDTI). The partial-depth isolation structure 134 extends substantially parallel to the first side and the second side of the photodetector. The partial-depth isolation structure 134 has a first width that is vertically aligned with the back side surface 104b of the substrate 104, and a bottom surface of the partial-depth isolation structure 134 has a second width that is less than the first width. Thus, in some embodiments, the first width of the partial-depth isolation structure 134 is greater than the width of the top surface of the full-depth isolation structure 132. In further embodiments, the second width of the partial-depth isolation structure 134 is less than the width of the bottom surface of the full-depth isolation structure 132. In some embodiments, the partial-depth isolation structure 134 includes a second trench fill layer 118 and a second liner 120. The second trench fill layer 118 is separated from the substrate 104 by the second liner 120, where the second liner 120 is disposed along an outer sidewall and a bottom surface of the second trench fill layer 118. The second liner 120 is also disposed along a top surface of the first trench fill layer 136 and the first liner 138. In various embodiments, a planarization process is performed on the second liner 120 and the second trench fill layer 118 such that a top surface of the second liner 120 and the second trench fill layer 118 is coplanar with the back side surface 104b of the substrate 104 (not shown). In such embodiments, the upper dielectric layer 140 is omitted.

[0032] Reference is made to Figure 2FIG. 3 is a cross-sectional view of the image sensor 100 along line C-C’ in FIG. 2. In some embodiments, the second trench fill layer 118 is separated from the first trench fill layer 136 by the second liner 120 and the first liner 138. The partial depth isolation structure 134 is aligned over the floating diffusion node 126, where the second trench fill layer 118 is separated from the floating diffusion node by the substrate 104 and the second liner 120.

[0033] In some embodiments, the first trench fill layer 136 and the second trench fill layer 118 are the same material. In other embodiments, the first trench fill layer 136 and the second trench fill layer 118 comprise different materials. The first trench fill layer 136 and the second trench fill layer 118 can be or comprise an oxide, such as silicon dioxide or a high-k dielectric material. In some embodiments, the first liner 138 and the second liner 120 are the same material or comprise different materials. The first liner 138 and the second liner 120 can be or comprise an oxide or a high-k dielectric material.

[0034] The partial depth isolation structure 134 is disposed over the floating diffusion node 126, and the full depth isolation structure 132 laterally extends between the plurality of photodetectors 122 from the partial depth isolation structure 134. The full depth isolation structure 132 has a first depth dl, and the partial depth isolation structure 134 has a second depth d2 that is less than the first depth dl. As such, when viewed from above, the trench isolation structure 130 has a grid structure that includes the partial depth isolation structures 134 dispersed over the floating diffusion nodes 126 between the image sensors 100 and the full depth isolation structures 132 extending between the photodetectors 122 (see, e.g., FIG. 3). Figure 3 Further, as seen from the top view 300, the full depth isolation structures 132 and the partial depth isolation structures 134 together at least form a linear grid segment 302 of the trench isolation structure 130.

[0035] Each photodetector of the plurality of photodetectors 122 is laterally surrounded on all sides by partial full depth isolation structures 132 and partial partial depth isolation structures 134. For example, as seen in the top view 300, the first photodetector 122a has a first pair of edges opposite one another relative to line C-C’, and a second pair of edges opposite one another relative to line D-D’, where the line C-C’ and the line D-D’ are rotated 90 degrees relative to one another. The second pair of edges face the full depth isolation structure 132 along the line C-C’, and the first pair of edges face the partial depth isolation structure 134 along the line D-D’. Further, adjacent photodetectors of the plurality of photodetectors 122 are laterally spaced apart from one another and separated by both the full depth isolation structures 132 and the partial depth isolation structures 134. Figure 3

[0036] ​The trench isolation structure 130 provides enhanced performance for the image sensor 100. The full-depth isolation structure 132 provides isolation between the multiple photodetectors 122 across the full depth of the substrate 104. However, since the floating diffusion node 126 is disposed within the substrate 104 in a shared pixel layout, the full-depth isolation structure 132 disposed above the floating diffusion node 126 would damage the floating diffusion node 126 and / or hinder the pixel sensor 103 from having a shared pixel layout. To accommodate the floating diffusion node 126 while still providing electrical and photonic isolation between the multiple photodetectors 122, a partial-depth isolation structure 134 is disposed above the floating diffusion node 126. In this way, the performance of the image sensor 100 is enhanced by utilizing isolation structures of varying depths. Furthermore, the trench isolation structure 130 is formed using the front and back surface treatments of the substrate 104, thereby providing design flexibility.

[0037] Figure 4 A top view of an image sensor 400 with a full-depth isolation structure 132 is shown, the full-depth isolation structure 132 including one or more patch structures 402 surrounding a corresponding partial-depth isolation structure 134. Figure 4 The top view provides Figures 1-3 Some other embodiments of the image sensor, wherein the first and second liner are omitted ( Figures 1-3 138, 120), and the full-depth isolation structure 132 is defined by the first trench filling layer 136, and the partial-depth isolation structure 134 is defined by the second trench filling layer 118. In various embodiments, the first trench filling layer 136 contacts the second trench filling layer 118. In various embodiments, the full-depth isolation structure 132 includes ( Figures 1-3 The first liner 138 surrounds the first trench filling layer 136, and the partial depth isolation structure 134 includes ( Figures 1-3 The second liner 120 surrounds the second trench filling layer 118. In other embodiments, either the first liner 138 or the second liner 120 is omitted.

[0038] In some embodiments, the full-depth isolation structure 132 includes a tab structure 402 located at the interface between the full-depth isolation structure 132 and the partial-depth isolation structure 134. Specifically, each tab structure 402 is defined by a first width W1 that is the same as or substantially the same as the width of the adjacent surface of the partial-depth isolation structure 134. Furthermore, the tab structure 402 has a thickness T1 defined along the adjacent surface of the partial-depth isolation structure 134. An elongated segment of the full-depth isolation structure 132 extends from each tab structure 402, wherein each elongated segment of the full-depth isolation structure 132 has a second width W2 smaller than the first width W1. In this way, the outer wall of the partial-depth isolation structure 134 is laterally surrounded by the full-depth isolation structure 132. In various embodiments, when viewed in a top view, the partial-depth isolation structure 134 is square, and the full-depth isolation structure 132 is cross-shaped.

[0039] Thus, the first trench filling layer 136 and the second trench filling layer 118 are in direct contact at the interface along the outer sidewall of the second trench filling layer 118. In a further embodiment, the first liner ( Figures 1-3 138) is disposed around the outer periphery of the first ditch filling layer 136 and may be disposed between the first ditch filling layer 136 and the second ditch filling layer 118.

[0040] Figure 5 Show along Figure 4 The line B-B' intercepts Figure 4 Cross-sectional views of some embodiments of the image sensor 400. Figure 5 The second trench fill layer 118 of the partial-depth isolation structure 134 is shown to directly contact the first trench fill layer 136 of the full-depth isolation structure 132. It should be understood that... Figures 4-5 One or more alternative features can also be applied Figures 1-3 Conversely, the same applies. For example, Figures 1-3 It can include Figure 4 The splice structure 402 and / or such Figures 4-5 The first lining 138 or the second lining 120 shown is omitted, or Figures 4-5 It can include Figures 1-3 The first lining is 138 or the second lining is 120.

[0041] Figure 6 Showing with Figure 5 The image sensor 400 is shown in cross-sectional views corresponding to some embodiments of the image sensor 600, wherein a portion of the depth isolation structure 134 has a wedge shape. In various embodiments, Figure 6 The sectional view is along Figure 4embodiments, the width of the portion of the depth isolation structure 134 aligned with the backside surface 104b of the substrate 104 is wider than the bottom surface of the portion of the depth isolation structure 134. The second liner 120 is disposed along the sidewalls and the bottom surface of the second trench fill layer 118. The inner opposing sidewalls of the full depth isolation structure 132 laterally surrounding the floating diffusion node 126 extend away from each other at the backside surface 104b of the substrate 104 relative to the frontside surface 104f of the substrate. Figure 6 FIGS. 7A-7D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 2 FIGS. 8A-8D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 6 FIGS. 9A-9D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 2 FIGS. 10A-10D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 5 FIGS. 11A-11D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. FIGS. 12A-12D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104.

[0042] FIGS. 13A-13D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figures 7-9 FIGS. 14A-14D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 7 FIGS. 15A-15D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 9 FIGS. 16A-16D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 8 FIGS. 17A-17D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 9 FIGS. 18A-18D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 9 FIGS. 19A-19D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figures 7-9 FIGS. 20A-20D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. FIGS. 21A-21D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104.

[0043] FIGS. 22A-22D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 7 FIGS. 23A-23D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104.

[0044] FIGS. 24A-24D illustrate various views of some embodiments of the image sensor 700 having a dual-depth isolation structure extending into the backside surface 104b of the substrate 104. Figure 8As seen in [the diagram], the full-depth isolation structure 132 and the partial-depth isolation structure 134 are connected to form a continuous structure. A dielectric substrate 702 is disposed along the bottom surface of the full-depth isolation structure 132 and the partial-depth isolation structure 134. In this way, the dielectric substrate 702 separates the trench isolation structure 130 from the interconnect structure 102. Furthermore, the dielectric substrate 702 is disposed between the partial-depth isolation structure 134 and the top of the floating diffusion node 126. The image sensor 700 has the advantage of a continuous trench isolation structure 130, thereby avoiding the processing defects of forming the full-depth isolation structure 132 and the partial-depth isolation structure 134 in different processing steps, thus improving isolation and photodetector performance.

[0045] Figure 10 A top view showing some other embodiments of an image sensor 1000 with alternative features of a dual-depth isolation structure. Figure 10 An array of four photodetectors out of a plurality of photodetectors 122 is shown, each photodetector 122 surrounding a corresponding floating diffusion node 126. Each array of four photodetectors is laterally surrounded by a full-depth isolation structure 132, and a liner 1002 is disposed along the sidewalls of the full-depth isolation structure 132 and the partial-depth isolation structure 134. The partial-depth isolation structure 134, which may be configured as a P-BDTI structure, is disposed above the floating diffusion node 126. The full-depth isolation structure 132 may be an F-FDTI structure and extends from the outer sidewall of the partial-depth isolation structure 134 between the arrays of four photodetectors. Figure 10 The cross-sectional view at line B-B' is similar. Figure 5 The image sensor 400. Because each array of four photodetectors in the plurality of photodetectors 122 is completely surrounded by a full-depth isolation structure 132, the subarray of four photodetectors has enhanced isolation characteristics compared to other configurations.

[0046] Figures 11-33 Various views 1100-3300 illustrate some embodiments of a method for forming an image sensor, the image sensor including an isolation structure having full-depth isolation structures and partial-depth isolation structures with different depths. Although the reference method describes... Figures 11-33 The various views shown are 1100-3300, but it should be understood that... Figures 11-33 The structure shown is not limited to the method described, but can exist independently of it. Furthermore, although Figures 11-33 The actions are described as a series of actions, but it should be understood that these actions are not limited, as the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0047] like Figure 11As shown in cross-sectional view 1100, one or more ion implantation processes are performed to form a deep well region 128, a shallow well region 124, and a plurality of photodetectors 122 in a substrate 104. In some embodiments, the substrate 104 may be, for example, or include a bulk silicon substrate, single-crystal silicon, epitaxial silicon, silicon-germanium (SiGe), or another suitable semiconductor material and / or include a first doping type (e.g., p-type). The substrate 104 includes a front surface 104f opposite to a rear surface 104b. Furthermore, the substrate 104 has a first doping type (e.g., p-type). In various embodiments, the ion implantation process includes: selectively forming a mask layer (not shown) over the front surface 104f of the substrate 104; performing a selective ion implantation process based on the mask layer to implant one or more dopants within the substrate 104; and then performing a removal process to remove the mask layer (not shown). In some embodiments, a first ion implantation process can be performed to form a plurality of photodetectors 122, such that the photodetectors 122 include a second doping type (e.g., n-type) opposite to the first doping type; a second ion implantation process can be performed to form a shallow well region 124, such that the shallow well region 124 includes the first doping type; and a third ion implantation process can be performed to form a deep well region 128, such that the deep well region 128 includes the second doping type (e.g., n-type). In various embodiments, the photodetectors 122 have a higher doping concentration than the deep well region 128. In yet another embodiment, the third ion implantation process can be performed without forming a mask layer over the substrate 104.

[0048] like Figure 12 As shown in the cross-sectional view 1200, the front surface 104f of the substrate 104 is patterned to form a full-depth isolation opening 1202 extending into the front surface 104f. Figure 13 Show Figure 12A top view 1300 of some embodiments of the cross-sectional view 1200. In some embodiments, the patterning process includes: forming a mask layer (not shown) over a front surface 104f of a substrate 104; etching the substrate 104 according to the mask layer (e.g., by dry etching and / or wet etching); and removing the mask layer. In some embodiments, the etchant is reactive ion etching or other plasma etching techniques. However, etching processes may introduce physical defects such as roughness or pitting into the substrate, thereby altering the electrical properties of the substrate. Therefore, in some embodiments, a high-temperature process can be used after etching to repair any etching damage. For example, a surface passivation process and / or additional chemical treatments can be applied to the substrate 104 and the full-depth isolation opening 1202 to stabilize the etched surface and reduce the impact of etching-induced damage. In various embodiments, the full-depth isolation opening 1202 has a depth 1204 that is less than the full depth (i.e., height) of the substrate 104. In a further embodiment, the full-depth isolation opening 1202 is formed such that when viewed from above, the full-depth isolation opening 1202 is annular and continuously laterally surrounds a plurality of photodetectors 122 (not shown).

[0049] like Figure 14 As shown in the cross-sectional view 1400, a first liner 1402 is formed within the full-depth isolation opening 1202 and on the substrate 104. Figure 15 Show Figure 14 A top view 1500 of some embodiments of the cross-sectional view 1400. A first liner 1402 is formed on the front surface 104f of the substrate and extends into the full-depth isolation opening 1202. The first liner 1402 is formed by a deposition process. In some embodiments, the first liner 1402 is formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), thermal oxidation, etc. In some embodiments, the first liner 1402 may be an oxide or include oxides, such as silicon dioxide, high-k dielectrics, etc. In some embodiments, an annealing process is performed after the formation of the first liner 1402. The annealing process can reduce defects in the substrate 104 caused by the etchant forming the full-depth isolation opening 1202.

[0050] like Figure 16 and Figure 17 As shown in cross-sectional views 1600 and 1700, a first trench filling layer 136 is formed between the inner sidewalls of the first liner 138 and above the front surface 104f of the substrate 104. Figure 18 Show Figure 16 and Figure 17 Top view 1800 of some embodiments, wherein Figure 16 The sectional view 1600 is along Figure 18 The line A-A' is intercepted, andFigure 17 The sectional view 1700 is along Figure 18 The line B-B' was cut off before the formation of the first trench filling layer 136. Figure 14 The first liner 1402 undergoes a removal process, such as a planarization process. In some embodiments, the removal process applied to the first liner 1402 is a chemical mechanical planarization (CMP) process. Subsequently, the first liner 1402 is removed from the front surface 104f of the substrate 104, thereby... Figure 14 A first liner 138 is formed within the full-depth isolation opening 1202. In some embodiments, the first trench filling layer 136 is formed by CVD, PVD, ALD, or other processes. In some embodiments, the full-depth trench filling layer may be an oxide or include oxides, such as silicon dioxide, high-k dielectrics, etc. It should be understood that in some embodiments, Figure 15 The first lining 138 is omitted (see, for example, see...). Figure 4 and Figure 5 Moreover, the full-depth trench filling layer is formed in Figure 14 Between the inner sidewalls of the substrate 104 within the full-depth isolation opening 1202.

[0051] like Figure 19 and Figure 20 As shown in cross-sectional views 1900 and 2000, a floating diffusion node 126 is formed within a substrate 104, a plurality of pixel devices 112 are formed on the substrate 104, and an interconnect structure 102 is formed along the front surface 104f of the substrate 104. This partially defines a plurality of pixel sensors 103 on the substrate 104, wherein each pixel sensor 103 includes a plurality of photodetectors 122 surrounding the floating diffusion node 126 and a plurality of pixel devices 112 on the substrate 104. Figures 16-18The substrate 104 is subjected to a removal process, such as a planarization process, to form a first trench-filling layer 136 having a top surface flush with the front surface 104f of the substrate 104. Floating diffusion nodes 126 are formed according to a mask (not shown) and a doping process on the front surface 104f of the substrate 104. Floating diffusion nodes 126 are formed between adjacent photodetectors in a plurality of photodetectors 122. In some embodiments, the floating diffusion nodes 126 are formed by a second doping type (e.g., n-type) that is different from the doping type of the substrate 104 but the same as the doping type of the photodetector 122. The interconnect structure 102 includes an interconnect dielectric structure 106, a plurality of conductive metal lines 108, and a plurality of vias 110. In various embodiments, the interconnect dielectric structure 106 can be formed by one or more deposition processes, such as PVD, CVD, ALD, another suitable growth or deposition process, or any combination of the foregoing processes. In another embodiment, the plurality of conductive metal lines 108 and / or the plurality of vias 110 may be formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, or some other suitable processes.

[0052] like Figure 21 and Figure 22 As shown in the sectional views 2100 and 2200, Figure 19 and Figure 20 The structure is rotated 180 degrees, and a thinning process is performed on the rear surface 104b of the substrate 104. The thinning process reduces the height of the substrate 104 from an initial substrate height 104i to a height 104h. In some embodiments, the height 104h of the substrate 104 is in the range of about 2 μm to about 6 μm, in the range of about 2 μm to 4 μm, in the range of about 4 μm to 6 μm, or some other suitable value. In other embodiments, the thinning process includes performing a CMP process, a mechanical polishing process, another suitable thinning process, or any combination of the foregoing processes. In various embodiments, the thinning process removes at least a portion of the deep well region 128 and / or is completed until the first trench filling layer 136 is exposed. After the thinning process, the full-depth isolation structure 132 has a first depth d1, which may, for example, be equal to the height 104h of the substrate 104 (i.e., the full depth).

[0053] like Figure 23 and Figure 24 As shown in cross-sectional views 2300 and 2400, the rear surface 104b of the substrate 104 is patterned to form a first partial depth isolation opening 2302 extending into the rear surface 104b. Figure 25 Show Figure 23 and Figure 24 Top view 2500 of some embodiments, wherein Figure 23 The sectional view 2300 is alongFigure 25 The line A-A' is intercepted, and Figure 24 The sectional view 2400 is along Figure 25 The patterning process is taken from line B-B'. In some embodiments, the patterning process includes: forming a mask layer (not shown) over the rear surface 104b of the substrate 104; etching (e.g., by dry etching) the substrate 104 according to the mask layer; and removing the mask layer. After etching, from a top view (e.g., Figure 25 Viewed from above, the first partial depth isolation opening 2302 is separated from the full-depth isolation structure 132 by the substrate 104. In some embodiments, the first partial depth isolation opening 2302 is formed such that when viewed from above, the first partial depth isolation opening 2302 is cross-shaped and separated between adjacent photodetectors in the plurality of photodetectors 122 (e.g., Figure 25 Alternatively, the first depth isolation opening 2302 can be square (e.g., Figure 4 The first partial depth isolation opening 2302 is formed with a front surface separated from the floating diffusion node 126 by the substrate 104. In some embodiments, the etching that forms the first partial depth isolation opening 2302 is referred to as the primary etch. In some embodiments, the primary etch is performed using low-bias dry etching, such that the substrate 104 is etched in a controlled manner to provide an etch profile with precision.

[0054] like Figure 26 and Figure 27 As shown in cross-sectional views 2600 and 2700, a patterning process with controlled extension etching is performed on the rear surface 104b of the substrate 104 to form a second partial depth isolation opening 2602, which is an extension of the first partial depth isolation opening 2302. Figure 28 Show Figure 26 and Figure 27 Top view 2800 of some embodiments, wherein Figure 26 The sectional view 2600 is along Figure 28 A-A' cut and Figure 27 The sectional view 2700 is along Figure 28In some embodiments, the patterning process includes: forming a mask layer (not shown) over the backside surface 104b of the substrate 104; performing a controlled extension etch of the substrate 104 according to the first partial depth isolation 2302 above the mask layer, for example by wet etching; and removing the mask layer. In some embodiments, the controlled extension etch is performed according to a wet etchant including tetramethyl ammonium hydroxide (TMAH) wet etchant. In some embodiments, the substrate 104 is exposed to the TMAH wet etchant for 10 seconds. As such, the first partial depth isolation 2302 is extended (e.g., in depth and / or width). In some embodiments, the first partial depth isolation 2302 is formed with a registration or alignment error. The second partial depth isolation 2602 formation process allows for precise control in extending the first partial depth isolation 2302 to address the registration error and achieve the co-design objectives of the isolation structure.

[0055] In further embodiments, the second partial depth isolation 2602 is formed by a single etch process including forming a mask layer over the substrate 104 and performing a low bias etch (e.g., dry etch) of the backside surface 104b of the substrate 104 (not shown). In such embodiments, the low bias etch is performed at a bias lower than the bias of the etch process. Figure 12

[0056] As shown in cross-sectional views 2900 and 3000 of FIGS. 29 and 30, respectively, a deposition process is performed to form the partial depth isolation structure 134 within the second partial depth isolation 2602. Figure 29 Figure 30 A top view 3100 of some embodiments of the partial depth isolation structure 134 of FIG. 31, where Figure 31 Figure 29 Figure 30 A cross-sectional view 2900 of the partial depth isolation structure 134 of FIG. 29 is taken along line A-A’ of FIG. 31, and Figure 29 A cross-sectional view 3000 of the partial depth isolation structure 134 of FIG. 30 is taken along line B-B’ of FIG. 31. Figure 31 Figure 30 Figure 31 The cross-sectional view 3000 at line B-B’ of FIG. 30 and the top view 3100 of FIG. 31 of some embodiments of the partial depth isolation structure 134 show that the second partial depth isolation 2602 is formed according to a second partial depth. Figure 30 Figure 31 Figure 29 ​​​​​​​​The method steps are discussed. The second liner 120 is deposited over the substrate 104, covering the full-depth isolation structure 132 and lining the second partial-depth isolation opening 2602. Subsequently, the backside surface 104b of the substrate and the second partial-depth isolation opening 2602 are filled with a trench dielectric, forming a second trench fill layer 118 between the inner sidewalls of the second liner and an upper dielectric layer 140 over the substrate 104. The second liner 120 and the second trench fill layer 118 form a partial-depth isolation structure 134 having a second depth d2 that is less than a first depth dl, where the first depth dl extends from over the floating diffusion node 126 to the backside surface 104b of the substrate 104.

[0057] In some embodiments, the upper dielectric layer 140 is an extension of the second trench fill layer 118. In some embodiments, the second liner 120, the second trench fill layer 118, and / or the upper dielectric layer 140 are deposited by a CVD process, a PVD process, an ALD process, and / or some other suitable deposition or growth process, respectively. In some embodiments, the second liner 120, the second trench fill layer 118, and / or the upper dielectric layer 140 can be or can include an oxide such as silicon dioxide, a high-k dielectric, etc. It should be understood that in some embodiments, the second liner 120 can be omitted (e.g., see Figure 4 and Figure 5 ), and the second trench fill layer 118 is formed between the inner sidewalls of the substrate 104 within the second partial-depth isolation opening 2602. In cases where the full-depth isolation structure 132 extends from the frontside surface 104f of the substrate 104 to the backside surface 104b of the substrate 104, the full-depth isolation structure 132 can be referred to as a full front-side DTI (F-FDTI) structure. Figures 26-28

[0058] As shown in cross-sectional views 3200 and 3300, Figure 32 and Figure 33 , a dielectric mesh structure 144 is formed over the substrate 104, a plurality of optical filters 146 is formed over the plurality of photodetectors 122, and a plurality of microlenses 148 is formed over the plurality of optical filters 146. In some embodiments, the process of forming the conductive mesh structure 142 and the dielectric mesh structure 144 includes depositing (e.g., by PVD, CVD, ALD, electroplating, electroless plating, etc.) a metal mesh layer over the upper dielectric layer 140, depositing (e.g., by PVD, CVD, ALD, etc.) a dielectric mesh layer on the metal mesh layer, forming a mask layer (not shown) over the dielectric mesh layer, patterning the metal mesh layer and the dielectric mesh layer according to the mask layer, and performing a removal process to remove the mask layer. In some embodiments, the optical filters 146 and the microlenses 148 can be deposited by, for example, CVD, PVD, ALD, or some other suitable deposition or growth process.​

[0059] Figures 34-40 Showing according to, for example Figure 8 Cross-sectional views 3400-4000 of an alternative embodiment of the method for forming an image sensor, wherein a full-depth isolation structure 132 and a partial-depth isolation structure 134 are formed from the rear surface 104b of a substrate 104. Figure 34 Provided Figure 22 Other embodiments, wherein not in Figures 14-22 The first lining 138 and the first trench filling layer 136 are formed in the full-depth isolation opening 1202, but in Figure 12 A sacrificial dielectric structure 3402 is formed within the full-depth isolation opening 1202. The sacrificial dielectric structure 3402 can be formed by, for example, CVD, PVD, ALD, etc. In some embodiments, the sacrificial dielectric structure 3402 may be or may include oxides (e.g., silicon dioxide), or some other dielectric material, etc.

[0060] like Figure 35 As shown in cross-sectional view 3500, a multilayer dielectric structure 3512 is formed on the rear surface 104b of the substrate 104. The multilayer dielectric structure 3512 includes a dielectric liner 3502, a barrier layer 3504, an intermediate layer 3506, and a photoresist 3508. The multilayer dielectric structure 3512 can be formed by one or more deposition processes, including one or more of CVD, PVD, or ALD processes. The layers of the multilayer dielectric structure 3512 can be or may include one or more of oxides or dielectric materials. In some embodiments, the dielectric liner 3502 is formed with a thickness of 50 angstroms (Å) to 150 Å, the barrier layer 3504 is formed with a thickness of 1000 Å to 12000 Å, the intermediate layer 3506 is formed with a thickness of 400 Å to 500 Å, and the photoresist 3508 is formed with a thickness of 800 Å to 1000 Å. A photoresist removal process (not shown) is performed to form an opening 3510, which exposes the rear surface of the intermediate layer 3506 aligned above the floating diffusion node 126.

[0061] like Figure 36 As shown in the cross-sectional view 3600, the rear surface 104b of the substrate 104 is etched to form a first partial depth isolation opening 3602 extending into the rear surface 104b. Figure 36 The various aspects correspond to according to Figure 23 The processing steps described are as follows. In some embodiments, the first partial depth isolation opening 3602 is formed such that when viewed from above, the first partial depth isolation opening 3602 is cross-shaped and separated between adjacent photodetectors in the plurality of photodetectors 122 (e.g., Figure 25). Or, alternatively, the first partial depth isolation opening 3602 can be square shaped (e.g., Figure 4 ). The first partial depth isolation opening 3602 is formed with a front side surface that is separated from the floating diffusion node 126 by the substrate 104. In some embodiments, the etch that forms the first partial depth isolation opening 3602 is referred to as an initial etch. In some embodiments, the initial etch is performed with a low bias voltage such that the substrate 104 is etched in a controlled manner, thereby providing an etch profile with precision.

[0062] As shown in cross-sectional view 3700, a patterned process with a controlled extension etch is performed on the backside surface 104b of the substrate 104 to form a second partial depth isolation opening 3702 that is an extension of the first partial depth isolation opening 3602. As shown in cross-sectional view 3700, the patterned process is performed with a dielectric liner 3502 disposed along the backside surface 104b of the substrate 104. In some embodiments, the controlled extension etch is performed according to a wet etchant, including a TMAH wet etchant. In some embodiments, the substrate 104 is exposed to the TMAH wet etchant for 10 seconds. In this way, the first partial depth isolation opening 3602 is extended. In some embodiments, the first partial depth isolation opening 3602 is formed with a registration or alignment error. The second partial depth isolation opening 3702 formation process allows for precise control of the extension of the first partial depth isolation opening 3602 to address the registration error and achieve the co-design objectives of the isolation structure. Figure 37 Figure 36

[0063] As shown in cross-sectional view 3800, a removal process is performed to remove the sacrificial dielectric structure 3402. The removal process can include performing a dry etch, a wet etch, or some other suitable process. In some embodiments, the removal process is a wet removal process using a diluted hydrofluoric acid (DHF) etchant. In some embodiments, the sacrificial dielectric structure 3402 is exposed to the DHF etchant for up to 500 seconds to 800 seconds. In other embodiments, the sacrificial dielectric structure 3402 is exposed to the DHF etchant for 550 seconds to 750 seconds. After the removal process, a portion of the substrate 3802 is located above and around the floating diffusion node 126, and the front side surface of the interconnect structure 102 is exposed. Figure 38 Figure 37 As shown in cross-sectional view 3800, a removal process is performed to remove the sacrificial dielectric structure 3402. The removal process can include performing a dry etch, a wet etch, or some other suitable process. In some embodiments, the removal process is a wet removal process using a diluted hydrofluoric acid (DHF) etchant. In some embodiments, the sacrificial dielectric structure 3402 is exposed to the DHF etchant for up to 500 seconds to 800 seconds. In other embodiments, the sacrificial dielectric structure 3402 is exposed to the DHF etchant for 550 seconds to 750 seconds. After the removal process, a portion of the substrate 3802 is located above and around the floating diffusion node 126, and the front side surface of the interconnect structure 102 is exposed.

[0064] As shown in cross-sectional view 3800, a removal process is performed to remove the sacrificial dielectric structure 3402. The removal process can include performing a dry etch, a wet etch, or some other suitable process. In some embodiments, the removal process is a wet removal process using a diluted hydrofluoric acid (DHF) etchant. In some embodiments, the sacrificial dielectric structure 3402 is exposed to the DHF etchant for up to 500 seconds to 800 seconds. In other embodiments, the sacrificial dielectric structure 3402 is exposed to the DHF etchant for 550 seconds to 750 seconds. After the removal process, a portion of the substrate 3802 is located above and around the floating diffusion node 126, and the front side surface of the interconnect structure 102 is exposed. Figure 39 ​​​As shown in cross-sectional view 3900, a dielectric liner 702 is deposited over the substrate 104 and the interconnect structure 102, and a trench fill layer 3902 is deposited over the dielectric liner 702. In some embodiments, the dielectric liner 702 layer and the trench fill layer 3902 are deposited by a CVD process, a PVD process, an ALD process, and / or some other suitable deposition or growth process, respectively. The dielectric liner 702 and the trench fill layer 3902 can be or can include one or more of an oxide or a dielectric material. The trench fill layer 3902 forms the partial-depth isolation structure 134 over the floating diffusion node 126 and the full-depth isolation structure 132 on adjacent sides of the partial-depth isolation structure 134, where the partial-depth isolation structure 134 and the full-depth isolation structure 132 are continuous connected structures formed from the backside of the substrate. Forming the sacrificial dielectric structure 3402 from the frontside of the dielectric helps to precisely control the profile of the trench fill layer 3902 of the dual-depth trench structure. In the case where the full-depth isolation structure 132 extends from the backside surface 104b of the substrate to the frontside surface 104f (not shown) of the substrate, the full-depth isolation structure 132 can be referred to as a full back-side DTI (F-BDTI) structure.

[0065] As Figure 40 shown in cross-sectional view 4000, the conductive grid structure 142 and the dielectric grid structure 144 are formed over the substrate 104. In addition, a plurality of optical filters are formed over the plurality of photodetectors, and a plurality of microlenses are formed over the plurality of optical filters (not shown). The above-mentioned features are formed as described with reference to Figures 32-33 .

[0066] Although Figures 11-40 corresponding to a particular cross-sectional view or top-down view, it is to be understood that Figures 11-40 modifications can be made to the illustrated embodiments in accordance with the description and Figures 1-10 associated cross-sectional views or top-down views. As such, some features from one of the Figures 11-40 may be omitted, or additional features can be added in accordance with the Figures 1-10 .

[0067] Figure 41Some embodiments of a method 4100 of forming an image sensor or semiconductor device including isolation structures having full-depth isolation structures and partial-depth isolation structures of different depths formed from a front side and a back side of a substrate in accordance with the present disclosure are shown. Although the method 4100 is shown and / or described as a series of acts or events, it is understood that the method is not limited by the order of the acts or events. Thus, in some embodiments, the acts can be performed in other orders, and / or at least some acts can be performed concurrently. In addition, in some embodiments, the acts or events shown can be subdivided into multiple acts or events, which can be performed at separate times or concurrently with other acts or sub-acts. In some embodiments, some of the acts or events shown can be omitted, and other acts or events not shown can be included.

[0068] At act 4102, a plurality of photodetectors are formed within the substrate. Figure 11 A cross-sectional view 1100 corresponding to some embodiments of act 4102 is shown.

[0069] At act 4104, a front side surface of the substrate is patterned to define full-depth isolation openings extending into the front side surface of the substrate. Figures 12-13 Views 1100-1200 corresponding to some embodiments of act 4104 are shown.

[0070] At act 4106, a first liner is formed over the front side surface and within the full-depth isolation openings. Figures 14-15 Views 1400-1500 corresponding to some embodiments of act 4106 are shown.

[0071] At act 4108, a first trench fill layer is formed between inner sidewalls of the first liner and over the front side surface of the substrate. Figures 16-18 Views 1600-1800 corresponding to some embodiments of act 4108 are shown.

[0072] At act 4110, a plurality of pixel devices are formed within the interconnect structures on the front side surface of the substrate. In addition, a floating diffusion node is formed within the front side of the substrate. Figures 19-20 Cross-sectional views 1900-2000 corresponding to some embodiments of act 4110 are shown.

[0073] At act 4112, a thinning process is performed on a back side surface of the substrate, wherein the thinning process exposes the full-depth trench structures. Figures 21-22 and Figures 43-44 Views 2100-2200 and 4300-4400 corresponding to some embodiments of act 4112 are shown.

[0074] At action 4114, the backside surface of the substrate is patterned to define a first partial-depth isolation opening extending into the backside surface of the substrate. Figures 23-25 and Figures 45-46 Views 2300-2500 and 4500-4600 are shown that correspond to some embodiments of action 4114.

[0075] At action 4116, the backside surface of the substrate is controlled-etch to form an extended second partial-depth isolation opening as a first partial-depth isolation opening. Figures 26-28 and Figures 47-48 Views 2600-2800 and 4700-4800 are shown that correspond to some embodiments of action 4116.

[0076] At action 4118, a second liner and a second trench fill layer are deposited in the second partial-depth isolation opening, thereby forming a partial-depth isolation structure. Figures 29-31 Views 2900-3100 are shown that correspond to some embodiments of action 4118.

[0077] At action 4120, a plurality of optical filters are formed over the backside surface and a plurality of microlenses are formed over the plurality of optical filters. Figures 32-33 Views 3200-3300 are shown that correspond to some embodiments of action 4120.

[0078] Figure 42 A method 4200 of forming an image sensor including isolation structures having full-depth isolation structures and partial-depth isolation structures of different depths and formed from a backside of a substrate is shown in accordance with the present disclosure. Although the method 4200 is shown and / or described as a series of actions or events, it is understood that the method is not limited to the order or actions shown. Thus, in some embodiments, the actions can be performed in a different order than shown, and / or can be performed concurrently. Further, in some embodiments, the shown actions or events can be subdivided into multiple actions or events that can be performed at separate times or concurrently with other actions or sub-actions. In some embodiments, some of the shown actions or events can be omitted, and other non- shown actions or events can be included.

[0079] At action 4202, a sacrificial dielectric structure is formed from a frontside of the substrate laterally surrounding a floating diffusion node. Figure 34 A cross-sectional view 3400 is shown that corresponds to some embodiments of action 4202.

[0080] At action 4204, a multilayer dielectric structure is formed over a backside surface of the substrate. Figure 35 A cross-sectional view 3500 is shown that corresponds to some embodiments of action 4204.

[0081] At action 4206, etching is performed to form a first partial depth isolation opening extending into the rear surface of the substrate. Figure 36 A cross-sectional view 3600 is shown, corresponding to some embodiments of action 4206.

[0082] At action 4208, a controlled extension etching is performed on the rear surface of the substrate to form a second partial depth isolation opening as an extension of the first partial depth isolation opening. Figure 37 A cross-sectional view 3700 is shown, corresponding to some embodiments of action 4208.

[0083] At action 4210, a removal process is performed to remove the sacrificial dielectric structure, thereby forming a portion of the substrate disposed above and around the floating diffusion node. Figure 38 A cross-sectional view 3800 is shown, corresponding to some embodiments of action 4210.

[0084] At action 4212, a dielectric substrate and trench filling layer are deposited on a portion of the substrate and interconnect structure. Figure 39 A cross-sectional view 3900 is shown, corresponding to some embodiments of action 4212.

[0085] At action 4214, a conductive mesh structure and a dielectric mesh structure are formed on the trench filling layer. Figure 40 A cross-sectional view 4000 is shown, corresponding to some embodiments of action 4214.

[0086] Figures 43-48 Explanation shown Figures 11-40 Various views 4300-4800 of alternative embodiments of some aspects of the method flow shown, wherein the full-depth isolation structure 132 includes one or more patch structures 402. Figure 43 and Figure 44 The sectional view 4300 and top view 4400 show the formation as shown in the figure. Figure 4 The full-depth isolation structure 132 of the one or more patch structures 402. Figure 45 and Figure 46 Cross-sectional view 4500 and top view 4600 show a first etching performed between opposing sidewalls of one or more tab structures 402 to form a first partial depth isolation opening 2302. Several aspects of forming the first partial depth isolation opening 2302 are based on... Figures 23-25 The following explanation is provided. When viewed from the top view 4400, the first part of the depth isolation opening 2302 is basically rectangular in shape. Figure 47 and Figure 48Cross-sectional view 4700 and top view 4800 show a second etch within the first partial-depth isolation trench 2302 to form a second partial-depth isolation trench 2602. The second etch is a controlled-etch extension on the backside surface 104b of the substrate 104, as described according to Figures 26-28 The one or more tab structures 402 prevent the second etch from removing too much of the substrate 104 adjacent to the photodetectors 122 when forming the second partial-depth isolation trench 2602. Subsequently, a partial-depth isolation structure is formed according to the method steps as shown or described, where the partial-depth isolation structure is formed to have a substantially rectangular shape as shown according to Figures 29-31 Figure 4

[0087] Accordingly, in some embodiments, the present disclosure relates to an image sensor that includes partial-depth isolation structures and full-depth isolation structures within a substrate to enhance photodetector performance. Moreover, the full-depth isolation structures can be formed from the front side of the substrate that includes the photodetectors, and the partial-depth isolation structures can be formed from the backside of the substrate.

[0088] In some embodiments, the present disclosure relates to a semiconductor device having a plurality of photodetectors disposed within a substrate, where the substrate has a front side opposite a backside. The semiconductor device has a floating diffusion node disposed in the substrate, where the plurality of photodetectors are disposed around the floating diffusion node. The semiconductor device has a trench isolation structure disposed within the substrate and laterally surrounding the plurality of photodetectors. The trench isolation structure includes a first isolation structure disposed in the substrate and having a first depth, where the first isolation structure is disposed between adjacent photodetectors and laterally offset with respect to the floating diffusion node. The semiconductor device has a second isolation structure extending from the backside of the substrate to the floating diffusion node, where the second isolation structure is directly above the floating diffusion node and has a second depth that is less than the first depth.

[0089] ​​In some embodiments, a liner is disposed between the first isolation structure and the second isolation structure, where the liner is disposed on the backside of the substrate and covers the top surface of the first isolation structure. In some embodiments, the second isolation structure has a substantially rectangular shape when viewed from above, and where the first isolation structure surrounds the second isolation structure. In some embodiments, the first depth is equal to a height of the substrate. In some embodiments, a photodetector of the plurality of photodetectors has four sides, where the first isolation structure extends substantially parallel to a first side and a second side of the four sides of the photodetector, and where the second isolation structure extends substantially parallel to the first side and the second side. In some embodiments, a top surface of the second isolation structure has a first width, and a top surface of the first isolation structure has a second width, where the second width is less than the first width. In some embodiments, a bottom surface of the second isolation structure has a third width, and a bottom surface of the first isolation structure has a fourth width, where the third width is less than the fourth width.

[0090] In some embodiments, the present disclosure relates to an image sensor having an interconnect structure disposed on a front side surface of a substrate, where the substrate has a backside surface opposite the front side surface. The image sensor has a plurality of photodetectors disposed within the substrate. The image sensor has a partial depth isolation structure disposed within the substrate between the plurality of photodetectors, where the partial depth isolation structure extends from the backside surface of the substrate toward the interconnect structure, and where the partial depth isolation structure has a bottom surface above the front side surface of the substrate. The image sensor has a full depth isolation structure disposed within the substrate between the plurality of photodetectors, where the full depth isolation structure extends through an entire depth of the substrate, and where the full depth isolation structure and the partial depth isolation structure together form at least a linear mesh segment of trench isolation structures.

[0091] In some embodiments, the partial depth isolation structure extends laterally over the backside surface of the substrate and covers the full depth isolation structure and the plurality of photodetectors. In some embodiments, the full depth isolation structure includes a plurality of tab structures around an outer sidewall of the partial depth isolation structure. In some embodiments, adjacent photodetectors of the plurality of photodetectors are separated by the partial depth isolation structure and the full depth isolation structure. In some embodiments, a photodetector of the plurality of photodetectors has a first pair of edges opposite each other and a second pair of edges opposite each other when viewed from above, where the first pair of edges is rotated 90 degrees with respect to the second pair of edges, and the first pair of edges face the partial depth isolation structure, and where the second pair of edges face the full depth isolation structure. In some embodiments, the image sensor further includes a floating diffusion node disposed within the substrate on the front side surface of the substrate, where the floating diffusion node is directly below the bottom surface of the partial depth isolation structure. In some embodiments, the floating diffusion node is laterally surrounded by the full depth isolation structure.

[0092] In some embodiments, the disclosure relates to a method of forming an image sensor, the method including forming a photodetector within a substrate, where the substrate has a front side surface opposite a back side surface. The method includes patterning the front side surface of the substrate to form a full-depth isolation structure opening through the substrate, where the full-depth isolation structure opening surrounds a portion of the photodetector. The method includes forming a full-depth isolation structure within the full-depth isolation structure opening and patterning the back side surface of the substrate to form a partial-depth isolation structure opening surrounding a portion of the photodetector. The partial-depth isolation structure opening has a bottom surface that is above the front side surface of the substrate, and the partial-depth isolation structure opening is formed between opposing edges of the full-depth isolation structure. The method includes forming a partial-depth isolation structure within the partial-depth isolation structure opening.

[0093] In some embodiments, the photodetector includes four sides, and the full-depth isolation structure opening is formed to surround a first portion of each of the four sides of the photodetector. In some embodiments, the partial-depth isolation structure opening is formed to surround a second portion of each of the four sides of the photodetector, the second portion being different from the first portion of each of the four sides of the photodetector occupied by the full-depth isolation structure. In some embodiments, a liner is formed within the partial-depth isolation structure opening and separates the full-depth isolation structure from the partial-depth isolation structure opening, and the partial-depth isolation structure is formed on the liner. In some embodiments, the back side surface of the substrate is patterned with a dry etch to form the partial-depth isolation structure opening, and the method further includes wet etching the partial-depth isolation structure opening, and forming the partial-depth isolation structure within the partial-depth isolation structure opening after the wet etching, where the wet etching extends the partial-depth isolation structure opening in depth and width. In some embodiments, the partial-depth isolation structure is further formed on the back side surface of the substrate and covers the full-depth isolation structure.

[0094] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the present application; even though the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized by comprising: Including: a plurality of photodetectors disposed within a substrate, wherein the substrate has a front side opposite a back side; a floating diffusion node disposed in the substrate, wherein the plurality of photodetectors are disposed around the floating diffusion node; and a trench isolation structure disposed within the substrate and laterally surrounding the plurality of photodetectors, the trench isolation structure comprising: a first isolation structure disposed in the substrate and having a first depth, wherein the first isolation structure is disposed between adjacent photodetectors and is laterally offset with respect to the floating diffusion node; and a second isolation structure extending from the back side of the substrate to the floating diffusion node, wherein the second isolation structure is directly above the floating diffusion node and has a second depth that is less than the first depth. a liner disposed between the first isolation structure and the second isolation structure, wherein the liner is disposed on the back side of the substrate and covers a top surface of the first isolation structure.

2. The semiconductor device according to claim 1, wherein When viewed from above, the second isolation structure has a substantially rectangular shape, and wherein the first isolation structure surrounds the second isolation structure.

3. The semiconductor device according to claim 1, wherein The first depth is equal to a height of the substrate.

4. The semiconductor device according to claim 1, wherein A photodetector of the plurality of photodetectors has four sides, wherein the first isolation structure extends substantially parallel to a first side and a second side of the four sides of the photodetector, and wherein the second isolation structure extends substantially parallel to the first side and the second side.

5. The semiconductor device according to claim 1, wherein Including:

6. An image sensor, comprising: an interconnect structure disposed on a front side surface of a substrate, wherein the substrate has a back side surface opposite the front side surface; a plurality of photodetectors disposed within the substrate; a partial depth isolation structure disposed within the substrate between the plurality of photodetectors, wherein the partial depth isolation structure extends from the back side surface of the substrate to the interconnect structure, and wherein the partial depth isolation structure has a bottom surface above the front side surface of the substrate; and a full depth isolation structure disposed within the substrate between the plurality of photodetectors, wherein the full depth isolation structure extends through an entire thickness of the substrate, and wherein the full depth isolation structure and the partial depth isolation structure together at least form a linear grid segment of trench isolation structures. The partial depth isolation structure extends laterally over the back side surface of the substrate and covers the full depth isolation structure and the plurality of photodetectors.

7. The image sensor of claim 6, wherein, The full depth isolation structure includes a plurality of tab structures around an outer sidewall of the partial depth isolation structure.

8. The image sensor of claim 6, wherein, Adjacent photodetectors of the plurality of photodetectors are separated by the partial depth isolation structure and the full depth isolation structure.

9. The image sensor of claim 6, wherein, When viewed from above, a photodetector of the plurality of photodetectors has a first pair of edges opposite each other and a second pair of edges opposite each other, wherein the first pair of edges is rotated 90 degrees with respect to the second pair of edges, and 10. The image sensor of claim 6, wherein, the first pair of edges faces the partial depth isolation structure, and wherein the second pair of edges faces the full depth isolation structure. ​

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