Electrostatic chuck surface structure

Abstract

The utility model relates to an electrostatic chuck surface structure used in a semiconductor manufacturing process. The surface structure includes a substrate, a first protective coating disposed on the substrate, and a second protective coating disposed on the first protective coating. The first protective coating is deposited on the substrate and is made of a material selected from the group consisting of metal oxides, fluorides and nitrides. As a universal protective screen, the protective screen is resistant to abrasion, corrosion and heat effect. The second protective coating is deposited on the first protective coating having a hardness higher than that of the first protective coating, providing enhanced wear resistance.

Description

TECHNICAL FIELD

[0001] The present utility model generally relates to the field of semiconductor manufacturing equipment, and more particularly to a surface structure of an improved electrostatic chuck (ESC) used in a semiconductor processing chamber. BACKGROUND

[0002] In the manufacturing process of semiconductor wafers, electrostatic chucks are widely used in various processing chambers to secure wafers during operations such as heating, adsorption, and rotation. These chucks are often surface treated to improve their performance and durability.

[0003] One common surface treatment method is thermal spraying. However, as semiconductor manufacturing technology advances, the requirements for surface treatment of electrostatic chucks become increasingly stringent, and traditional thermal spraying techniques often result in insufficient density and hardness of the coating. This is a major disadvantage. In addition, because of the frequent loading and unloading of wafers, the bumps of the chuck can wear out, which in turn can cause particulate matter to adhere to the back of the wafer, affecting the yield of subsequent processes.

[0004] Another common surface treatment method is to use sintering technology for preparation, although sintered electrostatic chucks can provide higher hardness, but the overall manufacturing cost of the electrostatic chuck is also significantly increased.

[0005] Therefore, how to design an electrostatic chuck with a surface structure that has high hardness, high density, and wear resistance, while also being cost-effective, is a problem worth considering for those with ordinary knowledge in the field. SUMMARY

[0006] The purpose of the present utility model is to provide an electrostatic chuck surface structure that has high hardness, high density, and wear resistance, and also has a relatively low manufacturing cost.

[0007] The present utility model solves the limitations and challenges of traditional electrostatic chucks (ESCs) used in semiconductor manufacturing, introducing an innovative surface structure. This surface structure includes a substrate, a first protective coating disposed on the substrate, and a second protective coating disposed on the first protective coating. The second protective coating has a higher hardness than the first protective coating, thereby providing enhanced wear resistance.

[0008] The present utility model further distinguishes that the porosity of the second protective coating is less than the porosity of the first protective coating. This feature ensures higher density, which helps to improve the overall durability and performance of the electrostatic chuck. The first protective coating is selected from the group consisting of metal oxides, fluorides, and nitrides, and has a thickness of between 100 μm and 250 μm. This layer serves as a strong base, protecting the underlying substrate and improving the overall wear resistance and corrosion resistance of the ESC.

[0009] The second protective coating is also selected from the group consisting of metal oxides, fluorides and nitrides, but is thinner, ranging between 0.5 μm and 20 μm. Despite its thinness, this layer provides super hardness, ranging between 1000 HV and 1500 HV, and porosity less than 1%. These properties make it very effective in reducing particle contamination from the chuck to the wafer, thus increasing the yield of the subsequent semiconductor processes.

[0010] In addition to the structural properties, the method of forming the electrostatic chuck surface structure includes forming a first protective coating on the substrate, then forming a second protective coating on the first protective coating, and optimizing the specific deposition conditions for each layer to achieve the desired properties.

[0011] By providing a combination of high hardness, low porosity and wear resistance, and in a cost-effective manner, the present invention significantly advances the state of the art of electrostatic chuck technology in semiconductor manufacturing.

[0012] The present invention has the following advantages: high hardness, high density and wear resistance, and at the same time, it can reduce the cost of manufacturing electrostatic chuck surface structure.

[0013] In order to make the above features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 A schematic diagram of the electrostatic chuck surface structure 10 of the present embodiment is shown.

[0015] Figure 2 A flowchart of the method of forming the electrostatic chuck surface structure 10 is shown. DETAILED DESCRIPTION

[0016] Please refer to Figure 1 , Figure 1 A schematic diagram of the electrostatic chuck surface structure 10 of the present embodiment is shown. The present invention provides an advanced surface structure of an electrostatic chuck (ESC) designed with a unique surface structure to meet the stringent requirements of modern semiconductor manufacturing processes. The electrostatic chuck surface structure 10 of the present embodiment is composed of three main components: a substrate 12, a first protective coating 13 and a second protective coating 14.

[0017] The substrate 12 is usually made of conductive or semiconductor material, which can generate an electrostatic field that fixes the semiconductor wafer in place during various manufacturing processes. In the present embodiment, the substrate 12 can be made of aluminum, silicon or other commonly used metals and ceramic materials in the industry.

[0018] The substrate 12 is the base element of the electrostatic chuck and plays a critical role in the overall performance and functionality of the electrostatic chuck. Typically, a protective layer is deposited on the substrate 12, and the substrate 12 is responsible for generating the electrostatic field that holds the semiconductor wafer in place during the manufacturing process.

[0019] In this embodiment, the material of the substrate 12 is chosen taking into account several factors. First, the material must be electrically conductive or semiconductive to generate a sufficient electrostatic field. Common materials include aluminum, silicon, and other metals or ceramics compatible with semiconductor manufacturing environments. The material should also have high thermal conductivity to allow for uniform heating of the wafer, ensuring process consistency.

[0020] In addition, the structural integrity of the substrate 12 is another important consideration. It must be strong enough to withstand the mechanical stresses generated during wafer loading and unloading, as well as the thermal stresses generated during wafer heating. Furthermore, the substrate 12 is often designed with a specific geometry to optimize its mechanical properties, such as tensile strength and fracture toughness.

[0021] Additionally, the substrate 12 is typically subjected to a series of surface preparation steps before the protective layer is deposited. These can include cleaning, etching, and priming to ensure the surface is free of contaminants and conducive to the adhesion of subsequent layers. The surface roughness of the substrate 12 can also be controlled within a specific range to optimize the bond strength between the substrate 12 and the first protective coating 13.

[0022] The electrical properties of the substrate 12, such as resistivity and dielectric constant, are also adjusted to optimize electrostatic holding force. These properties are particularly important when handling extremely thin or irregularly shaped wafers, as they ensure that the wafer is securely held in place throughout the manufacturing process.

[0023] Please refer again to Figure 1 , the first protective coating 13 is directly disposed on the surface of the substrate 12, the first protective coating 13 is used to protect the substrate 12 from wear and corrosion, thereby extending the service life of the electrostatic chuck (ESC).

[0024] In this embodiment, the first protective coating 13 is formed using thermal spraying techniques, such as atmospheric plasma spraying (APS), suspended plasma spraying (SPS), or vacuum plasma spraying (VPS). Each method has its own advantages and limitations, and the choice of method is often dependent on factors such as the desired coating thickness, porosity, and hardness. The thickness of the first protective coating 13 ranges from 100 μm to 250 μm. This range is intended to provide sufficient protection to the substrate 12 while also allowing for efficient heat conduction.

[0025] The material of the first protective coating 13 is selected from the group consisting of metal oxides, fluorides and nitrides, such as Ti02, AI203, YF3, Er203, Gd203, Y203, etc. These materials are well known for their excellent thermal stability, corrosion resistance and mechanical properties, making them ideal for this application.

[0026] The hardness of the first protective coating 13 is designed to be in the range of 400 HV to 700 HV, providing a balance between mechanical strength and flexibility.

[0027] Since the first protective coating 13 requires a relatively thick thickness, a thermal spraying technique is employed to increase its deposition rate, accompanied by different process designs, with a porosity range of 1% to 5%.

[0028] The deposition process is carefully controlled to achieve the desired properties of the first protective coating 13. For example, an arc current of 200 A to 600 A and a turntable speed of 5 RPM to 30 RPM can be used. The selection of carrier gas, such as argon, nitrogen or helium, and its flow rate are also optimized to ensure high-quality deposition.

[0029] By carefully designing and implementing the first protective coating 13, the performance and lifetime of the electrostatic chuck are significantly improved. The first protective coating 13 has sufficient thickness and strength to increase the wear resistance and corrosion resistance of the substrate.

[0030] Please refer to Figure 1 , the second protective coating 14 is disposed on top of the first protective coating 13. The second protective coating 14 is much thinner than the first layer, with a thickness ranging from 0.5 μm to 20 μm. Although the second protective coating 14 is relatively thin, this layer provides super-hardness ranging from 1000 HV to 1500 HV, thereby providing superior wear resistance and reducing the risk of particle contamination.

[0031] The second protective coating 14 is formed using a physical vapor deposition (PVD) technique, so that the second protective coating 14 forms a high-density and high-hardness coating. In detail, the physical vapor deposition process is highly controlled to achieve the desired properties of the second protective coating 14. For example, parameters such as chamber temperature, deposition rate, ion source plasma power and gas flow are finely adjusted. For example, the chamber temperature can range from 25°C to 200°C, the deposition rate from 0.1 nm / s to 1.5 nm / s, and other parameters.

[0032] In addition, the physical vapor deposition (PVD) method, such as electron beam physical vapor deposition (E-Gun PVD) or ion-assisted electron beam physical vapor deposition, each provides specific advantages in terms of coating quality and process control.

[0033] While the material of the second protective coating 14 is also selected from the group consisting of metal oxides, fluorides and nitrides, similar to the first protective coating 13, but due to the use of vacuum physical vapor deposition techniques, a higher hardness and lower porosity of the protective coating can be achieved, the second protective coating 14 is designed to have a porosity of less than 1%, which is significantly lower than the porosity of the first protective coating 13. This low porosity helps to increase the hardness and wear resistance of the second protective coating 14, making it an ideal choice for long-term contact with semiconductor wafers, and is also very effective in reducing particle contamination from the chuck to the wafer.

[0034] In summary, the second protective coating 14, as the topmost layer, is in direct contact with the semiconductor wafer, which provides super-strong hardness, low porosity and excellent wear resistance, thereby improving the corrosion and wear resistance of the first protective coating 13. Therefore, the electrostatic chuck surface structure 10 of the present embodiment solves the shortcomings of the existing electrostatic chuck, not only enhances the wear resistance, but also significantly reduces the risk of particle contamination, reduces the overall manufacturing cost, and improves the yield and reliability of the semiconductor manufacturing process.

[0035] Referring to Figure 2 , Figure 2 a flowchart of a method of forming the electrostatic chuck surface structure 10 is shown. In the following, how the electrostatic chuck surface structure 10 of the present embodiment is manufactured will be described in detail.

[0036] First, referring to step S1, the first protective coating 13 is deposited on the substrate 12 using a thermal spraying technique under certain conditions, such as atmospheric plasma spraying (APS), suspended plasma spraying (SPS) and vacuum plasma spraying (VPS), which are described in detail as follows:

[0037] 1. Atmospheric plasma spraying (APS) is one of the most commonly used techniques for depositing the first protective coating 13. In this method, the coating material is fed into a high-temperature plasma jet, which pushes the molten particles towards the substrate 12. APS is usually carried out at atmospheric pressure and is suitable for a wide range of materials, including metal oxides, fluorides and nitrides. Process parameters such as arc current (200A-600A), carrier gas flow rate (30L / min-200L / min) and rotation speed (5RPM-30RPM) can be adjusted to achieve the desired coating properties.

[0038] 2. Suspended plasma spraying (SPS) is a variant of conventional plasma spraying, but uses a fine powder particle suspension in a liquid medium. This method allows the deposition of layers with unique microstructure and enhanced properties. SPS is particularly suitable for depositing coatings with complex compositions, such as mixed oxides. The process conditions are similar to APS, but additional controls may be required to manage the supply rate of the suspension and the plasma parameters.

[0039] Three, Vacuum Plasma Spraying (VPS) is performed in a controlled vacuum environment, which minimizes oxidation and contamination during the spraying process. This method is well suited for materials that are sensitive to atmospheric conditions. VPS allows for tighter control of the microstructure and properties of the coating. The vacuum pressure in the process ranges from 5.0E1 to 1.0E-2 Torr, and a pre-heat temperature can be set between 100°C and 300°C to improve the adhesion of the coating.

[0040] Also, the plasma spray deposition process is controlled by several parameters to achieve the desired coating properties. These include an arc current from 200 A to 600 A, a substrate rotation speed from 5 RPM to 30 RPM, and a carrier gas gas type such as argon, nitrogen, or helium. Also, the gas flow is adjusted between 30 L / min and 200 L / min, and the process pressure can vary from 1 atmosphere to 1.0E-2 Torr. The plasma spray technique is well suited for depositing thick coatings ranging from 100 μm to 250 μm, providing strong protection for the metal components of the electrostatic chuck.

[0041] Additionally, an optional but often beneficial step in the process is the pre-heating of the substrate 12. The pre-heat temperature of the substrate 12 can range from 100°C to 3000°C, which helps to improve the adhesion and density of the deposited layer. Also, when the material of the substrate 12 is different from the thermal properties of the coating material, the step of pre-heating the substrate 12 is highly beneficial for the adhesion between the substrate 12 and the first protective coating 13.

[0042] Next, referring to step S2, a second protective coating 14 is deposited on the first protective coating 13 using a physical vapor deposition (PVD) technique under optimized conditions. The physical vapor deposition (PVD) technique is, for example, electron beam physical vapor deposition (E-Gun PVD) or ion assisted electron beam physical vapor deposition, which are described in detail as follows:

[0043] One, electron beam physical vapor deposition (E-Gun PVD) is a highly specialized thin film deposition method. In this technique, an electron beam is used to evaporate the source material, which then condenses on the substrate 12 to form a coating. The process is performed in a high vacuum chamber, allowing for precise control of the microstructure and properties of the film. The deposition conditions can be finely tuned, including the chamber temperature (25°C to 200°C), the deposition rate (0.1 nm / s to 1.5 nm / s), and the process pressure (1.0E-2 to 1.0E-6 Torr). This method is particularly well suited for depositing coatings with high hardness (1000-1500 HV) and low porosity (<1%).

[0044] II. Ion Assisted Electron Beam Physical Vapor Deposition, which is an advanced variant of E-Gun PVD, where an ion source is used to assist the deposition process. Ion assistance helps to improve the density, adhesion, and other mechanical properties of the film. Ion source parameters such as plasma power, electron beam current (0-1500 mA), and voltage (100 V-1500 V) can be adjusted to achieve the desired coating properties. Argon and oxygen gas flow can be adjusted from 5 sccm to 50 sccm and 10 sccm to 200 sccm.

[0045] Where either Electron Beam Physical Vapor Deposition (E-Gun PVD) or Ion Assisted Electron Beam Physical Vapor Deposition is well suited for depositing the second protective coating 14 consisting of metal oxide, fluoride, or nitride, with a thickness ranging from 0.5 microns to 20 microns.

[0046] Furthermore, the aforementioned optimized conditions include chamber temperature, deposition rate, and process pressure. For example, chamber temperature (25°C to 200°C), deposition rate (0.1 nm / s to 1.5 nm / s), and ion source plasma power. Also, electron beam current can range from 0 to 1500 mA, and voltage from 100 V to 1500 V.

[0047] Additionally, the physical vapor deposition (PVD) technique uses carrier gas such as argon and oxygen with a flow ranging from 5 sccm to 50 sccm and 10 sccm to 200 sccm, while the process pressure is maintained between 1.0E-2 to 1.0E-6 Torr. By optimizing the deposition method, material, and process parameters under the conditions, the second protective coating 14 is formed with superior properties that exceed the stringent requirements of semiconductor manufacturing, greatly improving performance and extending the life of the electrostatic chuck.

[0048] Therefore, compared to the conventional sintering method used to form the surface structure of the electrostatic chuck, the present method selects the thermal spraying technology and the physical vapor deposition method to generate the first protective coating 13 and the second protective coating 14, which can more effectively reduce the cost of manufacturing the surface structure 10 of the electrostatic chuck.

[0049] In summary, the present utility model provides an electrostatic chuck surface structure and its forming method, which not only meets the performance and durability requirements of modern semiconductor manufacturing process, but also exceeds these requirements. Therefore, the present utility model represents a major progress in the field, providing a combination of high hardness, low porosity, and excellent wear resistance in a cost-effective manner.

[0050] Although the utility model has disclosed as above with preferable embodiments, it is not used to limit the utility model, anyone with ordinary knowledge in the art can make some changes and decorations without departing from the spirit and scope of the utility model, therefore the protection scope of the utility model is defined as the application patent range in the preceding annex.

Claims

1. An electrostatic chuck surface structure, characterized by, Comprising: a substrate; a first protective coating disposed on a surface of the substrate; and a second protective coating disposed on the first protective coating; wherein the second protective coating has a hardness greater than the hardness of the first protective coating, and the second protective coating has a porosity of less than 1%. The second protective coating has a porosity less than the porosity of the first protective coating.

2. The electrostatic chuck surface structure of claim 1, wherein, The first protective coating has a thickness between 100 μm and 250 μm.

3. The electrostatic chuck surface structure of claim 1, wherein, The first protective coating has a hardness between 400 HV and 700 HV.

4. The electrostatic chuck surface structure of claim 1, wherein, The first protective coating has a porosity between 1% and 5%.

5. The electrostatic chuck surface structure of claim 1, wherein, The second protective coating has a thickness between 0.5 μm and 20 μm.

6. The electrostatic chuck surface structure of claim 1, wherein, The second protective coating has a hardness between 1000 HV and 1500 HV.

7. The electrostatic chuck surface structure of claim 1 wherein, ​

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