Chip packaging structure
By combining a substrate with a pre-fabricated silicon wafer circuit board into a chip packaging structure, and utilizing TSV vias and horizontal copper pillars to achieve chip interconnection, the mechanical stability, thermal management, and testing challenges in traditional chip stacking packaging are solved, achieving simple packaging and efficient heat dissipation.
Patent Information
- Application Number
- CN202520158787.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-01-23
AI Technical Summary
Traditional chip stacking and packaging structures have problems such as difficulty in controlling mechanical stability, complexity in thermal management and heat dissipation, and difficulty in chip testing and fault isolation.
The structure combines a substrate with a pre-fabricated silicon wafer circuit board. The substrate includes circuit segments and flexible segments. The silicon wafer circuit board has TSV vias and horizontal copper pillars. Chip interconnection is achieved by setting vertical TSV vias and horizontal copper pillars on the silicon wafer circuit board. The flexible segments of the substrate can be folded to connect chips.
It reduces packaging difficulty, simplifies the chip stacking process, improves mechanical stability and heat dissipation efficiency, and facilitates testing and fault isolation.
Smart Images
Figure CN223885636U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the technical field of semiconductor packaging, especially relates to a chip packaging structure. BACKGROUND
[0002] With the continuous development of semiconductor technology, chip packaging technology is also continuously progressing. In the manufacture of semiconductor integrated circuits, with the miniaturization and multifunctionalization of electronic devices, the stacking density and integration of chips are becoming higher and higher.
[0003] The traditional chip stacking packaging structure has realized interconnection through the upper and lower stacking mode combined with the TSV through hole technology, that is, another chip is stacked above one chip, and the stacking of the chips is realized through the silicon wafer interlayer with TSV through holes. This stacking mode can realize higher integration and smaller volume, but it also increases the difficulty of packaging, and the following problems also exist:
[0004] 1. The mechanical stability control of the multilayer chip stacking structure is difficult;
[0005] 2. The chip heat management and heat dissipation solution is complex;
[0006] 3. Chip testing and fault isolation and positioning are difficult.
[0007] Therefore, there is an urgent need for a chip packaging structure with reasonable structure and without increasing the difficulty of packaging. INVENTION CONTENTS
[0008] The utility model discloses a chip packaging structure, which forms TSV vertical copper columns and horizontal copper columns on a silicon wafer, as well as an RDL rewiring layer, to form a prefabricated silicon wafer circuit board. The prefabricated silicon wafer circuit board has I / O interfaces on the front and side surfaces, which facilitates the mounting of chips and simplifies the structure. This reduces the packaging difficulty caused by vertical chip stacking, facilitates testing, fault isolation and positioning, and also facilitates heat dissipation.
[0009] To achieve the above-mentioned purpose, the utility model provides a chip packaging structure, which comprises:
[0010] A substrate, which comprises a circuit segment and a flexible segment, is used for mounting chips;
[0011] At least one prefabricated silicon wafer circuit board is mounted on the front surface of the circuit segment of the substrate. The silicon wafer circuit board comprises a silicon wafer and a rewiring layer on the front surface of the silicon wafer. The silicon wafer is provided with a plurality of longitudinal TSV through holes. A plurality of horizontal copper columns are arranged at the edge of the back surface of the silicon wafer. The horizontal copper columns are connected to the rewiring layer through the TSV through holes. Conductive bumps are arranged at the end of the TSV through holes on the back surface of the silicon wafer.
[0012] Wherein, the first chip is mounted on the surface of the redistribution layer of the silicon wafer circuit board, and the second chip is mounted on the flexible section of the substrate, then the flexible section is bent towards the silicon wafer circuit board, and the second chip is connected with the horizontal copper column.
[0013] Preferably, the middle position of the substrate is the circuit section, and the edge position on both sides is the flexible section.
[0014] Preferably, the thickness of the circuit section is 400-1500 mu m, and the thickness of the flexible section is 50-200 mu m.
[0015] Preferably, the silicon wafer circuit board is provided with 2-6 layers.
[0016] Preferably, the spacing between the conductive bumps on the back of the silicon wafer is 50-200 mu m.
[0017] Preferably, a plurality of grooves are arranged at the edge of the back of the silicon wafer, and the grooves are electroplated with copper to form horizontal copper columns.
[0018] Preferably, the height of the horizontal copper column is flush with the back of the silicon wafer, and the width is 20-50 mu m.
[0019] Preferably, the diameter of the TSV through hole is 20-50 mu m.
[0020] Compared with the prior art, the utility model has the following beneficial effects:
[0021] 1、The substrate is arranged as a circuit section and a flexible section in the utility model, so that the front surface of the circuit section can mount a chip, the flexible section can also mount a chip, then it can be bent to the side of the silicon wafer circuit board to realize connection, the overall structure is simple, the packaging difficulty is low, it is not necessary to stack chips in the vertical direction, so the problem of serious heat accumulation in the chip will not occur.
[0022] 2、The multi-layer prefabricated silicon wafer circuit board is ingeniously used to install to the substrate to realize the interconnection between the chips, and the interconnection between the chips is realized by arranging the longitudinal TSV through hole and the horizontal copper column on the prefabricated silicon wafer circuit board, so that the production is simple, the structure is ingenious, and the connection of the TSV through hole and the horizontal copper column is relatively stable. DETAILED DESCRIPTION
[0023] Figure 1 It is a schematic view of the chip packaging structure in the utility model;
[0024] Figure 2 It is Figure 1 The structure schematic view of the substrate in the utility model;
[0025] Figure 3 It is Figure 1 The structure schematic view of the silicon wafer circuit board in the utility model;
[0026] Figure 4For Figure 3 Schematic diagram of the back structure of the middle silicon wafer circuit board;
[0027] Figure 5 For Figure 1 Schematic diagram of the structure of the middle substrate flexible section before bending.
[0028] The drawing reference: substrate-1, circuit section-101, flexible section-102, silicon wafer circuit board-2, silicon wafer-201, rewiring layer-202, TSV through hole-203, horizontal copper column-204, conductive bump-205, first chip-3, second chip-4. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical scheme and advantages of the utility model more clear, the technical scheme of the present application will be described clearly and completely below in conjunction with the drawings.
[0030] As Figure 1 shown, the present application discloses a kind of chip packaging structure, it includes substrate 1 and at least one layer of prefabricated silicon wafer circuit board 2, at least one layer of prefabricated silicon wafer circuit board 2 is attached to the front of substrate 1 circuit section 101;First chip 3 is attached on the surface of the rewiring layer 202 of silicon wafer circuit board 2, after second chip 4 is attached on the flexible section 102 of substrate 1, flexible section 102 is bent to the direction of silicon wafer circuit board 2, and the horizontal copper column 204 of second chip 4 and silicon wafer circuit board 2 is connected.
[0031] As Figure 2 shown, the substrate 1 in the utility model adopts the structure that circuit section 101 and flexible section 102 are combined.The middle position of substrate 1 is circuit section 101, and the edge position (opposite side, adjacent side can) of both sides is flexible section 102, and flexible section 102 is arranged in the two side edges opposite circuit section 101 in the present application.The thickness of circuit section 101 is 400 μm-1500 μm, and the thickness of flexible section 102 is 50 μm-200 μm.Circuit section 101 and flexible section 102 are arranged in substrate 1, so that the front of circuit section 101 can be attached chip, and flexible section 102 can also be attached chip, which can be folded to the side of silicon wafer circuit board 2 after that, realize connection, overall structure is simple, and packaging difficulty is low, and it is not necessary to stack chip in vertical direction, so that the problem of serious internal heat accumulation of chip does not occur.
[0032] As Figure 3 shown, silicon wafer circuit board 2 includes silicon wafer 201 and the rewiring layer 202 arranged on the front of silicon wafer 201, silicon wafer 201 is provided with a plurality of longitudinal TSV through holes 203, a plurality of horizontal copper columns 204 are arranged at the edge of the back of silicon wafer 201, the horizontal copper column 204 is connected with the rewiring layer 202 through the TSV through hole 203, and the end of the TSV through hole 203 of the back of silicon wafer 201 is provided with a conductive bump 205.
[0033] The prefabricated silicon wafer circuit board 2 structure in the utility model is that TSV through hole 203 is made on the silicon wafer 201 first, and multiple grooves are opened at the edge position of the back surface of the silicon wafer 201, the grooves are electroplated with copper, and horizontal copper column 204 is formed. The height of the horizontal copper column 204 is flat with the back surface of the silicon wafer 201, and the width is set between 20 μm-50 μm. The diameter of the TSV through hole 203 is set between 20 μm-50 μm. The width of the horizontal copper column 204 is almost the same as the diameter of the TSV through hole 203, preferably, so as to ensure the stability of the connection between the horizontal copper column 204 and the TSV through hole 203. When necessary, the front and back surfaces of the silicon wafer 201 can be thinned, and the thickness is generally maintained at 50 μm-200 μm. Then, the front surface of the silicon wafer 201 is made of the rewiring layer 202, and the line width and distance of the rewiring layer 202 are set at 5 μm-20 μm. Finally, the conductive bumps 205 are arranged at the end of the TSV through hole 203 of the back surface of the silicon wafer 201, and the spacing between the conductive bumps 205 is 50 μm-200 μm. Figure 4 The back surface schematic diagram of the silicon wafer circuit board 2 is shown.
[0034] According to actual needs, the prefabricated silicon wafer circuit board 2 can be provided with multiple layers, and the multiple silicon wafer circuit boards 2 are interconnected through the conductive bumps 205. In the utility model, the two-layer silicon wafer circuit board 2 is taken as an example. The upper and lower two-layer silicon wafer circuit boards 2 are connected to the circuit section 101 of the substrate 1, the lower silicon wafer circuit board 2 is first connected to the front surface of the circuit section 101, and then the upper silicon wafer circuit board 2 is connected to the lower silicon wafer circuit board 2.
[0035] In the specific implementation of the utility model, the prefabricated two-layer silicon wafer circuit board 2 is stacked up and down and connected to the front surface of the circuit section 101 of the substrate 1. Then the first chip 3 is inverted on the rewiring layer 202 of the top silicon wafer circuit board 2, the second chip 4 is attached to the front surface of the flexible section 102 of the substrate 1, the pin position of the second chip 4 matches the position of the horizontal copper column 204 at the side edge of the two-layer silicon wafer circuit board 2, then the flexible section 102 is bent, so that the second chip 4 is attached to the horizontal copper column 204 at the side edge of the silicon wafer circuit board 2. Finally, the ball is planted on the back surface of the substrate 1 and connected to other circuits. The structure schematic diagram of the flexible section 102 before bending is shown as Figure 5 , and the structure schematic diagram after bending is shown as Figure 1 . The number of the first chip 3 and the second chip 4 can be determined according to actual needs.
[0036] The above is only the preferred embodiment of the utility model, and is not used for limiting the utility model. For the person skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A chip package structure, characterized by, The application relates to a substrate for mounting chips, comprising: a substrate including a circuit segment and a flexible segment; at least one pre-prepared silicon wafer circuit board mounted on the front surface of the circuit segment of the substrate; the silicon wafer circuit board comprises a silicon wafer and a rewiring layer arranged on the front surface of the silicon wafer, the silicon wafer is provided with a plurality of longitudinal TSV through holes, a plurality of horizontal copper columns are arranged at the edge of the back surface of the silicon wafer, the horizontal copper columns are connected with the rewiring layer through the TSV through holes, and conductive bumps are arranged at the end of the TSV through holes of the back surface of the silicon wafer; wherein a first chip is mounted on the surface of the rewiring layer of the silicon wafer circuit board, a second chip is mounted on the flexible segment of the substrate, and then the flexible segment is bent towards the silicon wafer circuit board, and the second chip is connected with the horizontal copper column.
2. The chip package structure of claim 1, wherein, The middle position of the substrate is the circuit segment, and the edge positions on both sides are the flexible segments.
3. The chip package structure of claim 2, wherein, The thickness of the circuit segment is 400-1500 mu m, and the thickness of the flexible segment is 50-200 mu m.
4. The chip package structure according to claim 1 or 3, wherein, The silicon wafer circuit board is provided with 2-6 layers.
5. The chip package structure of claim 4, wherein, The spacing between the conductive bumps on the back surface of the silicon wafer is 50-200 mu m.
6. The chip package structure of claim 5, wherein, A plurality of grooves are arranged at the edge of the back surface of the silicon wafer, the grooves are electroplated with copper, and the horizontal copper columns are formed.
7. The chip package structure of claim 6, wherein The height of the horizontal copper column is flush with the back surface of the silicon wafer, and the width is 20-50 mu m.
8. The chip package structure of claim 7, wherein, The diameter of the TSV through hole is 20-50 mu m.