Semiconductor package
By setting an opening through the solder resist layer on the substrate surface and using a copper layer to guide the flow of molding compound, the feasibility problem of packaging large-size chips in WBGA packaging was solved, achieving a highly efficient packaging effect.
Patent Information
- Application Number
- CN202520188662.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-06
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-02-06
AI Technical Summary
In WBGA packaging structures, as chip size increases, insufficient window size on the substrate leads to ineffective filling of the molding compound, affecting packaging quality. Furthermore, adjusting the window size reduces the substrate's load-bearing capacity.
An opening penetrating the solder resist layer is provided on the first and second surfaces of the substrate, and the good wettability of the copper layer is used to guide the molding compound into the upper and lower molds to form a complete molded body.
Without adjusting the substrate window size, the feasibility of packaging large-size chips was achieved, improving packaging quality and efficiency, and avoiding the problem of reduced substrate load-bearing capacity.
Smart Images
Figure CN223885637U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a semiconductor package. BACKGROUND
[0002] In a WBGA (Windowed Ball Grid Array) packaging structure, the wire bonding surface of a memory chip is in the same direction as the ball planting surface of a substrate, and there is a window in the middle of the substrate to accommodate the wire bonding. The wire bonding is connected to the memory chip and the ball planting surface through the window in the center of the substrate. In the packaging operation, the mold sealing material in the lower mold flows into the upper mold located on the ball planting surface through the window, and fills the upper mold to form a mold sealing body on the upper and lower surfaces of the substrate. However, when the chip exceeds a certain size, the window will be excessively covered, so that the mold sealing material in the lower mold cannot flow into the upper mold through the window, affecting the filling of the ball planting surface mold sealing body.
[0003] If the filling of the ball planting surface mold sealing body is to be achieved, the size of the window needs to be increased, so that the size of the window is larger than the size of the chip, and therefore a corresponding substrate jig needs to be redesigned and developed. Moreover, a large window size reduces the carrying capacity of the substrate, which is likely to cause defective products in the packaging operation. CONTENT OF THE UTILITY MODEL
[0004] Therefore, the present application provides a semiconductor package that can solve the above technical problems and increase the packaging workability of large-size chips without adjusting the size of the window of the substrate.
[0005] A semiconductor package includes:
[0006] a substrate having opposite first and second surfaces;
[0007] a first solder resist layer covering the first surface, an edge of the first solder resist layer being provided with a first opening, the first opening penetrating the first solder resist layer, and part of the first surface being exposed from the first opening;
[0008] a chip located on the second surface;
[0009] a second solder resist layer covering the second surface exposed outside the chip, an edge of the second solder resist layer being provided with a second opening, the second opening penetrating the second solder resist layer, and part of the second surface being exposed from the second opening.
[0010] In some embodiments, the semiconductor package further includes a first plating layer covering the first surface exposed from the first opening.
[0011] In some embodiments, the semiconductor package further includes a second plating layer covering the surface of the first plating layer away from the substrate.
[0012] In some embodiments, the first plating layer or the second plating layer has a height difference from the surface of the substrate facing away from the first surface.
[0013] In some embodiments, the substrate has a through hole penetrating the first surface and the second surface, and the chip covers the through hole.
[0014] In some embodiments, the substrate further comprises a wire, which electrically connects the chip and the first surface through the through hole.
[0015] In some embodiments, the first anti-soldering layer further has a third opening at the edge thereof, and the third opening and the first opening are located at opposite sides of the substrate.
[0016] In some embodiments, the third opening is located corresponding to the first opening.
[0017] In some embodiments, the semiconductor package further comprises a first mold, which covers the first anti-soldering layer and the first surface exposed from the first anti-soldering layer.
[0018] In some embodiments, the semiconductor package further comprises a second mold, which covers the chip and the second surface.
[0019] The present application discloses a semiconductor package. The semiconductor package comprises a substrate with an anti-soldering layer, a chip, a first opening at the edge of the substrate, a third opening at the edge of the substrate, and a through hole penetrating the first surface and the second surface of the substrate. The first opening and the third opening are located at opposite sides of the substrate. The first surface and the second surface of the substrate are exposed from the first opening and the third opening. The chip is electrically connected to the first surface through the through hole. The semiconductor package is encapsulated by a mold. The mold comprises an upper mold and a lower mold. The upper mold is located at the side of the first surface, and the lower mold is located at the side of the second surface. The mold is filled with encapsulating material through the injection ports of the upper mold and the lower mold. The first surface and the second surface exposed from the first opening and the third opening have good wettability with the encapsulating material, which promotes the flow of the encapsulating material into the mold, thereby achieving the encapsulation of the first surface and the second surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 The structure of the substrate, the chip, the first opening, the third opening, and the through hole before encapsulation is provided for an embodiment of the present application.
[0021] Figure 2 The cross section of the substrate along the thickness of the substrate at the first opening is provided for an embodiment of the present application.
[0022] Figure 3 The cross section of the semiconductor package is provided for an embodiment of the present application.
[0023] Explanation of main element symbols
[0024] 1. substrate; 101, first surface; 102, second surface; 103, third surface; 11, first dielectric layer; 12, first copper layer; 13, second copper layer; 14, third copper layer; 15, second dielectric layer; 21, first anti-soldering layer; 22, second anti-soldering layer; 3, chip; 41, first opening; 42, second opening; 43, third opening; 44, fourth opening; 51, first plating layer; 52, second plating layer; 53, third plating layer; 54, fourth plating layer; 6, via hole; 71, first mold seal body; 72, second mold seal body; 100, semiconductor package. DETAILED DESCRIPTION
[0025] Embodiments of the present application are described below in detail. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and cannot be understood as a limitation of the present application. The reagents and materials described in the following embodiments can be obtained from commercial channels.
[0026] In order to more clearly understand the above-mentioned purposes, features and advantages of the embodiments of the present application, the present application will be described in detail below in conjunction with the drawings and specific embodiments. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.
[0027] In the following description, many specific details are set forth in order to provide a thorough understanding of the embodiments of the present application. The described embodiments are merely a part of the embodiments of the present application and are not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the embodiments of the present application.
[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present application belong. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the embodiments of the present application.
[0029] The scheme of the present application is applicable to the case where the size of the chip is greater than the size of the via hole of the substrate. In the packaging operation, the conventional mold only has a lower mold with a mold seal material injection port, and the upper mold does not have a mold seal material injection port. Therefore, the mold seal material injected by the lower mold needs to flow into the upper mold through the window of the substrate to form a mold seal body in the upper mold. Since the size of the chip is greater than the size of the via hole, the mold seal material of the lower mold cannot flow into the upper mold through the window. If the mold seal material injection ports are provided on both the upper mold and the lower mold, the mold seal material is difficult to enter the upper mold and the lower mold through the injection ports due to the poor wettability of the anti-soldering layer on the surface of the substrate and the mold seal material.
[0030] To solve the above problems, the application provides a semiconductor package 100, please refer to Figures 1 to 3 The semiconductor package 100 includes a substrate 1, a first anti-solder layer 21, a second anti-solder layer 22, and a chip 3. The substrate 1 has opposite first and second surfaces 101 and 102. The first anti-solder layer 21 covers the first surface 101. The edge of the first anti-solder layer 21 is provided with a first opening 41, which penetrates the first anti-solder layer 21 and exposes part of the first surface 101. The chip 3 is located on the second surface 102. The second anti-solder layer 22 covers the second surface 102 exposed outside the chip 3, and the edge of the second anti-solder layer 22 is provided with a second opening 42, which penetrates the second anti-solder layer 22 and exposes part of the second surface 102.
[0031] In some embodiments, the substrate 1 includes a first dielectric layer 11 and a copper layer, which is disposed on at least one side of the first dielectric layer 11 and serves as a circuit of the substrate 1.
[0032] Please refer to Figure 3 In this embodiment, the copper layer includes a first copper layer 12 and a second copper layer 13, which are located on opposite surfaces of the first dielectric layer 11. The first dielectric layer 11 exposed on the surface of the first copper layer 12 and the surface of the first copper layer 12 away from the first dielectric layer 11 constitutes the first surface 101. The first dielectric layer 11 exposed on the surface of the second copper layer 13 and the surface of the second copper layer 13 away from the first dielectric layer 11 constitutes the second surface 102.
[0033] The application provides a first opening 41 on the first surface 101 of the substrate 1, which penetrates the first anti-solder layer 21, so that part of the copper layer is exposed from the first opening 41. Copper has good wettability with mold sealing material, so the copper layer exposed from the first opening 41 plays a role of guiding the mold sealing material to smoothly enter the inside of the upper mold and form a mold sealing body in the upper mold. Similarly, a second opening 42 is provided on the second surface 102 of the substrate 1, which penetrates the second anti-solder layer 22, so that part of the copper layer located on the second surface 102 is exposed from the second opening 42. The copper layer exposed from the second opening 42 plays a role of guiding the mold sealing material to smoothly enter the inside of the lower mold and form a mold sealing body in the lower mold, thereby achieving the purpose of forming a mold sealing body on both the first and second surfaces 101 and 102 of the substrate 1.
[0034] In some embodiments, the semiconductor package 100 further includes a first plating layer 51 covering the first surface 101 exposed from the first opening 41.
[0035] In this embodiment, the material of the first plating layer 51 is nickel. Nickel can prevent the first surface 101 exposed to the first opening 41 from being oxidized, and has good wettability with the mold sealant, which helps the mold sealant to enter the mold without hindering the packaging operation. In other embodiments, the material of the first plating layer 51 can also be other materials that can prevent the first surface 101 from being oxidized and have good wettability with the mold sealant.
[0036] In some embodiments, the semiconductor package 100 further comprises a second plating layer 52 covering the surface of the first plating layer 51 away from the substrate 1.
[0037] In this embodiment, the material of the second plating layer 52 is gold. Gold can prevent the first surface 101 exposed to the first opening 41 from being oxidized, and has good wettability with the mold sealant, which helps the mold sealant to enter the mold without hindering the packaging operation. In other embodiments, the material of the second plating layer 52 can also be other materials that can prevent the first surface 101 from being oxidized and have good wettability with the mold sealant.
[0038] Please refer to Figure 2 In some embodiments, the surface of the first plating layer 51 or the second plating layer 52 away from the substrate 1 has a height difference with the surface of the first anti-welding layer 21 away from the substrate 1. When only the first plating layer 51 is provided, the surface of the first plating layer 51 away from the substrate 1 has a height difference with the surface of the first anti-welding layer 21 away from the substrate 1, which helps to increase the flow channel of the mold sealant at the first opening 41 and the second opening 42, so that the mold sealant can better flow into the mold from the first opening 41 and the second opening 42. When the first plating layer 51 and the second plating layer 52 are provided at the same time, the surface of the second plating layer 52 away from the substrate 1 has a height difference with the surface of the first anti-welding layer 21 away from the substrate 1, and for the same reason, such arrangement helps to increase the flow channel of the mold sealant at the first opening 41 and the second opening 42, so that the mold sealant can better enter the mold.
[0039] In some embodiments, the substrate 1 has a through hole 6 penetrating the first surface 101 and the second surface 102. The through hole 6 is used for wire bonding between the chip 3 and the first surface 101. The chip 3 covers the through hole 6, so that the plastic sealant injected into one side of the first surface 101 and the second surface 102 cannot flow into the other side of the first surface 101 and the second surface 102 through the through hole 6.
[0040] In some embodiments, the substrate 1 further comprises a wire (not shown in the figure) electrically connecting the chip 3 and the first surface 101 through the through hole 6.
[0041] Please refer to Figure 2 and Figure 3In some embodiments, the edge of the first anti-welding layer 21 is further provided with a third opening 43, which is located on the opposite side of the substrate 1 from the first opening 41. The first opening 41 serves as the inflow end of the mold sealant, and the third opening 43 serves as the outflow end of the mold sealant. After the mold sealant flows into the first opening 41, it gradually fills the upper mold until the mold is filled, and then flows out of the third opening 43. At the same time, the third opening 43 also has the function of exhausting gas, which can promptly exhaust the gas in the mold and reduce the phenomenon of bubbles or defects in the mold sealant.
[0042] In some embodiments, the third opening 43 is located opposite the first opening 41. The location of the third opening 43 opposite the first opening 41 is conducive to guiding the flow of the mold sealant from the first opening 41 to the third opening 43.
[0043] Please refer to Figure 2 and Figure 3 In some embodiments, the edge of the second anti-welding layer 22 is further provided with a fourth opening 44, which is located on the opposite side of the substrate 1 from the second opening 42. For the lower mold, the second opening 42 serves as the inflow end of the mold sealant, and the fourth opening 44 serves as the outflow end of the mold sealant. After the mold sealant flows into the second opening 42, it gradually fills the lower mold until the lower mold is filled, and then flows out of the fourth opening 44. At the same time, the fourth opening 44 also has the function of exhausting gas, which can promptly exhaust the gas in the mold and reduce the phenomenon of bubbles or defects in the mold sealant.
[0044] In this application, the number of first openings 41, second openings 42, third openings 43, and fourth openings 44 is at least one. The number of first openings 41, second openings 42, third openings 43, and fourth openings 44 can be multiple, which helps to increase the amount of mold sealant and facilitate rapid packaging.
[0045] Please refer to Figure 2 and Figure 3 In some embodiments, the semiconductor package 100 further comprises a third plating layer 53 and a fourth plating layer 54, the third plating layer 53 covers the second surface 102 exposed from the second opening 42, and the fourth plating layer 54 covers the surface of the third plating layer 53 away from the substrate 1.
[0046] Please refer to Figure 2 and Figure 3 In some embodiments, the semiconductor package 100 further comprises a first mold sealant 71, which covers the first anti-welding layer 21 and the first surface 101 exposed from the first anti-welding layer 21. During packaging, the mold sealant filled in the upper mold forms the first mold sealant 71 after solidification, thereby completing the packaging of the first surface 101 of the substrate 1.
[0047] Please refer to Figure 2In some embodiments, the semiconductor package 100 further comprises a second mold body 72 covering the chip 3 and the second surface 102. The mold material filled in the lower mold is cured to form the second mold body 72, thereby completing the encapsulation of the second surface 102 of the substrate 1.
[0048] Referring to Figure 3 and Figure 3 Figure 2 Figure 3 In some embodiments, the substrate 1 further comprises a second dielectric layer 15 and a third copper layer 14. The second dielectric layer 15 covers the surface of the second copper layer 13 facing away from the first dielectric layer 11. The third copper layer 14 covers the surface of the second dielectric layer 15 facing away from the second copper layer 13. The surface of the third copper layer 14 and the surface of the third copper layer 14 facing away from the second dielectric layer 15 constitute a third surface 103. The chip 3 is located on the third surface 103, and the second solder mask layer 22 covers the third surface 103 exposed outside the chip 3. The edge of the second solder mask layer 22 is provided with a second opening 42, and the second opening 42 penetrates the second solder mask layer 22 and exposes part of the third surface 103.
[0049] In this application, the number of layers of the substrate 1 is not limited, and in addition to the single-layer board and double-layer board shown in this application, the substrate 1 can also be a three-layer board, a four-layer board, etc. The corresponding number of layers of the substrate 1 can be used according to the actual design requirements.
[0050] In this application, by opening an opening in the edge of the substrate 1 with a solder mask layer, part of the copper layer of the substrate 1 will be exposed from the opening. During encapsulation, the upper mold is placed on the side where the first surface 101 is located, and the lower mold is placed on the side where the second surface 102 is located, and then the substrate 1 is clamped between the upper mold and the lower mold by the clamp. The mold material is injected through the injection port of the upper mold and the lower mold. Since the copper layer has good wettability with the mold material, the copper layer exposed from the opening can promote the flow of the mold material into the mold, thereby realizing the encapsulation of the substrate 1 and the chip 3, forming a first mold body 71 on the first surface 101 and a second mold body 72 on the second surface 102.
[0051] The above embodiments are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application.
Claims
1. A semiconductor package, characterized by, The semiconductor package comprises: a substrate having opposite first and second surfaces; a first solder resist layer covering the first surface, an edge of the first solder resist layer being provided with a first opening penetrating the first solder resist layer, part of the first surface being exposed from the first opening; a chip located on the second surface; a second solder resist layer covering the second surface exposed outside the chip, an edge of the second solder resist layer being provided with a second opening penetrating the second solder resist layer, part of the second surface being exposed from the second opening.
2. The semiconductor package of claim 1, wherein, The semiconductor package further comprises a first plating layer covering the first surface exposed from the first opening.
3. The semiconductor package of claim 2, wherein, The semiconductor package further comprises a second plating layer covering a surface of the first plating layer away from the substrate.
4. The semiconductor package of claim 3, wherein, A surface of the first plating layer or the second plating layer away from the substrate has a height difference with a surface of the first solder resist layer away from the substrate.
5. The semiconductor package of claim 1, wherein, The substrate has a via penetrating the first and second surfaces, the chip covering the via.
6. The semiconductor package of claim 5, wherein, The substrate further comprises a wire electrically connecting the chip and the first surface through the via.
7. The semiconductor package of claim 1, wherein, An edge of the first solder resist layer is further provided with a third opening, the third opening being located on an opposite side of the substrate from the first opening.
8. The semiconductor package of claim 7, wherein the semiconductor die is mounted on the substrate by flip-chip mounting. The third opening is located corresponding to the first opening.
9. The semiconductor package of claim 1, wherein, The semiconductor package further comprises a first mold encapsulation covering the first solder resist layer and the first surface exposed from the first solder resist layer.
10. The semiconductor package of claim 1, wherein, The semiconductor package further comprises a second mold encapsulation covering the chip and the second surface.